WO2015067148A1 - 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置 - Google Patents

氧化物薄膜晶体管及其制作方法、阵列基板、显示装置 Download PDF

Info

Publication number
WO2015067148A1
WO2015067148A1 PCT/CN2014/090154 CN2014090154W WO2015067148A1 WO 2015067148 A1 WO2015067148 A1 WO 2015067148A1 CN 2014090154 W CN2014090154 W CN 2014090154W WO 2015067148 A1 WO2015067148 A1 WO 2015067148A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoresist
source
thin film
active layer
drain
Prior art date
Application number
PCT/CN2014/090154
Other languages
English (en)
French (fr)
Inventor
崔贤植
林允植
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/652,639 priority Critical patent/US9520422B2/en
Publication of WO2015067148A1 publication Critical patent/WO2015067148A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • Embodiments of the present invention relate to an oxide thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • the Advanced Super Dimension Switch (ADS) mode gradually replaces the TN (Twisted Nematic) liquid crystal mode due to its high transmittance, wide viewing angle, fast response speed and low power consumption. It has become one of the important technologies in the field of liquid crystal display.
  • ADS Advanced Super Dimension Switch
  • the oxide thin film transistor forms a protective layer 13 on the indium gallium zinc oxide (IGZO) layer forming a channel.
  • 1 and 2 are a cross-sectional view and a plan view, respectively, of an oxide thin film transistor.
  • the IGZO layer is connected to the source 2 and the drain 3 through via holes.
  • a via is formed, in order to prevent short-circuiting of the source 2 and the drain 3, a certain interval is left between the source 2 and the drain 3.
  • the active layer in this interval is the channel 12 of the oxide thin film transistor, as indicated by L in FIG.
  • the length of the channel is generally between 9.5 and 10 ⁇ m.
  • Embodiments of the present invention provide an oxide thin film transistor, a method of fabricating the same, an array substrate, and a display device, thereby shortening a channel length of an oxide thin film transistor.
  • At least one embodiment of the present invention provides a method of fabricating an oxide thin film transistor, the method comprising: sequentially forming a gate and a gate insulating layer on a substrate; forming an oxide semiconductor film on the gate insulating layer, in an oxide Forming a first photoresist over the active layer region of the semiconductor film such that a thickness of the first photoresist over the channel region is greater than a thickness of the first photoresist over the non-channel region; removing the region of the non-active layer An oxide semiconductor film, forming a pattern of the active layer, removing the first photoresist over the non-channel region, leaving the first photoresist over the channel region; forming source and drain sequentially above the pattern of the active layer
  • the metal thin film and the second photoresist remove a portion of the portion of the source/drain metal film corresponding to the first photoresist over the channel region and correspond to the first photoresist over the channel region a portion of the portion of the second photoresist such that an edge
  • the oxide semiconductor film is formed on the gate insulating layer, and a first photoresist is formed over the active layer region of the oxide semiconductor film to make the first region above the channel region.
  • the step of the thickness of the photoresist being greater than the thickness of the first photoresist over the non-channel region includes:
  • Forming a first photoresist on the oxide semiconductor film, using a halftone mask to perform full light transmission exposure development on the first photoresist over the non-active layer region, and non-channeling on the active layer region The first photoresist over the region is subjected to semi-transmissive exposure development and the first photoresist over the channel region is subjected to opaque exposure development to form a photoresist of the active layer region.
  • the oxide semiconductor film of the non-active layer region is removed, a pattern of the active layer is formed, the first photoresist over the non-channel region is removed, and the first region above the channel region is retained.
  • the steps of a photoresist include:
  • the first photoresist over the non-channel region is removed using an ashing process, leaving the first photoresist over the channel region.
  • the length of the channel in the oxide thin film transistor is, for example, 5 to 7 ⁇ m.
  • the length of the channel in the oxide thin film transistor is, for example, 5 to 6 ⁇ m.
  • Another embodiment of the present invention also provides an oxide thin film transistor including: a gate, a gate insulating layer formed on one side of the gate, and a gate away from the gate in the gate insulating layer An active layer formed on the side, and a source and a drain formed on a side of the active layer away from the gate insulating layer, the source and the drain being directly connected to the active layer,
  • the active layer is composed of an oxide semiconductor material.
  • the channel length between the source and the drain is, for example, 5 to 7 ⁇ m.
  • the channel length between the source and the drain is, for example, 5 to 6 ⁇ m.
  • Another embodiment of the present invention provides an array substrate comprising the oxide thin film transistor of any of the above.
  • the array substrate further includes: a resin layer and a passivation layer; the resin layer covers the source, the drain, and a channel between the source and the drain
  • the passivation layer is located on a side of the resin layer away from the source and the drain.
  • Another embodiment of the present invention provides a display device comprising the array substrate of any of the above.
  • Figure 1 is a cross-sectional view of an oxide thin film transistor
  • FIG. 2 is a plan view of a semiconductor layer of the oxide thin film transistor shown in FIG. 1;
  • FIG. 3 is a cross-sectional view of an array substrate including an oxide thin film transistor provided by an embodiment of the present invention
  • FIG. 4 is a top plan view of an oxide thin film transistor according to an embodiment of the present invention.
  • 5a-5d are process flow diagrams of a method of fabricating an oxide thin film transistor according to an embodiment of the present invention.
  • 5e is a cross-sectional view of an array substrate including an oxide thin film transistor provided by an embodiment of the present invention.
  • the inventors have noted that since the channel length of the oxide thin film transistor is relatively long, Ultra-high-definition products such as 400PPI to 500PPI, and in a pixel structure having a pixel pitch of 21 ⁇ m or less, it is difficult to apply an oxide thin film transistor.
  • One embodiment of the present invention provides a method of fabricating an oxide thin film transistor, including:
  • Forming an oxide semiconductor film on the gate insulating layer forming a first photoresist over the active layer region of the oxide semiconductor film, so that a thickness of the first photoresist above the channel region is greater than a non-channel region The thickness of the first photoresist;
  • a method for fabricating an oxide thin film transistor provided by an embodiment of the present invention protects an active layer by using a photoresist instead of a protective layer, so that a source and a drain are formed above the active layer, and the source and the drain are ensured.
  • the drain is directly connected to the active layer without the need for vias to be connected to the active layer.
  • the final source-drain pattern is formed by a photoresist strip process, thereby shortening the length of the channel of the oxide thin film transistor.
  • the "partial source/drain metal film corresponding to the first photoresist above the channel region" as used in the embodiment of the present invention refers to a portion of the source and drain metal film opposite to the first photoresist above the channel region, for example It may be a portion of the source-drain metal film directly above the first photoresist above the channel region.
  • a specific process flow of a method for fabricating an oxide thin film transistor according to an embodiment of the present invention includes the following steps.
  • the gate electrode 1 and the gate insulating layer 4 are sequentially formed on the substrate 14 by a patterning process, and the oxide semiconductor film 10 is formed on the gate insulating layer 4.
  • the oxide semiconductor thin film 10 is a thin film made of at least two elements of an element such as oxygen and In (indium), Ga (gallium), Zn (zinc), or Sn (tin).
  • the oxide semiconductor film may be an IGZO (indium gallium zinc oxide) film, an IZO (indium zinc oxide) film, an InSnO (indium tin oxide) film, or an InGaSnO (indium gallium oxide) film.
  • the patterning process used in this step is a known scheme and will not be described herein.
  • the first photoresist 11a is formed on the oxide semiconductor film 10 by a photoresist process, and the first photoresist 11a is exposed and developed using a halftone mask.
  • the first photoresist as a positive photoresist as an example, a portion of the halftone mask corresponding to the non-active layer region is fully transparent, and the halftone mask is correspondingly active.
  • the portion of the non-channel region in the layer region is semi-transmissive, and the portion of the halftone mask corresponding to the channel region is opaque.
  • the first photoresist 11a is exposed and developed by the halftone mask, the first photoresist 11a above the active layer region in FIG. 5b is obtained.
  • the thickness of the first photoresist 11a above the channel region is greater than the thickness of the first photoresist 11a over the non-channel region.
  • the oxide semiconductor film 10 is etched to obtain the active layer 5, and the first photoresist 11a over the active layer region is subjected to an ashing process to retain the first photoresist 11a over the channel region.
  • the first photoresist 11a over the active layer region protects the active layer 5 during etching of the oxide semiconductor film 10.
  • the non-active layer region of the oxide semiconductor film 10 is etched to obtain the active layer 5 as shown in Fig. 5c.
  • the first photoresist 11a over the active layer region is subjected to an ashing process to obtain a channel region as shown in FIG. 5c.
  • the first photoresist 11a, at this time, the length of the photoresist above the channel region is the length of the channel 12 of the oxidized thin film transistor.
  • the thickness of the photoresist above the active layer region is smaller than the thickness of the photoresist above the active layer region before the ashing process.
  • a source/drain metal film is formed over the active layer 5, and the first photoresist 11a above the channel region is entirely covered by the source/drain metal film.
  • a second photoresist 11b is formed over the source/drain metal film.
  • the active layer region between the source 2 and the drain 3 is the channel 12 of the oxide thin film transistor.
  • the distance between the source 2 and the drain 3 is 3 ⁇ m
  • the width w1 of the source 2 located above the first photoresist 11a is 1 to 1.5 ⁇ m
  • the width d2 of the drain 3 located above the first photoresist 11a is 1 to 1.5 ⁇ m.
  • the first photoresist 11a over the channel region may be peeled off together with the portion overlying the first photoresist 11a by a lift-off method.
  • the array substrate including the oxide thin film transistor can be further formed by the following steps, as shown in FIG. 5e.
  • a resin layer 6 is formed over the source 2 and the drain 3 by a patterning process, and a common electrode line 9 is formed over the resin layer 6.
  • the passivation layer 7 and the pixel electrode 8 are formed. Thereby, an array substrate including the oxide thin film transistor provided by the embodiment of the present invention as shown in FIG. 3 is formed.
  • an oxide thin film transistor as shown in FIG. 4 is obtained, and the channel length S can be accurately 5 to 6 ⁇ m. If the accuracy becomes smaller, an oxide thin film transistor having a smaller channel length can be obtained.
  • the oxide thin film transistor When the source/drain metal film covering the edge of the first photoresist 11a over the channel region is peeled off during the above peeling process, some source/drain metal films may be peeled off, so that after the source and drain patterns are obtained.
  • the channel length S in Fig. 4 is 5 to 7 ⁇ m.
  • the known oxide thin film transistor has a channel length of 9.5 to 10 ⁇ m or even more than 10 ⁇ m. Therefore, the oxide thin film transistor provided by the embodiment of the present invention protects the active layer by using a photoresist instead of the protective layer.
  • the photoresist is stripped, thereby making the source and the drain
  • the pole is directly connected to the active layer, shortening the channel length of the oxide thin film transistor.
  • the reduction in channel length can make thin film transistors smaller, thereby increasing the aperture ratio in some high PPI products.
  • Embodiments of the present invention also provide an oxide thin film transistor, as shown in FIGS. 3 and 4.
  • the oxide thin film transistor includes:
  • a gate electrode 1 formed on one side of the substrate 14, a gate insulating layer 4 formed on a side of the gate electrode 1 away from the substrate 14, an active layer 5 formed on a side of the gate insulating layer 4 away from the gate electrode 1, and
  • the source layer 5 is composed of an oxide semiconductor material.
  • the oxide semiconductor material may be IGZO, IZO, InSnO, or InGaSnO or the like.
  • the length S of the channel 12 between the source 2 and the drain 3 is 5 to 6 ⁇ m.
  • the distance between the source 2 and the drain 3 is 3 ⁇ m, and the width w1 of the source 2 located above the first photoresist 11a is 1 to 1.5 ⁇ m, the width d2 of the drain 3 located above the first photoresist 11a is 1 to 1.5 ⁇ m.
  • the length S of the channel 12 between the source 2 and the drain 3 is 5 to 7 ⁇ m.
  • An oxide thin film transistor provided by the embodiment of the invention forms a source and a drain at both ends of the active layer by using a source/drain process to ensure that the source and the drain are directly connected to the active layer without using a via hole.
  • the connection to the active layer shortens the length of the channel of the oxide thin film transistor.
  • the embodiment of the invention further provides an array substrate comprising the oxide thin film transistor of any of the above embodiments.
  • the array substrate provided by the embodiment of the present invention further includes: a resin layer 6 and a passivation layer 7; as shown in FIG.
  • the resin layer 6 covers the source 2, the drain 3 and the channel 12;
  • the passivation layer 7 is located on a side of the resin layer 6 away from the source 2 and the drain 3.
  • the array substrate provided by the embodiment of the present invention further includes: a pixel electrode 8 located above the passivation layer 7 and connected to the drain 3, and a common electrode line 9 located inside the passivation layer 7 and in close contact with the resin layer 6.
  • the embodiment of the invention further provides a display device comprising the array substrate according to any of the above embodiments.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the implementation of the display device can In the above embodiments, the repetition will not be described again.
  • the oxide thin film transistor and the manufacturing method thereof, the array substrate and the display device provided by the invention protect the active layer by using a photoresist instead of the protective layer when forming the preliminary pattern of the source and the drain, and form a final by a photoresist stripping process.
  • the source and drain patterns shorten the channel length of the oxide thin film transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种氧化物薄膜晶体管及其制作方法、阵列基板、显示装置。所述方法包括：在基板上依次形成栅极（1）、栅绝缘层（4）和氧化物半导体薄膜（10）；在氧化物半导体薄膜（10）的有源层区域上方形成第一光刻胶（11a），使沟道区域上方的第一光刻胶比非沟道区域上方的第一光刻胶厚；保留沟道区域上方的第一光刻胶（11a）；在有源层图案的上方依次形成源漏金属薄膜和第二光刻胶（11b），去除源漏金属薄膜的一部分和第二光刻胶（11b）的一部分，使沟道区域上方的第一光刻胶（11a）的边缘被源漏金属薄膜覆盖；得到源极和漏极图案。在形成源漏极初步图案时利用光刻胶代替保护层对有源层进行保护，从而缩短了氧化物薄膜晶体管的沟道长度。

Description

氧化物薄膜晶体管及其制作方法、阵列基板、显示装置 技术领域
本发明的实施例涉及一种氧化物薄膜晶体管及其制作方法、阵列基板、显示装置。
背景技术
在液晶显示技术中，高级超维场转换技术(Advanced Super Dimension Switch，ADS)模式因透过率高、宽视角、响应速度快和功耗低的优点而逐渐取代TN(Twisted Nematic)液晶模式，成为液晶显示领域的重要技术之一。
在ADS模式中，氧化物薄膜晶体管在形成沟道的铟镓锌氧化物(indium gallium zinc oxide，IGZO)层上形成保护层13。图1和图2分别为一种氧化物薄膜晶体管的剖视图和俯视图。在该氧化物薄膜晶体管中，IGZO层通过过孔连接源极2和漏极3。在形成过孔时，为了防止源极2和漏极3的短路，源极2和漏极3间留有一定间隔。该间隔内的有源层即该氧化物薄膜晶体管的沟道12，如图2中的L所指示。在氧化物薄膜晶体管的结构中，该沟道的长度一般在9.5～10μm之间。
发明内容
本发明的实施例提供了一种氧化物薄膜晶体管及其制作方法、阵列基板、显示装置，从而缩短氧化物薄膜晶体管的沟道长度。
本发明的至少一个实施例提供了一种氧化物薄膜晶体管制作方法，该方法包括：在基板上依次形成栅极和栅绝缘层；在所述栅绝缘层上形成氧化物半导体薄膜，在氧化物半导体薄膜的有源层区域上方形成第一光刻胶，使沟道区域上方的第一光刻胶的厚度大于非沟道区域上方的第一光刻胶的厚度；去除非有源层区域的氧化物半导体薄膜，形成有源层的图案，去除非沟道区域上方的第一光刻胶，保留沟道区域上方的第一光刻胶；在所述有源层的图案上方依次形成源漏金属薄膜和第二光刻胶，去除与沟道区域上方的第一光刻胶对应的部分源漏金属薄膜的一部分及与沟道区域上方的第一光刻胶对应 的部分第二光刻胶的一部分，使所述沟道区域上方的第一光刻胶的边缘被所述源漏金属薄膜覆盖；剥离剩余的第二光刻胶、覆盖所述沟道区域上方的第一光刻胶的边缘的源漏金属薄膜、以及所述沟道区域上方的第一光刻胶，形成源极和漏极的图案。
在本发明的一个实施例中，所述在所述栅绝缘层上形成氧化物半导体薄膜，在氧化物半导体薄膜的有源层区域上方形成第一光刻胶，使沟道区域上方的第一光刻胶的厚度大于非沟道区域上方的第一光刻胶的厚度的步骤包括：
在所述氧化物半导体薄膜上形成第一光刻胶，利用半色调掩膜板对非有源层区域上方的第一光刻胶进行全透光曝光显影、对有源层区域的非沟道区域上方的第一光刻胶进行半透光曝光显影以及对沟道区域上方的第一光刻胶进行不透光曝光显影，形成有源层区域的光刻胶。
在本发明的一个实施例中，所述去除非有源层区域的氧化物半导体薄膜，形成有源层的图案，去除非沟道区域上方的第一光刻胶，保留沟道区域上方的第一光刻胶的步骤包括：
根据构图工艺去除非有源层区域的氧化物半导体薄膜，得到有源层图案；
利用灰化工艺去除非沟道区域上方的第一光刻胶，保留沟道区域上方的第一光刻胶。
在本发明的一个实施例中，所述氧化层薄膜晶体管中沟道的长度例如为5～7μm。
在本发明的一个实施例中，所述氧化层薄膜晶体管中沟道的长度例如为5～6μm。
本发明的另一个实施例还提供了一种氧化物薄膜晶体管，其包括：栅极、在所述栅极的一侧形成的栅绝缘层、在所述栅绝缘层远离所述栅极的一侧形成的有源层，以及在所述有源层远离栅绝缘层的一侧形成的源极和漏极，所述源极和所述漏极均直接与所述有源层连接，所述有源层由氧化物半导体材料构成。
在本发明的一个实施例中，所述源极和所述漏极之间的沟道长度例如为5～7μm。
在本发明的一个实施例中，所述源极和所述漏极之间的沟道长度例如为 5～6μm。
本发明的另一个实施例还提供了一种阵列基板，包括上述任一项所述的氧化物薄膜晶体管。
在本发明的一个实施例中，所述阵列基板还包括：树脂层和钝化层；所述树脂层覆盖所述源极、所述漏极以及所述源极和漏极之间的沟道；所述钝化层位于所述树脂层远离所述源极和所述漏极的一侧。
本发明的另一个实施例还提供了一种显示装置，包括上述任一所述的阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1是一种氧化物薄膜晶体管剖视图；
图2是图1所示氧化物薄膜晶体管的半导体层的俯视图；
图3是包含本发明的实施例提供的氧化物薄膜晶体管的阵列基板的剖视图；
图4是本发明的实施例提供的氧化物薄膜晶体管的俯视图；
图5a～5d是本发明的实施例提供的氧化物薄膜晶体管制作方法的工艺流程图；以及
图5e为包含本发明的实施例提供的氧化物薄膜晶体管的阵列基板的剖视图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
发明人注意到，由于氧化物薄膜晶体管的沟道长度相对较长，对于 400PPI～500PPI等超高清产品，以及在像素间距为21μm以下的像素结构中，难以应用氧化物薄膜晶体管。
实施例1
本发明的一个实施例提供了一种氧化物薄膜晶体管的制作方法，其包括：
在基板上依次形成栅极和栅绝缘层；
在所述栅绝缘层上形成氧化物半导体薄膜，在氧化物半导体薄膜的有源层区域上方形成第一光刻胶，使沟道区域上方的第一光刻胶的厚度大于非沟道区域上方的第一光刻胶的厚度；
去除非有源层区域的氧化物半导体薄膜，形成有源层的图案，去除非沟道区域上方的第一光刻胶，保留沟道区域上方的第一光刻胶；
在所述有源层的图案上方依次形成源漏金属薄膜和第二光刻胶，去除与沟道区域上方的第一光刻胶对应的部分源漏金属薄膜的一部分及与沟道区域上方的第一光刻胶对应的部分第二光刻胶的一部分，使所述沟道区域上方的第一光刻胶的边缘被所述源漏金属薄膜覆盖；
剥离剩余的第二光刻胶、覆盖所述沟道区域上方的第一光刻胶的边缘的源漏金属薄膜、以及所述沟道区域上方的第一光刻胶，形成源极和漏极的图案。
本发明的实施例提供的一种氧化物薄膜晶体管的制作方法，利用光刻胶代替保护层对有源层进行保护，使得在有源层的上方形成源极和漏极时，保证源极和漏极与有源层直接相连，而不需要利用过孔与有源层连接。通过光刻胶剥离工艺形成最终的源漏极图案，从而缩短了氧化物薄膜晶体管的沟道的长度。
本发明的实施例所述的“与沟道区域上方的第一光刻胶对应的部分源漏金属薄膜”是指与沟道区域上方的第一光刻胶相对的部分源漏金属薄膜，例如可以为位于沟道区域上方的第一光刻胶正上方的部分源漏金属薄膜。
如图5a～5d所示，本发明的一个实施例提供的一种氧化物薄膜晶体管的制作方法的具体工艺流程包括以下步骤。
利用构图工艺在基板14上依次形成栅极1和栅绝缘层4，并在栅绝缘层4上形成氧化物半导体薄膜10。氧化物半导体薄膜10是由氧元素和In(铟)、Ga(镓)、Zn(锌)、Sn(锡)等元素中的至少两种元素构成的薄膜。例如， 氧化物半导体薄膜可以为IGZO(氧化铟镓锌)薄膜、IZO(氧化铟锌)薄膜、InSnO(氧化铟锡)薄膜或InGaSnO(氧化铟镓锡)薄膜等。参见图5a，本步骤中使用的构图工艺均为已知方案，在此不作赘述。
利用光刻胶工艺在氧化物半导体薄膜10上形成第一光刻胶11a，并利用半色调掩膜板对第一光刻胶11a进行曝光显影。
参见图5a、图5b，以所述第一光刻胶为正性光刻胶为例，半色调掩膜板对应非有源层区域的部分为全透光，半色调掩膜板对应有源层区域内的非沟道区域的部分为半透光，半色调掩膜板对应沟道区域的部分为不透光。通过该半色调掩膜板对第一光刻胶11a进行曝光显影后，得到图5b中的有源层区域上方的第一光刻胶11a。在有源层区域上方的第一光刻胶11a中，沟道区域上方的第一光刻胶11a的厚度大于非沟道区域上方的第一光刻胶11a的厚度。
对氧化物半导体薄膜10进行蚀刻，得到有源层5，以及对有源层区域上方的第一光刻胶11a进行灰化工艺处理，保留沟道区域上方的第一光刻胶11a。
在对氧化物半导体薄膜10进行蚀刻过程中，有源层区域上方的第一光刻胶11a对有源层5起到保护作用。
对氧化物半导体薄膜10的非有源层区域进行蚀刻处理，得到如图5c所示的有源层5。在对该氧化物半导体薄膜10的非有源层区域进行蚀刻处理之后，对有源层区域上方的第一光刻胶11a进行灰化工艺处理，得到如图5c所示的沟道区域上方的第一光刻胶11a，此时沟道区域上方的光刻胶的长度即为氧化薄膜晶体管的沟道12的长度。
对有源层区域上方的光刻胶进行灰化工艺处理后，有源层区域上方的光刻胶的厚度小于灰化工艺之前有源层区域上方的光刻胶的厚度。
在有源层5的上方形成源漏金属薄膜，所述沟道区域上方的第一光刻胶11a被源漏金属薄膜全部覆盖。
在源漏金属薄膜上方形成第二光刻胶11b。
去除与沟道区域上方的第一光刻胶11a对应的部分源漏金属薄膜的一部分及与沟道区域上方的第一光刻胶11a对应的部分第二光刻胶11b的一部分，使所述沟道区域上方的第一光刻胶11a的边缘被所述源漏金属薄膜覆盖。
如图5d所示，所述源极2和所述漏极3之间的有源层区域为氧化物薄膜晶体管的沟道12。在目前的精度允许的情况下，例如，所述源极2和所述漏极3之间的距离为3μm，且位于所述第一光刻胶11a上方的所述源极2的宽度w1为1～1.5μm，位于所述第一光刻胶11a上方的所述漏极3的宽度w2为1～1.5μm。
剥离所述沟道区域上方的第一光刻胶11a、所述第二光刻胶11b，以及所述沟道区域上方的第一光刻胶11a边缘上覆盖的源漏金属薄膜，形成源极和漏极图案，最后形成如图5e中所示的氧化物薄膜晶体管。例如，可以通过离地剥离(lift-off)方式，将沟道区域上方的第一光刻胶11a连同覆盖在第一光刻胶11a之上的部分一起剥离掉。
在形成氧化物薄膜晶体管之后，可通过以下步骤进一步形成包含所述氧化物薄膜晶体管的阵列基板，如图5e所示。
利用构图工艺在源极2和漏极3上方形成树脂层6，以及在树脂层6上方形成公共电极线9。
在形成树脂层6和公共电极线9之后，形成钝化层7和像素电极8。从而形成如图3所示的包含本发明实施例提供的氧化物薄膜晶体管的阵列基板。
利用本发明实施例提供的氧化物薄膜晶体管制作方法，得到如图4所示的氧化物薄膜晶体管，其沟道长度S可精确地达到5～6μm。如果精度变得更小的话，可以得到沟道长度更小的氧化物薄膜晶体管。
在上述剥离过程中剥离掉覆盖在所述沟道区域上方的第一光刻胶11a边缘的源漏金属薄膜时，可能会多剥离一些源漏金属薄膜，使得在得到源极和漏极图案之后，图4中的沟道长度S为5～7μm。而如图2所示，已知的氧化物薄膜晶体管的沟道长度为9.5～10μm之间，甚至是大于10μm。因此，本发明实施例提供的氧化物薄膜晶体管，利用光刻胶代替保护层对有源层进行保护，在氧化物薄膜晶体管制作的最后一步中，将光刻胶剥离，从而使得源极和漏极与有源层直接相连，缩短了氧化物薄膜晶体管的沟道长度。沟道长度的减小可以使薄膜晶体管更小，从而在一些高PPI的产品中提高开口率。
实施例2
本发明的实施例还提供了一种氧化物薄膜晶体管，如图3、图4所示。 所述氧化物薄膜晶体管包括：
在基板14的一侧形成的栅极1、在栅极1远离基板14的一侧形成的栅绝缘层4、在栅绝缘层4远离栅极1的一侧形成的有源层5，以及
在所述有源层5远离栅绝缘层4的一侧形成的源极2和漏极3，所述源极2和所述漏极3均直接与所述有源层5连接，所述有源层5由氧化物半导体材料构成。
例如，所述氧化物半导体材料可以为IGZO、IZO、InSnO或InGaSnO等。
例如，所述源极2和所述漏极3之间的沟道12的长度S为5～6μm。在目前的精度允许的情况下，例如，所述源极2和所述漏极3之间的距离为3μm，且位于所述第一光刻胶11a上方的所述源极2的宽度w1为1～1.5μm，位于所述第一光刻胶11a上方的所述漏极3的宽度w2为1～1.5μm。
在剥离过程中剥离掉覆盖在所述沟道区域上方的第一光刻胶11a边缘的源漏金属薄膜时，可能会多剥离一些源漏金属薄膜，使得在得到源极和漏极图案之后，所述源极2和所述漏极3之间的沟道12的长度S为5～7μm。
本发明实施例提供的一种氧化物薄膜晶体管，利用源/漏工艺在有源层两端形成源极和漏极，保证源极和漏极与有源层直接相连，而不需要利用过孔与有源层连接，从而缩短了氧化物薄膜晶体管的沟道的长度。
实施例3
本发明实施例还提供了一种阵列基板，包括上述实施例任一所述的氧化物薄膜晶体管。
本发明的实施例提供的阵列基板还包括：树脂层6和钝化层7；参照图3所示。
所述树脂层6覆盖所述源极2、所述漏极3以及沟道12；
所述钝化层7位于所述树脂层6远离所述源极2和所述漏极3的一侧。
本发明的实施例提供的阵列基板还包括：位于钝化层7上方以及与漏极3相连的像素电极8，位于钝化层7内部且与树脂层6紧贴的公共电极线9。
实施例4
本发明实施例还提供了一种显示装置，包括上述实施例任一所述的阵列基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可 以参见上述实施例，重复之处不再赘述。
本发明提供的氧化物薄膜晶体管及其制作方法、阵列基板、显示装置，在形成源漏极初步图案时利用光刻胶代替保护层对有源层进行保护，并通过光刻胶剥离工艺形成最终的源漏极图案，从而缩短了氧化物薄膜晶体管的沟道长度。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。
本申请要求于2013年11月5日递交的中国专利申请第201310542201.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种氧化物薄膜晶体管制作方法，包括：
    在基板上依次形成栅极和栅绝缘层；
    在所述栅绝缘层上形成氧化物半导体薄膜，在氧化物半导体薄膜的有源层区域上方形成第一光刻胶，并且使沟道区域上方的第一光刻胶的厚度大于非沟道区域上方的第一光刻胶的厚度；
    去除非有源层区域的氧化物半导体薄膜，形成有源层的图案，去除非沟道区域上方的第一光刻胶，保留沟道区域上方的第一光刻胶；
    在所述有源层的图案上方依次形成源漏金属薄膜和第二光刻胶，去除与所述沟道区域上方的第一光刻胶相对的部分源漏金属薄膜的一部分及与所述沟道区域上方的第一光刻胶相对的部分第二光刻胶的一部分，使所述沟道区域上方的第一光刻胶的边缘被所述源漏金属薄膜覆盖；
    剥离剩余的第二光刻胶、覆盖住所述沟道区域上方的第一光刻胶的边缘的源漏金属薄膜、以及所述沟道区域上方的第一光刻胶，形成源极和漏极的图案。
  2. 根据权利要求1所述的方法，其中，在所述氧化物半导体薄膜上形成所述第一光刻胶，利用半色调掩膜板对所述非有源层区域上方的第一光刻胶进行全透光曝光显影、对所述有源层区域的非沟道区域上方的第一光刻胶进行半透光曝光显影以及对所述沟道区域上方的第一光刻胶进行不透光曝光显影，形成所述有源层区域的光刻胶。
  3. 根据权利要求1所述的方法，其中，根据构图工艺去除所述非有源层区域的氧化物半导体薄膜，得到有源层图案；
    利用灰化工艺去除所述非沟道区域上方的第一光刻胶，保留所述沟道区域上方的第一光刻胶。
  4. 根据权利要求1～3中任一项所述的方法，其中，所述氧化层薄膜晶体管中沟道的长度为5～7μm。
  5. 根据权利要求4所述的方法，其中，所述氧化层薄膜晶体管中沟道的长度为5～6μm。
  6. 一种氧化物薄膜晶体管，包括：栅极、在所述栅极的一侧形成的栅绝 缘层、在所述栅绝缘层远离所述栅极的一侧形成的有源层，
    其中，在所述有源层远离栅绝缘层的一侧形成有源极和漏极，所述源极和所述漏极均直接与所述有源层连接，所述有源层由氧化物半导体材料构成。
  7. 根据权利要求6所述的氧化物薄膜晶体管，其中，所述源极和所述漏极之间的沟道长度为5～7μm。
  8. 根据权利要求7所述的氧化物薄膜晶体管，其中，所述源极和所述漏极之间的沟道长度为5～6μm。
  9. 一种阵列基板，包括上述权利要求6～8中任一项所述的氧化物薄膜晶体管。
  10. 根据权利要求9所述的阵列基板，还包括：树脂层和钝化层；
    其中，所述树脂层覆盖所述源极、所述漏极以及所述源极和漏极之间的沟道；
    所述钝化层位于所述树脂层远离所述源极和所述漏极的一侧。
  11. 一种显示装置，包括上述权利要求9或10所述的阵列基板。
PCT/CN2014/090154 2013-11-05 2014-11-03 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置 WO2015067148A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/652,639 US9520422B2 (en) 2013-11-05 2014-11-03 Oxide thin film transistor and manufacturing method thereof, array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310542201.X 2013-11-05
CN201310542201.XA CN103545378B (zh) 2013-11-05 2013-11-05 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置

Publications (1)

Publication Number Publication Date
WO2015067148A1 true WO2015067148A1 (zh) 2015-05-14

Family

ID=49968644

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/090154 WO2015067148A1 (zh) 2013-11-05 2014-11-03 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置

Country Status (3)

Country Link
US (1) US9520422B2 (zh)
CN (1) CN103545378B (zh)
WO (1) WO2015067148A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545378B (zh) * 2013-11-05 2016-09-07 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置
CN103915379B (zh) * 2014-03-24 2017-07-04 京东方科技集团股份有限公司 一种氧化物薄膜晶体管阵列基板的制造方法
CN104091784A (zh) * 2014-07-11 2014-10-08 合肥鑫晟光电科技有限公司 一种阵列基板制备方法
CN104319278A (zh) * 2014-10-22 2015-01-28 京东方科技集团股份有限公司 阵列基板、显示面板和阵列基板的制作方法
CN105632920B (zh) * 2014-10-27 2019-05-21 鸿富锦精密工业（深圳）有限公司 薄膜晶体管基板的制作方法
CN104409413B (zh) 2014-11-06 2017-12-08 京东方科技集团股份有限公司 阵列基板制备方法
TWI559549B (zh) 2014-12-30 2016-11-21 鴻海精密工業股份有限公司 薄膜電晶體及其製作方法
CN105810743B (zh) * 2014-12-30 2019-01-25 鸿富锦精密工业（深圳）有限公司 薄膜晶体管及其制作方法
CN105161541A (zh) * 2015-08-04 2015-12-16 京东方科技集团股份有限公司 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
CN105047723B (zh) * 2015-09-18 2017-12-19 京东方科技集团股份有限公司 一种薄膜晶体管、其制作方法、阵列基板及显示装置
US10170635B2 (en) 2015-12-09 2019-01-01 Ricoh Company, Ltd. Semiconductor device, display device, display apparatus, and system
CN106206456B (zh) * 2016-08-10 2019-08-27 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
CN107579040B (zh) * 2017-09-07 2020-04-21 京东方科技集团股份有限公司 一种掩膜版、阵列基板及其制作方法
CN109873001A (zh) * 2019-02-26 2019-06-11 深圳市华星光电半导体显示技术有限公司 阵列基板及其制作方法
CN112289744B (zh) * 2020-11-13 2022-09-09 武汉华星光电技术有限公司 阵列基板及其制作方法
CN112864254A (zh) * 2021-04-06 2021-05-28 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板及显示装置
CN116615799A (zh) * 2021-12-14 2023-08-18 京东方科技集团股份有限公司 薄膜晶体管的制备方法、阵列基板及显示面板
CN117525164A (zh) * 2024-01-04 2024-02-06 惠科股份有限公司 阵列基板、阵列基板的制备方法及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007206134A (ja) * 2006-01-31 2007-08-16 Epson Imaging Devices Corp アクティブマトリクス型表示装置の製造方法
CN101621038A (zh) * 2008-07-01 2010-01-06 中华映管股份有限公司 有源元件阵列基板的制造方法
CN102709327A (zh) * 2012-05-16 2012-10-03 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板和显示装置
CN102709326A (zh) * 2012-04-28 2012-10-03 北京京东方光电科技有限公司 薄膜晶体管及其制造方法、阵列基板和显示装置
CN103337462A (zh) * 2013-06-13 2013-10-02 北京大学深圳研究生院 一种薄膜晶体管的制备方法
CN103545378A (zh) * 2013-11-05 2014-01-29 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379684B1 (ko) * 2001-04-20 2003-04-10 엘지.필립스 엘시디 주식회사 박막 트랜지스터 액정표시소자 제조방법
JP4522660B2 (ja) * 2003-03-14 2010-08-11 シャープ株式会社 薄膜トランジスタ基板の製造方法
JP3923462B2 (ja) * 2003-10-02 2007-05-30 株式会社半導体エネルギー研究所 薄膜トランジスタの作製方法
US20050074914A1 (en) * 2003-10-06 2005-04-07 Toppoly Optoelectronics Corp. Semiconductor device and method of fabrication the same
CN101336485B (zh) * 2005-12-02 2012-09-26 出光兴产株式会社 Tft基板及tft基板的制造方法
KR101376073B1 (ko) * 2007-06-14 2014-03-21 삼성디스플레이 주식회사 박막 트랜지스터, 이를 포함하는 어레이 기판 및 이의 제조방법
KR20090075554A (ko) * 2008-01-04 2009-07-08 삼성전자주식회사 액정 표시 장치와 그 제조 방법
US8822995B2 (en) * 2008-07-24 2014-09-02 Samsung Display Co., Ltd. Display substrate and method of manufacturing the same
KR101593443B1 (ko) * 2009-02-19 2016-02-12 엘지디스플레이 주식회사 어레이 기판의 제조방법
KR101578694B1 (ko) * 2009-06-02 2015-12-21 엘지디스플레이 주식회사 산화물 박막 트랜지스터의 제조방법
KR20110093113A (ko) * 2010-02-11 2011-08-18 삼성전자주식회사 박막 트랜지스터 기판 및 이의 제조 방법
CN102148195B (zh) * 2010-04-26 2013-05-01 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
KR101820372B1 (ko) * 2010-11-09 2018-01-22 삼성디스플레이 주식회사 표시 기판, 표시 장치 및 이의 제조 방법
CN102479752B (zh) * 2010-11-30 2014-08-13 京东方科技集团股份有限公司 薄膜晶体管、有源矩阵背板及其制造方法和显示器
KR101960796B1 (ko) * 2012-03-08 2019-07-16 삼성디스플레이 주식회사 박막 트랜지스터의 제조 방법, 표시 기판의 제조 방법 및 표시 기판
KR101951260B1 (ko) * 2012-03-15 2019-02-25 삼성디스플레이 주식회사 박막트랜지스터, 상기 박막트랜지스터를 포함하는 표시 장치 및 상기 박막트랜지스터를 포함하는 유기 발광 표시 장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007206134A (ja) * 2006-01-31 2007-08-16 Epson Imaging Devices Corp アクティブマトリクス型表示装置の製造方法
CN101621038A (zh) * 2008-07-01 2010-01-06 中华映管股份有限公司 有源元件阵列基板的制造方法
CN102709326A (zh) * 2012-04-28 2012-10-03 北京京东方光电科技有限公司 薄膜晶体管及其制造方法、阵列基板和显示装置
CN102709327A (zh) * 2012-05-16 2012-10-03 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板和显示装置
CN103337462A (zh) * 2013-06-13 2013-10-02 北京大学深圳研究生院 一种薄膜晶体管的制备方法
CN103545378A (zh) * 2013-11-05 2014-01-29 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置

Also Published As

Publication number Publication date
US20150340504A1 (en) 2015-11-26
CN103545378A (zh) 2014-01-29
US9520422B2 (en) 2016-12-13
CN103545378B (zh) 2016-09-07

Similar Documents

Publication Publication Date Title
WO2015067148A1 (zh) 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置
WO2016119324A1 (zh) 阵列基板及其制作方法、显示装置
WO2014127579A1 (zh) 薄膜晶体管阵列基板、制造方法及显示装置
WO2019109712A1 (zh) 阵列基板及制作方法、显示面板、显示装置
US10910498B2 (en) Array substrate, method for fabricating the same and display device
WO2015149482A1 (zh) 阵列基板及其制作方法、显示装置
US10663820B2 (en) Display substrate, its manufacturing method, and display device
US9276014B2 (en) Array substrate and method of fabricating the same, and liquid crystal display device
US10504926B2 (en) Thin film transistor, method for fabricating the same, array substrate, and display panel
WO2017020480A1 (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
EP2757589A2 (en) Methods for fabricating a thin film transistor and an array substrate
WO2017008347A1 (zh) 阵列基板、阵列基板的制造方法及显示装置
US20150311345A1 (en) Thin film transistor and method of fabricating the same, display substrate and display device
WO2015055030A1 (zh) 阵列基板及其制作方法、显示装置
WO2015180357A1 (zh) 阵列基板及其制作方法和显示装置
WO2017028493A1 (zh) 薄膜晶体管及其制作方法、显示器件
CN108550595B (zh) X-ray探测器阵列基板及其制作方法、X-ray探测器
US20130329157A1 (en) Liquid crystal display and manufacturing method thereof
US10714512B2 (en) Thin film transistor, method for fabricating the same, and display device
US20170243901A1 (en) Thin film transistor array substrate, method for manufacturing the same, and display device
CN107735853B (zh) 薄膜晶体管制造方法及阵列基板
CN112951853A (zh) 薄膜晶体管阵列基板及其制作方法
US9923099B2 (en) TFT with oxide layer on IGZO semiconductor active layer
CN102832170A (zh) 阵列基板的制造方法及阵列基板、显示装置
WO2018040795A1 (zh) 一种阵列基板及其制备方法、显示面板及其制备方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14652639

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14860399

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 16.09.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 14860399

Country of ref document: EP

Kind code of ref document: A1