WO2016000342A1 - 阵列基板及其制作方法、显示装置 - Google Patents
阵列基板及其制作方法、显示装置 Download PDFInfo
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- WO2016000342A1 WO2016000342A1 PCT/CN2014/088082 CN2014088082W WO2016000342A1 WO 2016000342 A1 WO2016000342 A1 WO 2016000342A1 CN 2014088082 W CN2014088082 W CN 2014088082W WO 2016000342 A1 WO2016000342 A1 WO 2016000342A1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H10K2102/00—Constructional details relating to the organic devices covered by this subclass
- H10K2102/301—Details of OLEDs
- H10K2102/302—Details of OLEDs of OLED structures
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- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Definitions
- Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
- OLED organic light emitting diode
- PMOLED Passive Matrix Driving OLED
- AMOLED Active Matrix Driving OLED
- an AMOLED In the framework of an AMOLED, it can be driven using amorphous silicon, polysilicon, an oxide semiconductor or an organic thin film transistor.
- a patterning process multiple times, for example, an 8- to 9-mask exposure process. In this way, not only the process is complicated, the cost is high, but the cumbersome process steps also lead to the continuous superposition of production errors, making the quality of the AMOLED display device difficult to ensure.
- a method for fabricating an array substrate including:
- an array substrate including:
- a gate electrode a gate electrode, a gate insulating layer, and a polysilicon active layer formed on the base substrate;
- a passivation layer formed on a surface of the polysilicon active layer, and first via holes and second via holes on a surface of the passivation layer;
- a pixel electrode electrically connected to the drain.
- a display device comprising any of the array substrates as described above.
- 1 is a schematic structural view of a known array substrate
- FIG. 2 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention
- 3a-3e are schematic structural diagrams of steps in another process of fabricating an array substrate according to an embodiment of the present invention.
- FIG. 4 is a flow chart of another method for fabricating an array substrate according to an embodiment of the present invention.
- FIG. 5 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present invention.
- FIG. 6 is a flowchart of still another method for fabricating an array substrate according to an embodiment of the present invention.
- FIG. 7 is a schematic structural diagram of each step in the process of fabricating an array substrate according to an embodiment of the present invention.
- FIG. 8 is a flowchart of still another method for fabricating an array substrate according to an embodiment of the present invention.
- FIG. 9 is a schematic structural diagram of each step in the process of preparing an array substrate according to an embodiment of the present invention.
- FIG. 10 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
- FIG. 11 is a flowchart of still another method for fabricating an array substrate according to an embodiment of the present invention.
- FIG. 12 is a schematic structural diagram of each step in the process of fabricating an array substrate according to an embodiment of the present invention.
- FIG. 13 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
- a polysilicon active layer 102 made of polysilicon is located on a surface of the buffer layer 200; the surface of the polysilicon active layer 102 has a gate insulating layer 101 and a gate in this order.
- an interlayer insulating layer 201; a source 106 and a drain 107 are electrically connected to the polysilicon active layer 102 through via holes on the surface of the interlayer insulating layer 201, and the pixel electrode 108 passes through a via located on the surface of the passivation layer 103.
- the drain 107 is electrically connected; the pixel electrode 108 and the surface of the passivation layer 103 are provided with a pixel defining layer 109.
- An embodiment of the present invention provides a method for fabricating an array substrate, as shown in FIG. 2, including:
- a pattern including the gate electrode 100, the gate insulating layer 101, and the polysilicon active layer 102 may be formed by one patterning process.
- a passivation layer 103 may be formed on the surface of the substrate on which the above pattern is formed, and a pattern of the first via hole 104 and the second via hole 105 may be formed on the surface of the passivation layer 103 by one patterning process. .
- a pattern of the source 106, the drain 107, and the pixel electrode 108 may be formed by a patterning process on the surface of the substrate on which the pattern is formed; wherein the source 106 passes through the first via 104 and the polysilicon
- the active layer 102 is electrically connected, and the drain 106 is electrically connected to the polysilicon active layer 102 through the second via 105.
- the pattern of the pixel defining layer 109 can be formed by one patterning process.
- the patterning process refers to a photolithography process, or includes a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.;
- the process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, etc., including a film forming, exposure, and developing process.
- the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
- Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device.
- a gate electrode, a gate insulating layer, and a polysilicon active layer may be formed on the substrate by one patterning process; and the first via located on the surface of the passivation layer is formed by one patterning process.
- a pixel defining layer is formed by one patterning process. In this way, only four patterning processes are used in the process of the AMOLED array substrate, which effectively reduces the number of patterning processes, simplifies the process steps, reduces production errors, and improves production efficiency and quality.
- step S101 includes:
- the buffer layer 200 is covered on the base substrate 10.
- the buffer layer 200 is located between the gate electrode 100 and the base substrate 01, and includes a second material layer 221 near the surface of the gate 100 side and a surface near the surface of the substrate substrate 01. A material layer 220.
- the first material layer 220 is made of silicon nitride (SiN) and has a thickness of 50 to 100 nm; and the second material layer 221 is made of silicon dioxide (SiO2) and has a thickness of 100 to 400 nm.
- the first material layer 220 composed of silicon nitride (SiN) has a strong diffusion barrier property, can suppress the influence of metal ions on the polysilicon active layer 102, and has a function of waterproof dust.
- the second material layer 221 composed of silicon oxide (SiO2) has an excellent interface with the polysilicon active layer 102, and can prevent the self-defect of the first material layer 220 composed of silicon nitride (SiN) from the polysilicon active layer 102. The quality caused damage.
- a gate metal thin film layer 300, a gate insulating film layer 301, and a polysilicon thin film layer 302 are sequentially formed on the surface of the buffer layer 200.
- a gate metal thin film layer 300 having a thickness of 200 to 500 nm may be deposited on the surface of the buffer layer 200 by magnetron sputtering.
- the gate metal thin film layer 300 may be made of at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), and aluminum-niobium alloy (AlNd), or may be made of molybdenum/aluminum.
- Multilayer metal composite film such as molybdenum (Mo/Al/Mo) or titanium/aluminum/titanium (Ti/Al/Ti).
- a gate insulating film layer 301 is deposited on the surface of the gate metal thin film layer 300 by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
- the gate insulating layer 101 formed of the gate insulating film layer 301 may be located between the gate electrode 100 and the polysilicon active layer 102, including the first material layer 220 near the surface of the gate 100 side. And a second material layer 221 near a surface of one side of the polysilicon active layer 102.
- the first material layer 220 is made of silicon nitride (SiN) and has a thickness of 20 to 100 nm; and the second material layer 221 is made of silicon dioxide (SiO2) and has a thickness of 30 to 400 nm.
- the first material layer 220 composed of silicon nitride (SiN) has a strong diffusion barrier property, and the influence of the metal ions on the polysilicon active layer 102 can be suppressed.
- the second material layer 221 composed of silicon oxide (SiO2) has an excellent interface with the polysilicon active layer 102, and can prevent the self-defect of the first material layer 220 composed of silicon nitride (SiN) from the polysilicon active layer 102. The quality caused damage.
- the step of forming the polysilicon film layer 302 on the surface of the gate insulating film layer 301, as shown in FIG. 5, may include:
- an amorphous silicon (a-Si) thin film is formed on the surface of the gate insulating film layer 301.
- a-Si amorphous silicon
- PECVD method chemical vapor deposition method
- an amorphous silicon (a-Si) film may be formed on the surface of the second material layer 221 composed of silicon oxide (SiO2).
- Amorphous silicon (a-Si) film subjected to the above dehydrogenation process is subjected to a crystallization process to form a polysilicon film layer 302.
- a method such as laser annealing crystallization, metal induced crystallization, solid phase crystallization, or the like can be used.
- amorphous silicon (a-Si) film is subjected to a dehydrogenation process before the crystallization process, it is possible to prevent the hydrogen ion from overflowing due to laser irradiation or the like during the crystallization process, resulting in hydrogen explosion.
- the surface of the polysilicon film layer 302 is not flat, which seriously affects the quality of the product.
- a photoresist 400 is coated on the surface of the polysilicon film layer 302, and is exposed by a two-tone reticle to form a first photoresist completely remaining region A (photoresist 401).
- the thickness is 1 to 3 ⁇ m
- the first photoresist portion is reserved (not shown in the drawing, the photoresist of the region is 0.5 to 1 ⁇ m thick)
- the first photoresist is completely removed from the region B.
- the first photoresist completely remaining region A corresponds to a pattern of the gate electrode 100, the gate insulating layer 101, and the polysilicon active layer 102 to be formed.
- the first photoresist partially reserved region corresponds to a pattern of gate lines (not shown) connected to the gate 100; the first photoresist completely removed region B corresponds to the remaining region of the surface of the polysilicon film layer 302, the first The photoresist completely removed region B is not covered by the photoresist 400.
- the gate 100 and the gate finally formed by the patterning process are illustrated.
- the patterns of the insulating layer 101 and the polysilicon active layer 102 are identical. Therefore, a region other than the gate electrode 100 (or the gate insulating layer 101 or the polysilicon active layer 102) and the gate line on the surface of the polysilicon film layer 302 may be the first photoresist completely removed region B.
- the polysilicon film layer 302 may be cleaned by the diluted hydrofluoric acid to reduce the surface roughness of the polysilicon film layer 302.
- the two-tone reticle is a semi-transparent reticle, and two different thicknesses of photoresist 400 can be formed on the surface of the polysilicon film layer 302 (the first photoresist completely retains the area A).
- the two-tone reticle may include a gray-tone mask and a half-tone mask.
- a mixed gas such as carbon tetrafluoride/oxygen (CF4/O2), trifluoromethane/oxygen (CHF3/O2) or sulfur hexafluoride/oxygen (SF6/O2) may be used, by plasma or inductively coupled plasma method.
- CF4/O2 carbon tetrafluoride/oxygen
- CHF3/O2 trifluoromethane/oxygen
- SF6/O2 sulfur hexafluoride/oxygen
- etching or etching is performed by plasma or inductively coupled plasma method.
- a gas such as carbon tetrafluoride (CF4), carbon tetrafluoride/oxygen (CF4/O2), or trifluoromethane/oxygen (CHF3/O2)
- etching or etching is performed by plasma or inductively coupled plasma method.
- wet etching or dry etching such as inductively coupled plasma using a mixed gas of carbon tetrachloride/boron trichloride (CCl2/BCl3) and carbon tetrafluoride/oxygen (CF4/O2), may be employed.
- the gate etch process etches the gate metal film layer 300 to form a gate 100 and a gate line electrically connected to the gate 100.
- the gate metal film layer 300 can be etched by a dry etching process when manufacturing a high resolution display panel; for a low resolution display panel
- the gate metal thin film layer 300 may be etched by a wet etching process.
- a thinner photoresist is removed using a plasma ashing process
- a thicker photoresist 401 is retained as an etch barrier
- a thinner photoresist is removed during ashing
- a thicker photoresist is used.
- the thickness of 401 is reduced.
- the polysilicon film layer 302 is then etched by a plasma or inductively coupled plasma method to remove the polysilicon film layer 302 overlying the array gate lines.
- step S206 as shown in FIG. 3e, the photoresist 401 of the first photoresist completely remaining region A is peeled off, and finally the pattern of the gate electrode 100, the gate insulating layer 101, and the gate line is formed.
- the surface of the polysilicon film layer 302 which is preliminarily prepared as the polysilicon active layer 102 can be exposed.
- the region other than the above polysilicon island may be performed through the mask. Protection to avoid adverse effects on the above areas during ion doping.
- step S102 may include:
- a passivation layer 103 is formed on the surface of the polysilicon active layer 102; for example, the passivation layer 103 is composed of a silicon nitride (SiN) film containing a hydrogen element. Its thickness is 200 to 500 nm.
- annealing the passivation layer 103 by using an annealing process includes rapid thermal annealing or annealing using a heat treatment furnace.
- both the passivation layer 103 and the gate insulating layer 101 contain silicon nitride (SiN), and the passivation layer 103 contains a hydrogen element. Therefore, hydrogenation treatment of the inside of the polysilicon active layer 102 and the interface of the polysilicon active layer 102 can be realized by silicon nitride (SiN). The dangling bonds in the polysilicon active layer 102 can be removed by the above hydrogenation treatment, thereby improving the mobility and reducing the drift of the threshold voltage.
- a pattern of the first via hole 104 and the second via hole 105 is formed by one patterning process (for example, one mask exposure process).
- step S103 includes:
- a source/drain metal thin film layer 303 and a transparent conductive thin film layer 304 are sequentially formed on the surface of the passivation layer 103.
- a source/drain metal thin film layer 303 having a thickness of 200 to 500 nm may be deposited on the surface of the passivation layer 103 by magnetron sputtering.
- the source/drain metal thin film layer 303 may be made of at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), and aluminum-niobium alloy (AlNd), or may be used.
- a multilayer metal film such as molybdenum/aluminum/molybdenum (Mo/Al/Mo) or titanium/aluminum/titanium (Ti/Al/Ti).
- the metallic materials such as copper (Cu), molybdenum (Mo) or molybdenum/aluminum/molybdenum (Mo/Al/Mo) are relatively common in production processes due to their mature manufacturing process.
- a transparent conductive film layer 304 is deposited on the surface of the source/drain metal film layer 303 by magnetron sputtering, and indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO), indium zinc oxide/silver may be used.
- Composite film (IZO/Ag) For example, the ITO has a thickness of 10 to 50 nm, and the Ag metal film has a thickness of 20 to 100 nm.
- a photoresist 400 is formed on the surface of the transparent conductive film layer 304, and a second photoresist corresponding to the pattern of the source 106 and the drain 107 to be formed is completely retained by a single exposure and development process.
- the region G, and the second photoresist corresponding to the remaining region of the surface of the transparent conductive film layer 304 completely removes the region F.
- the second photoresist completely removed region F includes a source to be formed on the surface of the transparent conductive film layer 304.
- the pixel defining layer 109 is formed on the surface of the substrate on which the above structure is formed by the step S104, and the array substrate as shown in FIG. 10 is produced.
- the array substrate can be used to form a low temperature polysilicon display panel of a top emission type AMOLED.
- the light of the display panel can be emitted upward (in a direction away from the surface of the base substrate 01). Since the source 106 and the drain 107 formed of the source/drain metal thin film layer 303 can reflect the emitted light, the aperture ratio of the display panel can be increased. Therefore, the top emission type AMOLED display panel can be applied to a high resolution display device.
- step S103 may include:
- a transparent conductive film layer 304 and a source/drain metal film layer 303 are sequentially formed on the surface of the passivation layer 103.
- a transparent conductive film layer 304 is deposited on the surface of the passivation layer 103 by magnetron sputtering, and indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO), indium zinc oxide/silver (IZO/) may be used.
- Composite film such as Ag). The thickness is 20 to 100 nm.
- a source/drain metal film layer 303 is deposited on the surface of the transparent conductive film layer 304 by magnetron sputtering to a thickness of 200 to 500 nm.
- a photoresist 400 is formed on the surface of the source/drain metal film layer 303, and can be exposed once by the above-mentioned two-color reticle to form a third photoresist completely reserved region after development.
- the domain C (the thickness of the photoresist 401 is 1 to 3 ⁇ m)
- the second photoresist portion retaining region D (the thickness of the photoresist 402 is 0.5 to 1.5 ⁇ m)
- the third photoresist completely removed region E is the third photoresist completely removed region E.
- the third photoresist completely remaining region C corresponds to the source 106 and the drain 107 to be formed and the pattern of the data line (not shown) connected to the source 106; the second photoresist portion retains the region D Corresponding to the pattern of the pixel electrode 108; the third photoresist completely removed region E corresponds to the remaining region of the surface of the source/drain metal film layer 303.
- the third photoresist completely removed region E includes a source to be formed on the surface of the transparent conductive film layer 304.
- the photoresist 402 of the second photoresist portion remaining region D is removed by an ashing process, and the source/drain metal film layer 303 of the second photoresist portion remaining region D is etched.
- the thickness of the photoresist 401 of the third photoresist completely remaining region C is thinned.
- the photoresist 401 of the third photoresist completely remaining region C is peeled off, and finally the source conductive layer 1061, the source 106 located on the surface of the source conductive layer 1061, the pixel electrode 108, and A pattern of drain electrodes 107 to which pixel electrodes 108 are connected.
- the pixel defining layer 109 is formed on the surface of the substrate on which the above structure is formed by the step S104, and the array substrate as shown in FIG. 13 is produced.
- the array substrate can be used to form a low temperature polysilicon display panel of a bottom emission AMOLED.
- the light of the display panel can be emitted downward (in the direction close to the surface of the base substrate 01). In this way, since the thin film transistor blocks a part of the light, the aperture ratio of the display panel is small. Therefore, the top emission type AMOLED display panel can be applied to a low resolution display device.
- An embodiment of the present invention provides an array substrate, as shown in FIG. 10 or 13, including:
- a source 106 electrically connected to the polysilicon active layer 102 through the first via 104;
- a pixel electrode 108 electrically connected to the drain 107.
- Embodiments of the present invention provide an array substrate.
- the array substrate includes a base substrate, a gate formed on the base substrate, a gate insulating layer, a polysilicon active layer, a passivation layer formed on a surface of the polysilicon active layer, and a first via located on a surface of the passivation layer And a second via, a source electrically connected to the polysilicon active layer through the first via, a drain electrically connected to the polysilicon active layer through the second via, and a pixel electrode electrically connected to the drain.
- only four patterning processes can be used in the process of fabricating the above-mentioned AMOLED array substrate, which effectively reduces the number of patterning processes, simplifies the process steps, reduces production errors, and improves production efficiency and quality.
- the gate 100, the gate insulating layer 101, and the polysilicon active layer 102 may be sequentially located on the surface of the base substrate 01; and the patterns of the gate 100, the gate insulating layer 101, and the polysilicon active layer 102 are uniform. . In this way, the gate electrode 100, the gate insulating layer 101, and the polysilicon active layer 102 on the surface of the base substrate 01 can be fabricated by one patterning process, thereby simplifying the fabrication process, improving productivity, and product quality.
- the embodiment of the present invention provides a display device, including any of the array substrates described above, having the same advantageous effects as the array substrate provided by the foregoing embodiments of the present invention, since the detailed structure of the array substrate has been made in the foregoing embodiment. A detailed description will not be repeated here.
- the display device may be any product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
- a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
- Embodiments of the present invention provide a display device including an array substrate.
- the array substrate includes a base substrate, a gate formed on the base substrate, a gate insulating layer, a polysilicon active layer, a passivation layer formed on a surface of the polysilicon active layer, and a first pass on the surface of the passivation layer Hole and second via.
- the source is electrically connected to the polysilicon active layer through the first via
- the drain is electrically connected to the polysilicon active layer through the second via.
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Abstract
Description
Claims (13)
- 一种阵列基板的制作方法,包括:在衬底基板上通过一次构图工艺形成包括栅极、栅极绝缘层、多晶硅有源层的图案;在形成有上述图案的基板表面,形成钝化层,并在所述钝化层的表面通过一次构图工艺形成第一过孔和第二过孔的图案;在形成有上述图案的基板表面,通过一次构图工艺形成源极、漏极以及像素电极的图案;其中,所述源极通过所述第一过孔与所述多晶硅有源层电连接,所述漏极通过所述第二过孔与所述多晶硅有源层电连接;在形成有上述图案的基板表面通过一次构图工艺形成像素界定层的图案。
- 根据权利要求1所述的阵列基板的制作方法,其中所述在衬底基板上形成栅极、栅极绝缘层、多晶硅有源层的图案的步骤包括:在所述衬底基板上覆盖缓冲层;在所述缓冲层的表面依次形成栅极金属薄膜层、栅极绝缘薄膜层以及多晶硅薄膜层;在所述多晶硅薄膜层的表面涂覆一层光刻胶,通过一次曝光显影工艺后形成第一光刻胶完全保留区域、第一光刻胶部分保留区域和第一光刻胶完全去除区域,所述第一光刻胶完全保留区域对应待形成的所述栅极、所述栅极绝缘层以及所述多晶硅有源层的图案,所述第一光刻胶部分保留区域对应与所述栅极相连的栅线的图案,所述第一光刻胶完全去除区域对应所述多晶硅薄膜层表面的其余区域;刻蚀对应所述第一光刻胶完全去除区域的所述多晶硅薄膜层、所述栅极绝缘薄膜层以及所述栅极金属薄膜层;去除所述第一光刻胶部分保留区域的光刻胶,并对所述第一光刻胶部分保留区域对应的所述多晶硅薄膜层进行刻蚀;对所述第一光刻胶完全保留区域的光刻胶进行剥离,最终形成所述栅极、所述栅极绝缘层以及所述栅线的图案;对对应所述第一光刻胶完全保留区域的所述多晶硅薄膜层进行离子掺杂 工艺,以形成所述多晶硅有源层的图案。
- 根据权利要求2所述的阵列基板的制作方法,其中所述栅极绝缘层位于所述栅极与所述多晶硅有源层之间,包括靠近所述栅极一侧表面的第二材料层和靠近所述多晶硅有源层一侧表面的第一材料层;所述缓冲层位于所述栅极与所述衬底基板之间,包括靠近所述栅极一侧表面的所述第一材料层和靠近所述衬底基板一侧表面的所述第二材料层。
- 根据权利要求3所述的阵列基板的制作方法,其中所述第一材料层由氮化硅构成;所述第二材料层由二氧化硅构成。
- 根据权利要求2所述的阵列基板的制作方法,其中在所述栅极绝缘薄膜层的表面形成所述多晶硅薄膜层的步骤包括:在所述栅极绝缘薄膜层的表面形成非晶硅薄膜;对所述非晶硅薄膜进行脱氢工艺;对经过所述脱氢工艺的所述非晶硅薄膜采用结晶工艺,以形成所述多晶硅薄膜层。
- 根据权利要求2所述的阵列基板的制作方法,其中所述在形成有上述图案的基板表面,形成钝化层,并在所述钝化层的表面形成第一过孔和第二过孔的步骤包括:在所述多晶硅有源层的表面形成所述钝化层;其中,所述钝化层由含氢元素的氮化硅薄膜构成;采用退火工艺对所述钝化层进行退火处理;在经过所述退火处理的所述钝化层表面,通过一次构图工艺形成所述第一过孔和所述第二过孔的图案。
- 根据权利要求6所述的阵列基板的制作方法,其中所述在形成有上述图案的基板表面形成源极、漏极以及像素电极的图案的步骤包括:在所述钝化层的表面,依次形成源漏金属薄膜层、透明导电薄膜层;在所述透明导电薄膜层的表面形成所述光刻胶,通过一次曝光显影工艺,在所述透明导电薄膜层的表面形成对应待形成的所述源极和所述漏极图案的第二光刻胶完全保留区域,以及对应所述透明导电薄膜层表面其余区域的第二光刻胶完全去除区域;对对应所述第二光刻胶完全去除区域的所述透明导电薄膜层、所述源漏金属薄膜层进行刻蚀;将所述第二光刻胶完全保留区域的光刻胶剥离,最终形成所述源极、所述漏极以及位于所述源极表面的源极导电层、位于所述漏极表面的所述像素电极。
- 根据权利要求6所述的阵列基板的制作方法,其中所述在形成有上述图案的基板表面形成源极、漏极以及像素电极的图案的步骤包括:在所述钝化层的表面,依次形成所述透明导电薄膜层、所述源漏金属薄膜层;在所述源漏金属薄膜层的表面形成所述光刻胶,通过一次曝光,显影工艺形成第三光刻胶完全保留区域、第二光刻胶部分保留区域以及第三光刻胶完全去除区域,所述第三光刻胶完全保留区域对应待形成的所述源极和所述漏极的图案;所述第二光刻胶部分保留区域对应所述像素电极的图案;所述第三光刻胶完全去除区域对应所述源漏金属薄膜层表面的其余区域;刻蚀对应所述第三光刻胶完全去除区域的所述透明导电薄膜层、所述源漏金属薄膜层;去除所述第二光刻胶部分保留区域的光刻胶,并对所述第二光刻胶部分保留区域的所述源漏金属薄膜层进行刻蚀;将所述第三光刻胶完全保留区域的所述光刻胶剥离,最终形成所述源极导电层、位于所述源极导电层表面的源极、像素电极以及与所述像素电极相连接的所述漏极的图案。
- 根据权利要求1-8任一项所述的阵列基板的制作方法,其中所述栅极金属薄膜层和所述源漏金属薄膜层均由铝、钼、铜、钛中的一种或多种构成。
- 根据权利要求2所述的阵列基板的制作方法,其中所述在所述多晶硅薄膜层的表面涂覆一层光刻胶的步骤之前,所述方法还包括:采用稀释处理的氢氟酸对多晶硅薄膜层的表面进行清洗。
- 一种阵列基板,包括:衬底基板;形成于所述衬底基板上的栅极、栅极绝缘层、多晶硅有源层;形成于所述多晶硅有源层表面的钝化层,以及位于所述钝化层表面的第 一过孔和第二过孔;通过所述第一过孔与所述多晶硅有源层电连接的源极;通过所述第二过孔与所述多晶硅有源层电连接的漏极;和与所述漏极电连接的像素电极。
- 根据权利要求11所述的阵列基板,其中所述栅极、所述栅极绝缘层、所述多晶硅有源层依次位于所述衬底基板的表面;并且,所述栅极、所述栅极绝缘层以及所述多晶硅有源层的图案一致。
- 一种显示装置,包括权利要求11或12所述的阵列基板。
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CN104078423A (zh) * | 2014-06-24 | 2014-10-01 | 京东方科技集团股份有限公司 | 一种阵列基板的制造方法、阵列基板及显示装置 |
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