WO2016045270A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2016045270A1
WO2016045270A1 PCT/CN2015/070885 CN2015070885W WO2016045270A1 WO 2016045270 A1 WO2016045270 A1 WO 2016045270A1 CN 2015070885 W CN2015070885 W CN 2015070885W WO 2016045270 A1 WO2016045270 A1 WO 2016045270A1
Authority
WO
WIPO (PCT)
Prior art keywords
active layer
layer
electrode
pattern
forming
Prior art date
Application number
PCT/CN2015/070885
Other languages
English (en)
French (fr)
Inventor
谢振宇
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/771,320 priority Critical patent/US9627461B2/en
Publication of WO2016045270A1 publication Critical patent/WO2016045270A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • An Active Matrix Organic Light Emitting Diode (AMOLED) display device is a novel flat panel display device. Compared with a liquid crystal display, an Organic Light Emitting Diode (OLED) has self-luminous light. The function does not require a backlight. Therefore, the viewing angle and contrast of the AMOLED display device are superior to those of the liquid crystal display, and have the advantages of small size, light weight, and low power consumption. At the same time, since the AMOLED display device uses a low-power-transmission thin film transistor (Thin-Film Transistor, TFT for short) to transmit pixel voltage to the OLED for display, it also has the advantage of fast response. AMOLED display devices can also operate over a wider temperature range with lower production costs.
  • TFT Thin-Film Transistor
  • the TFT can be classified into a polysilicon (p-Si) TFT and an amorphous silicon (a-Si) TFT, and the difference between the two is that the transistor characteristics are different. Due to its own defects in amorphous silicon a-Si, such as low on-state current, low mobility, and poor stability due to many defect states, it is limited in many fields. However, the molecular structure of P-Si is neat and directional in a grain, so the electron mobility is 200-300 times faster than the disordered amorphous silicon. usage of.
  • the manufacturing process of the AMOLED includes:
  • a source electrode and a drain electrode are formed on the insulating structure, and the source electrode and the drain electrode are in electrical contact with the active layer through the via hole.
  • the insulating structure includes at least two insulating layers
  • the usual technical method is to use a certain percentage of over-etching, generally about 40%, meaning that during the etching process,
  • the active layer at the via hole needs to withstand long-term ion bombardment. The ion bombardment will cause the surface of the active layer at the via hole to be rough, and the number of defects will increase sharply.
  • the characteristics of the gold half-contact will be It is affected, which affects the conduction characteristics of the entire TFT.
  • the embodiment of the present application provides an array substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the via etching process in the insulating structure causes the underlying active layer to be rough, thereby affecting the conduction characteristics of the entire TFT. problem.
  • the embodiment of the first aspect of the present application provides a method of fabricating an array substrate.
  • the method includes the steps of forming a thin film transistor, and the step of forming a thin film transistor includes:
  • an embodiment of the second aspect of the present application also provides an array substrate.
  • the array substrate includes a thin film transistor, wherein the thin film transistor further includes:
  • An ion implantation region located in the active layer pattern and corresponding to a position of the first via hole
  • a source electrode and a drain electrode disposed on the insulating structure the source electrode and the drain electrode are in contact with a surface of the ion implantation region through the first via hole, and further electrically connected to the active layer pattern contact.
  • An embodiment of the third aspect of the present application also provides a display device.
  • the display device includes the array substrate as described above.
  • the source electrode and the drain electrode are located above the active layer pattern, and the source electrode and the drain electrode pass through the through-the insulating structure
  • the first via is in electrical contact with the active layer pattern, wherein the exposed active layer pattern is paired through the first via extending through the insulating structure before the source electrode and the drain electrode are fabricated Performing ion implantation to form the ion implantation region, so that the etching process for forming via holes can be repaired to cause damage to the surface of the active layer pattern, thereby improving the source electrode/the drain electrode and the active layer pattern.
  • the semi-electrical contact performance of the gold further improves the electrical characteristics of the thin film transistor and ensures the display quality of the display device.
  • FIGS. 1-8 show schematic diagrams of a process of fabricating an AMOLED according to an embodiment of the present application
  • FIG. 9 is a schematic structural view of a bottom gate type thin film transistor
  • Fig. 10 is a schematic structural view of a top gate type thin film transistor.
  • electrical connection between different conductive layers is generally achieved by making via holes in the insulating layer, that is, electrical contact between the different conductive layers through the via holes in the insulating layer.
  • the gold/semiconductor contact of the source/drain electrodes of the thin film transistor with the active layer pattern is realized by a via hole in the insulating layer (specifically, the source/drain metal is in electrical contact with the semiconductor active layer)
  • the insulating layer In the etching process for forming via holes, in order to ensure complete etching of the via holes in the insulating layer, the active layer pattern corresponding to the via position is also etched, which results in a position corresponding to the via hole.
  • the active layer pattern has a rough surface and thereby affects the gold semi-electrical contact between the subsequently formed source electrode, drain electrode and active layer pattern, thereby affecting the electrical characteristics of the entire thin film transistor.
  • an embodiment of the present application provides an array substrate and a method of fabricating the same.
  • the fabricating method includes: forming a first via hole in an insulating structure over the active layer pattern to expose an active layer pattern corresponding to the first via hole position; The first via hole performs ion implantation on the exposed active layer pattern to form an ion implantation region, so that a subsequently formed source/drain electrode passes through the first via and the ion of the active layer pattern The implantation region is electrically contacted, thereby improving the gold semi-electrical contact performance of the source electrode/the drain electrode and the active layer pattern, thereby improving the electrical characteristics of the thin film transistor.
  • Embodiments of the first aspect of the present application provide a method of fabricating an array substrate.
  • the method includes the step of forming a thin film transistor, wherein the step of forming a thin film transistor includes:
  • Step S1 forming an active layer pattern on the substrate
  • Step S2 forming an insulating structure on the active layer pattern
  • Step S3 forming a first via hole penetrating the insulating structure to expose an active layer pattern corresponding to the first via hole position, wherein the first via hole extends to the exposed active layer pattern internal;
  • Step S4 performing ion implantation on the exposed active layer pattern via the first via to form an ion implantation region, wherein the ion implantation region is located in the active layer pattern;
  • Step S5 forming a source electrode and a drain electrode on the insulating structure, wherein the source electrode and the drain electrode are in contact with a surface of the ion implantation region through the first via hole, thereby contacting the active layer
  • the pattern is electrically contacted.
  • the exposed active layer pattern is ion-implanted through the first via hole in the insulating structure to form the ion implantation region.
  • an embodiment of the second aspect of the present application also provides an array substrate.
  • the array substrate includes a thin film transistor, wherein the thin film transistor includes:
  • An ion implantation region located in the active layer pattern and corresponding to a position of the first via hole
  • a source electrode and a drain electrode disposed on the insulating structure, the source electrode and the drain electrode being in contact with a surface of the ion implantation region through the first via hole to be in electrical contact with the active layer pattern.
  • thin film transistors can be classified into polysilicon thin film transistors and amorphous silicon thin film transistors according to different active layer materials.
  • Polycrystalline silicon has an electron mobility rate that is 200-300 times faster than that of disordered amorphous silicon because it has a molecular structure that is neat and directional in a crystal grain, and thus is more and more widely used.
  • Thin film transistors can be classified into a bottom gate type, a top gate type, and a coplanar type depending on the structure of the film layer.
  • the bottom gate type thin film transistor includes a gate electrode 12, a gate insulating layer 103, an active layer pattern 10, a source electrode 14 and a drain electrode 15, which are sequentially formed on the substrate 100, and a passivation layer 106.
  • the top gate type thin film transistor includes a source electrode 14 and a drain electrode 15, sequentially formed on a substrate 100, an active layer pattern 10, a gate insulating layer 103, and a gate electrode 12, and a passivation layer 106. As shown in FIG.
  • the coplanar thin film transistor includes an active layer pattern 2, a gate insulating layer 103, a gate electrode 1, an interlayer insulating layer 104, a source electrode 3, and a drain electrode 4 which are sequentially formed on a substrate 100, and is flat.
  • Layer 105 The coplanar thin film transistor includes an active layer pattern 2, a gate insulating layer 103, a gate electrode 1, an interlayer insulating layer 104, a source electrode 3, and a drain electrode 4 which are sequentially formed on a substrate 100, and is flat.
  • Layer 105 Layer 105.
  • the source electrode 3 and the drain electrode 4 are in electrical contact with the active layer pattern 2 through via holes penetrating the gate insulating layer 103 and the interlayer insulating layer 104.
  • the via it is necessary to simultaneously etch away the gate insulating layer 103 and the interlayer insulating layer 104.
  • the via holes in the through-gate insulating layer 103 and the interlayer insulating layer 104 are etched away, usually by a certain percentage of over-etching manner (that is, a certain percentage of the thickness direction is performed on the active layer pattern exposed corresponding to the via position) Etching), generally about 40%, which means that the active layer pattern corresponding to the via position needs to be subjected to long-time etching, resulting in a rough surface corresponding to the active layer pattern of the via position, with The increase in surface roughness of the source layer pattern may seriously affect the gold semi-electrical contact between the subsequently formed source electrode, drain electrode and active layer pattern.
  • the exposed active layer pattern 2 is ion-implanted to form an ion implantation region 22, thereby performing surface repair on the active layer pattern exposed at the position corresponding to the first via hole 8, which significantly improves the gold of the coplanar thin film transistor.
  • Semi-contact performance As shown in FIG. 5 and FIG. 6, before forming the source electrode 3 and the drain electrode 4, first through the first via 8 penetrating the gate insulating layer 103 and the interlayer insulating layer 104.
  • the exposed active layer pattern 2 is ion-implanted to form an ion implantation region 22, thereby performing surface repair on the active layer pattern exposed at the position corresponding to the first via hole 8, which significantly improves the gold of the coplanar thin film transistor.
  • Semi-contact performance As shown in FIG. 5 and FIG. 6, before forming the source electrode 3 and the drain electrode 4, first through the first via 8 penetrating the gate insulating layer 103 and the interlayer insulating layer 104.
  • the exposed active layer pattern 2 is ion-implanted
  • the insulating structure between the active layer pattern 2 and the source electrode 3 and the drain electrode 4 is not limited to the gate insulating layer 103 and the interlayer insulating layer 104, and may include other insulating layers, which are not limited herein.
  • the material of the active layer pattern 2 of the thin film transistor is polysilicon.
  • both ends of the active layer pattern 2 ie, regions other than the channel region of the active layer pattern 2
  • the source electrode 3 and the drain electrode 4 pass through the first via 8 and the exposed active layer pattern 2
  • a doped polysilicon active layer 21 is in electrical contact.
  • the active layer pattern 2 includes a polysilicon active layer 20 and a first doped polysilicon active layer 21 on both sides of the polysilicon active layer 20.
  • the specific formation process includes:
  • a buffer layer 101 is formed on the substrate 100, usually using SiNx/SiO 2 , and subjected to high-temperature treatment dehydrogenation after deposition to avoid affecting the semiconductor characteristics of the active layer pattern subsequently formed thereon. , see Figure 1;
  • an amorphous silicon film layer is formed on the buffer layer 101.
  • a polysilicon film layer is formed, and the polysilicon film layer is patterned (including photoresist coating, exposure and development, and engraving). Etching process) forming the active layer pattern 2, as shown in FIG. 1;
  • a photoresist is formed on the active layer pattern 2, and the photoresist is exposed and developed to form a pattern 102 of the photoresist;
  • ion implantation is performed on both ends of the active layer pattern 2 by using the photoresist pattern 102 formed as a mask to form a first doped polysilicon active layer 21, as shown in FIG. 2, and then the remaining photolithography is removed. gum.
  • the active layer pattern 2 formed by the above steps includes a polysilicon active layer 20 and a first doped polysilicon active layer 21 on both sides of the polysilicon active layer 20.
  • the array substrate further includes a storage capacitor for maintaining the pixel voltage unchanged during the display time of one frame of the picture.
  • the gate insulating layer 103 can serve as an insulating medium for the storage capacitor.
  • the first electrode 5 of the storage capacitor may be formed on the buffer layer 101 simultaneously with the active layer pattern 2, and the second electrode 6 of the storage capacitor may be simultaneously with the gate electrode 1 It is formed on the gate insulating layer 103, as shown in FIG.
  • the specific process of forming the thin film transistor and the storage capacitor is:
  • an amorphous silicon film layer is formed on the substrate 100, and after being crystallized by laser annealing, a polysilicon film layer is formed, and the polysilicon film layer is patterned (including coating and exposure of the photoresist). And developing, and etching process), forming a pattern of the first electrode 5 including the active layer pattern 2 and the storage capacitor;
  • a photoresist is formed on the pattern of the active pattern 2 and the first electrode 5 of the storage capacitor, and the photoresist is exposed and developed to form a pattern 102 of the photoresist.
  • both ends of the active layer pattern 2 are ion-implanted using the photoresist pattern 102 formed as a mask to form a first doped polysilicon active layer 21.
  • the pattern of the first electrode 5 of the storage capacitor is ion-implanted by using the photoresist pattern 102 formed as a mask to form a second doped polysilicon active layer, thereby forming a first electrode 5 of the storage capacitor, and then removing the remaining Photoresist
  • the active layer pattern 2 formed by the above steps includes a polysilicon active layer 20 and a first doped polysilicon active layer 21 on both sides of the polysilicon active layer 20.
  • a gate insulating layer 103 is formed on the active layer pattern 2 and the pattern of the first electrode 5 of the storage capacitor;
  • a gate metal layer is formed on the gate insulating layer 103, and the gate metal layer is patterned to form a pattern of the second electrode 6 including the gate electrode 1 and the storage capacitor.
  • the first electrode 5 or the second electrode 6 of the storage capacitor is electrically connected to the pixel electrode of the array substrate for maintaining the pixel voltage on the pixel electrode unchanged for a period of time.
  • the pixel electrode is a cathode or an anode of the OLED, and is electrically connected to a drain electrode of the thin film transistor.
  • the storage capacitor of the array substrate is formed. Since the insulating medium of the storage capacitor includes only the gate insulating layer and has a large capacity, the stability of the display can be ensured. At the same time, a storage capacitor is formed in the process of forming a thin film transistor, which simplifies the fabrication process.
  • FIG. 1 to FIG. 8 a process of fabricating an array substrate in the embodiment of the present application is specifically described below by taking a process of fabricating an AMOLED array substrate as an example.
  • Step a providing a substrate 100, such as a transparent glass substrate, a quartz substrate or an organic resin substrate;
  • Step b forming a buffer layer 101
  • a buffer layer 101 is formed on the substrate 100, and a material commonly used is SiNx/SiO 2 , and is subjected to high-temperature treatment dehydrogenation after the deposition is completed to avoid an influence on the semiconductor characteristics of the active layer formed thereon.
  • the buffer layer 101 may be a single layer structure, such as a silicon nitride layer or a silicon dioxide layer, or may be a composite layer structure, such as: a silicon nitride layer and a silicon dioxide layer, optionally, a dioxide dioxide
  • the silicon layer is disposed close to the subsequently formed active layer pattern because the H content in the SiO 2 is relatively small, thereby avoiding an influence on the semiconductor characteristics of the active layer pattern.
  • Step c forming an active layer pattern 2 of the thin film transistor and the first electrode 5 of the storage capacitor
  • Step c1 forming an amorphous silicon film layer on the substrate 100 of the step b, forming a polysilicon film layer after laser annealing, and patterning the polysilicon film layer (including photoresist coating, exposure, and The development, and etching process) forms a pattern of the active layer pattern 2 and the first electrode 5 of the storage capacitor as shown in FIG.
  • a photoresist is coated on the polysilicon film layer, and the photoresist is exposed to form a photoresist-retained region and a photoresist.
  • the region where the first electrode 5 of the capacitor is located, and the region where the photoresist is not reserved corresponds to other regions;
  • the photoresist of the photoresist remaining region is removed by a developing process to form a pattern of the first electrode 5 including the active layer pattern 2 and the storage capacitor;
  • Step c2 coating a photoresist on the substrate 100 of the step c1, and exposing and developing the photoresist to form a photoresist retention region 102 and a photoresist non-retained region, as shown in FIG. 2;
  • ion implantation is performed on both ends of the exposed active layer pattern 2 by using the photoresist retention region 102 formed as a mask to form a first doped polysilicon active layer 21, and a first electrode of the storage capacitor.
  • the pattern of 5 is ion-implanted to form a second doped polysilicon active layer as the first electrode 5 of the storage capacitor, and finally the remaining photoresist is removed;
  • Step d forming a gate insulating layer 103 on the substrate 100 completing the step c2, and forming a gate metal layer on the gate insulating layer 103, and patterning the gate metal layer to form a gate electrode 1 and a second electrode of the storage capacitor 6,
  • the gate insulating layer 103 is an insulating medium for the storage capacitor, as shown in FIG. 3;
  • the gate metal may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals, and the gate metal layer may be a single layer structure or a multilayer structure, and a plurality of layers.
  • the structure is such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, and the like.
  • a thickness of about 100 may be deposited on the substrate 100 on which the step c2 is completed by sputtering or thermal evaporation. -approximately The gate metal layer.
  • the gate insulating layer 103 may be a composite layer of any two of the silicon dioxide layer, the silicon oxynitride layer and the silicon nitride layer or a composite of a silicon dioxide layer, a silicon oxynitride layer and a silicon nitride layer.
  • the silicon dioxide layer is disposed close to the active layer pattern 2 because the H content in the SiO 2 is relatively small, thereby avoiding an influence on the semiconductor characteristics of the active layer pattern.
  • the gate insulating layer 103 may be formed on the substrate 100 on which the step c2 is completed by a process such as coating, chemical deposition, sputtering, or the like.
  • Step e forming an interlayer insulating layer 104 on the substrate 100 completing step d, forming a first via hole 8 in the gate insulating layer 103 and the interlayer insulating layer 104 by an etching process to expose the first doped polysilicon
  • the source layer 21 is as shown in FIG.
  • the interlayer insulating layer 104 may be formed on the gate electrode 1 and the second electrode 6 of the storage capacitor by a process such as coating, chemical deposition, sputtering, or the like, wherein the interlayer insulating layer 104 may be an inorganic insulating layer such as silicon dioxide. a composite layer of any two of the layers of the silicon oxynitride layer and the silicon nitride layer or a composite layer of three layers of a silicon dioxide layer, a silicon oxynitride layer and a silicon nitride layer.
  • the first via 8 penetrating the gate insulating layer 103 and the interlayer insulating layer 104 is formed by a certain percentage of overetching, and 40% of the thickness of the first doped polysilicon active layer 21 is etched away, thereby making the first
  • the via 8 extends to the exposed first doped polysilicon active layer 21 to ensure complete etching
  • the first via 8 in the through gate insulating layer 103 and the interlayer insulating layer 104 is removed.
  • Step f ion-implanting the exposed first doped polysilicon active layer 21 via the first via 8 to form an ion implantation region 22, as shown in FIG. 5, such that the active layer pattern 2 includes the polysilicon active layer 20.
  • a first doped polysilicon active layer 21 on both sides of the polysilicon active layer 20, and an ion implantation region 22 located in the first doped polysilicon active layer 21 and corresponding to the position of the first via 8 are provided.
  • Step g forming a source/drain metal layer on the substrate 100 completing the step f, and patterning the source/drain metal layer to form the source electrode 3 and the drain electrode 4, as shown in FIG.
  • the source/drain metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals.
  • the source/drain metal layer may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo or the like.
  • a layer of thickness may be deposited by magnetron sputtering, thermal evaporation or other film forming method on the substrate 100 subjected to step f. -approximately Source and drain metal layer,
  • the glue retention area corresponds to the area where the source electrode 3 and the drain electrode 4 are located, and the photoresist non-retention area corresponds to other areas; the source/drain metal layer of the photoresist non-retained area is completely etched by wet etching, and then stripped The remaining photoresist forms the source electrode 3 and the drain electrode 4.
  • Step h as shown in FIG. 7, a flat layer 105 is formed on the substrate 100 on which the step g is completed, and a second via hole 9 is formed in the flat layer 105 by an etching process to expose the drain electrode 4.
  • planarization layer 105 is an organic insulating layer capable of reducing the parasitic capacitance of the display panel.
  • Step i As shown in FIG. 8, a cathode 7 of an organic light emitting diode (OLED) is formed on the substrate 100 on which the step h is completed, and a passivation layer 106 is formed on the cathode 7, and the passivation layer 106 is covered. Above the thin film transistor.
  • OLED organic light emitting diode
  • the cathode 7 is electrically connected to the drain electrode 4 through the second via hole 9, and the cathode 7 is connected to the second electrode 6 as a storage capacitor through an electrical connection structure, so that the storage capacitor can be maintained in the display time of one frame.
  • the pixel voltage on the cathode 7 is constant, achieving stable display.
  • the material of the cathode 7 may be Ag/ITO (Indium Tin Oxide), wherein Ag has a light reflecting effect, and ITO has a high light transmittance.
  • Ag/ITO Indium Tin Oxide
  • the AMOLED array substrate formed by the above steps specifically includes:
  • An interlayer insulating layer 104 covering the gate electrode 1 and the second electrode 6 of the storage capacitor, a first via hole 8 formed in the gate insulating layer 103 and the interlayer insulating layer 104, the first via hole 8 extending to the ion implantation region 22;
  • the second via hole 9 is formed in the flat layer 105 to expose the drain electrode 4;
  • a passivation layer 106 of the thin film transistor is covered.
  • the AMOLED includes other structures such as an organic light-emitting layer, an anode, an electron transport layer, and a hole transport layer, which will not be described herein.
  • the technical solution of the present application can also be applied to a liquid crystal display panel.
  • the fabrication process of the thin film transistor is the same as the above steps a-i, but the pixel electrode of the liquid crystal display panel can only be a transparent material such as ITO.
  • the fabrication of the storage capacitor, the common electrode, and the like is the same as that of the prior art, and will not be described in detail herein.
  • An embodiment of the third aspect of the present application also provides a display device.
  • the display device includes the above array substrate.
  • the performance of the thin film transistor on the array substrate is improved, thereby ensuring the display quality of the display device.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the source electrode and the drain electrode of the thin film transistor are located in the active layer pattern. Upper, and the source electrode and the drain electrode are in electrical contact with the active layer pattern through the first via hole penetrating the insulating layer, wherein before the source electrode and the drain electrode are fabricated, Forming the ion implantation region by ion implantation of the exposed active layer pattern through the via hole penetrating the insulating structure, so that the etching process for forming the via hole may be damaged to damage the surface of the active layer pattern, Thereby, the gold semi-electrical contact performance of the source/drain electrodes and the active layer pattern is improved, the electrical characteristics of the thin film transistor are improved, and the display quality of the display device is ensured.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)

Abstract

公开了阵列基板及其制作方法、显示装置。所述阵列基板包括薄膜晶体管，其中源电极和漏电极位于有源层图案的上方，且所述源电极和所述漏电极通过贯穿绝缘结构的第一过孔与所述有源层图案电性接触，并在制作所述源电极和所述漏电极之前，经由所述第一过孔对所述有源层图案进行离子注入，形成离子注入区。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2014年09月25日在中国提交的中国专利申请号No.201410498723.9的优先权，其全部内容通过引用包含于此。
技术领域
本申请涉及显示技术领域，特别是涉及一种阵列基板及其制作方法、显示装置。
背景技术
有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，简称AMOLED)显示器件是一种新型的平板显示器件，与液晶显示器相比，由于有机发光二极管(Organic Light Emitting Diode，简称OLED)具有自发光功能，不需要背光源，因此，AMOLED显示器件的视角和对比度均优于液晶显示器，具有尺寸小、重量轻和功耗低等优点。同时，由于AMOLED显示器件采用低直流驱动薄膜晶体管(Thin-Film Transistor，简称TFT)，传输像素电压至OLED进行显示，还具有快速响应的优点。AMOLED显示器件还可以在更宽的温度范围内工作，生产成本较低。
TFT可分为多晶硅(p-Si)TFT与非晶硅(a-Si)TFT，两者的差异在于电晶体特性不同。由于非晶硅a-Si本身自有的缺陷问题，如缺陷态多导致的开态电流低、迁移率低、稳定性差，使得它在很多领域受到限制。而P-Si的分子结构在一颗晶粒(Grain)中的排列状态是整齐而有方向性的，因此电子移动率比排列杂乱的非晶硅快了200-300倍，得到越来越广泛的使用。
现有技术中，AMOLED的制作工艺包括：
在有源层图案上沉积绝缘结构，并在所述绝缘结构中形成过孔，露出有源层；
在所述绝缘结构上形成源电极和漏电极，源电极和漏电极通过所述过孔与有源层电性接触。
当所述绝缘结构包括至少两个绝缘层时，在所述绝缘结构中形成过孔时，需要同时刻蚀多个绝缘层，由于薄膜存在膜厚的均匀性和刻蚀的均匀性，为 保证玻璃基板每个位置上的第一过孔刻蚀完成，没有残留的情况，通常的技术方法是采用一定的百分比过刻的方式，一般为40％左右，意味着在刻蚀过程中，所述过孔处的有源层需要承受长时间的离子轰击，离子轰击会导致过孔处的有源层表面粗糙，缺陷数量剧增，后续形成源电极和漏电极后，金半接触的特性会受到影响，从而影响整个TFT的导通特性。
发明内容
本申请的实施例提供一种阵列基板及其制作方法、显示装置，用以解决绝缘结构中的过孔刻蚀工艺会造成位于下方的有源层表面粗糙，从而影响整个TFT的导通特性的问题。
为解决上述技术问题，本申请第一方面的实施例提供了一种制作阵列基板的方法。根据本申请的实施例，所述方法包括形成薄膜晶体管的步骤，所述形成薄膜晶体管的步骤包括：
在基板上形成有源层图案；
在所述有源层图案上形成绝缘结构；
形成贯穿所述绝缘结构的第一过孔，以暴露出对应于所述第一过孔位置的有源层图案，其中所述第一过孔延伸至暴露出的有源层图案的内部；
经由所述第一过孔对所述暴露出的有源层图案进行离子注入，形成离子注入区，其中所述离子注入区位于所述有源层图案中；
在所述绝缘结构上形成源电极和漏电极，其中所述源电极和所述漏电极通过所述第一过孔与所述离子注入区的表面接触，从而与所述有源层图案电性接触。
本申请第二方面的实施例还提供了一种阵列基板。根据本申请的实施例，所述阵列基板包括薄膜晶体管，其中所述薄膜晶体管进一步包括：
位于基板上的有源层图案；
覆盖所述有源层图案的绝缘结构，其中所述绝缘结构中包括第一过孔，所述第一过孔延伸至暴露出的有源层图案内部；
离子注入区，位于所述有源层图案中且对应于所述第一过孔的位置；
设置在所述绝缘结构上的源电极和漏电极，所述源电极和所述漏电极通过所述第一过孔与所述离子注入区的表面接触，进而与所述有源层图案电性接触。
本申请第三方面的实施例还提供一种显示装置。根据本申请的实施例， 所述显示装置包括如上所述的阵列基板。
本申请的上述技术方案的有益效果如下：
根据本申请的实施例，在薄膜晶体管中，所述源电极和所述漏电极位于所述有源层图案的上方，且所述源电极和所述漏电极通过贯穿所述绝缘结构的所述第一过孔与所述有源层图案电性接触，其中在制作所述源电极和所述漏电极之前，经由贯穿绝缘结构的所述第一过孔对所述暴露出的有源层图案进行离子注入，形成所述离子注入区，从而可以修复形成过孔的刻蚀工艺对有源层图案表面的造成破坏，从而改善所述源电极/所述漏电极与所述有源层图案的金半电性接触性能，进而提高了薄膜晶体管的电学特性，并保证了显示装置的显示品质。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1-图8显示了根据本申请实施例制作AMOLED过程的示意图；
图9为底栅型薄膜晶体管的结构示意图；
图10为顶栅型薄膜晶体管的结构示意图。
具体实施方式
在阵列基板的制作过程中，一般通过在绝缘层中制作过孔来实现不同导电层之间的电性连接，即不同导电层之间通过绝缘层中的过孔电性接触。当通过绝缘层中的过孔来实现薄膜晶体管的源电极/漏电极与有源层图案的金半电性接触(具体指源漏金属与半导体有源层的电性接触)时，在绝缘层中形成过孔的刻蚀工艺中，为确保完全刻蚀掉绝缘层中的过孔，往往会造成对应于过孔位置的有源层图案也被刻蚀，这导致了对应于过孔位置的有源层图案具有粗糙的表面，并由此影响后续形成的源电极、漏电极与有源层图案之间的金半电性接触，进而影响整个薄膜晶体管的电学特性。
针对上述技术问题，本申请的实施例提供了一种阵列基板及其制作方法。根据本申请的实施例，所述制作方法包括：在位于有源层图案上方的绝缘结构中形成第一过孔，以暴露出对应于所述第一过孔位置的有源层图案；经由 所述第一过孔对暴露出的有源层图案进行离子注入，形成离子注入区，使得后续形成的源电极/漏电极通过所述第一过孔与所述有源层图案的所述离子注入区电性接触，从而改善了所述源电极/所述漏电极与所述有源层图案的金半电性接触性能，进而提高了薄膜晶体管的电学特性。
下面将结合附图和实施例，对本申请的具体实施方式作进一步详细描述。以下实施例用于说明本申请，但不用来限制本申请的范围。
本申请第一方面的实施例提供了一种制作阵列基板的方法。根据本申请的实施例，所述方法包括形成薄膜晶体管的步骤，其中所述形成薄膜晶体管的步骤包括：
步骤S1、在基板上形成有源层图案；
步骤S2、在所述有源层图案上形成绝缘结构；
步骤S3、形成贯穿所述绝缘结构的第一过孔，以暴露出对应于所述第一过孔位置的有源层图案，其中所述第一过孔延伸至暴露出的有源层图案的内部；
步骤S4、经由所述第一过孔对所述暴露出的有源层图案进行离子注入，形成离子注入区，其中所述离子注入区位于所述有源层图案中；
步骤S5、在所述绝缘结构上形成源电极和漏电极，其中所述源电极和所述漏电极通过所述第一过孔与所述离子注入区的表面接触，从而与所述有源层图案电性接触。
在上述技术方案中，在制作所述源电极和所述漏电极之前，经由所述绝缘结构中的所述第一过孔对暴露出的有源层图案进行离子注入，形成所述离子注入区，由此可以修复由形成所述第一过孔的刻蚀工艺对有源层图案表面造成的破坏，从而改善了所述源电极/所述漏电极与所述有源层图案的金半电性接触性能，进而提高了薄膜晶体管的电学特性，并保证了阵列基板的质量。
本申请第二方面的实施例还提供了一种阵列基板。根据本申请的实施例，所述阵列基板包括薄膜晶体管，其中所述薄膜晶体管包括：
位于基板上的有源层图案；
覆盖所述有源层图案的绝缘结构，其中所述绝缘结构中包括第一过孔，所述第一过孔延伸至暴露出的有源层图案内部；
离子注入区，位于所述有源层图案中且对应于所述第一过孔的位置；
设置在所述绝缘结构上的源电极和漏电极，所述源电极和所述漏电极通过所述第一过孔与所述离子注入区的表面接触，从而与有源层图案电性接触。
现有技术中，根据有源层材料的不同，薄膜晶体管可分为多晶硅薄膜晶体管和非晶硅薄膜晶体管。多晶硅由于其具有在一颗晶粒中整齐且有方向性排列状态的分子结构，其电子移动速率相比与排列杂乱的非晶硅快了200-300倍，因而得到越来越广泛的使用。
根据膜层结构的不同，薄膜晶体管可分为底栅型、顶栅型和共面型。其中，如图9所示，底栅型薄膜晶体管包括依次形成于基板100上的栅电极12、栅绝缘层103、有源层图案10、源电极14和漏电极15，以及钝化层106。如图10所示，顶栅型薄膜晶体管包括依次形成于基板100上的源电极14和漏电极15、有源层图案10、栅绝缘层103和栅电极12，以及钝化层106。如图8所示，共面型薄膜晶体管包括依次形成于基板100上的有源层图案2、栅绝缘层103、栅电极1、层间绝缘层104、源电极3和漏电极4，以及平坦层105。
由上述内容可见，在共面型薄膜晶体管中，源电极3和漏电极4通过贯穿栅绝缘层103和层间绝缘层104的过孔与有源层图案2电性接触。在所述过孔的制作工艺中，需要同时刻蚀掉栅绝缘层103和层间绝缘层104，由于基板100上的薄膜存在膜厚的不均匀性和刻蚀的不均匀性，为保证完全刻蚀掉贯穿栅绝缘层103和层间绝缘层104中的过孔，通常采用一定百分比的过刻方式(即对对应于过孔位置暴露出的有源层图案在厚度方向上进行一定百分比的刻蚀)，一般为40％左右，这意味着对应于过孔位置的有源层图案需要承受长时间的刻蚀，导致对应于过孔位置的有源层图案具有粗糙的表面，随着有源层图案表面粗糙层度的加剧会严重影响后续形成的源电极、漏电极与有源层图案之间的金半电性接触。
而通过采用本申请实施例的技术方案，如图5和图6所示，在形成源电极3和漏电极4之前，首先经由贯穿栅绝缘层103和层间绝缘层104的第一过孔8对暴露出的有源层图案2进行离子注入，形成离子注入区22，从而对对应于第一过孔8位置暴露出的有源层图案进行表面修复，显著改善了共面型薄膜晶体管的金半接触性能。
当然，有源层图案2与源电极3、漏电极4之间的绝缘结构并不局限于栅绝缘层103和层间绝缘层104，还可以包括其它绝缘层，在此并不做限定。
作为一个示例性的实施方式，所述薄膜晶体管的有源层图案2的材料为多晶硅。通常地，为了提高金半接触性能，会对有源层图案2的两端(即有源层图案2除沟道区域以外的区域)进行离子掺杂，形成第一掺杂多晶硅有源层21，源电极3和漏电极4通过第一过孔8与暴露出的有源层图案2的第 一掺杂多晶硅有源层21电性接触。此时，有源层图案2包括多晶硅有源层20和位于多晶硅有源层20两侧的第一掺杂多晶硅有源层21，具体的形成过程包括：
首先，在基板100上形成缓冲层101，通常采用的材料为SiNx/SiO2，并在沉积完成后进行高温处理脱氢，以避免对后续形成在其上的有源层图案的半导体特性产生影响，参见图1所示；
之后，在缓冲层101上形成非晶硅膜层，经过激光退火晶化后，形成多晶硅膜层，对所述多晶硅膜层进行构图工艺(包括光刻胶的涂覆、曝光和显影，以及刻蚀工艺)形成有源层图案2，参见图1所示；
然后，在有源层图案2上形成光刻胶，并对光刻胶进行曝光，显影，形成光刻胶的图案102；
最后，以上述形成的光刻胶图案102作为掩膜对有源层图案2的两端进行离子注入，形成第一掺杂多晶硅有源层21，参见图2所示，然后去除剩余的光刻胶。
通过上述步骤形成的有源层图案2包括多晶硅有源层20和位于多晶硅有源层20两侧的第一掺杂多晶硅有源层21。
为了实现稳定显示，阵列基板还包括存储电容，用于在一帧画面的显示时间内，维持像素电压不变。在本申请实施例中，栅绝缘层103可以作为所述存储电容的绝缘介质。当有源层图案2的材料为多晶硅时，所述存储电容的第一电极5可以与有源层图案2同时形成在缓冲层101上，而存储电容的第二电极6可以与栅电极1同时形成在栅绝缘层103上，参见图3所示。
具体地，形成所述薄膜晶体管和所述存储电容的具体过程为：
首先，如图1所示，在基板100上形成非晶硅膜层，经过激光退火晶化后，形成多晶硅膜层，对所述多晶硅膜层进行构图工艺(包括光刻胶的涂覆、曝光和显影，以及刻蚀工艺)，形成包括有源层图案2和存储电容的第一电极5的图案；
之后，如图2所示，在有源图案2和存储电容的第一电极5的图案的上形成光刻胶，并对光刻胶进行曝光，显影，形成光刻胶的图案102。之后，以上述形成的光刻胶图案102为掩膜对有源层图案2的两端进行离子注入，形成第一掺杂多晶硅有源层21。同时以上述形成的光刻胶图案102为掩膜对存储电容的第一电极5的图案进行离子注入，形成第二掺杂多晶硅有源层，从而形成存储电容的第一电极5，然后去除剩余的光刻胶；
通过上述步骤形成的有源层图案2包括多晶硅有源层20和位于所述多晶硅有源层20两侧的第一掺杂多晶硅有源层21。
然后，参见图3所示，在有源层图案2和存储电容的第一电极5的图案上形成栅绝缘层103；
最后，在栅绝缘层103上形成栅金属层，对所述栅金属层进行构图工艺，形成包括栅电极1和存储电容的第二电极6的图案。其中，存储电容的第一电极5或第二电极6与阵列基板的像素电极电性连接，用于在一段时间内维持像素电极上的像素电压不变。当阵列基板为AMOLED阵列基板时，所述像素电极为OLED的阴极或阳极，与薄膜晶体管的漏电极电性连接。
至此，形成阵列基板的存储电容，由于存储电容的绝缘介质仅包括栅绝缘层，并且具有较大容量，能够保证显示的稳定性。同时，在形成薄膜晶体管的过程中形成存储电容，简化了制作工艺。
结合图1-图8所示，下面以制作AMOLED阵列基板的过程为例，具体介绍本申请实施例中制作阵列基板的方法。
步骤a、提供基板100，例如：透明的玻璃基板、石英基板或有机树脂基板；
步骤b、形成缓冲层101
在基板100上形成缓冲层101，通常采用的材料为SiNx/SiO2，并在沉积完成后进行高温处理脱氢，以避免对后续形成在其上有源层的半导体特性产生影响。
其中，缓冲层101可以为单层结构，如：氮化硅层或二氧化硅层，也可以为复合层结构，如：包括氮化硅层和二氧化硅层，可选地，将二氧化硅层设置为靠近后续形成的有源层图案，因为SiO2中H含量比较小，从而避免了对有源层图案的半导体特性产生影响。
步骤c、形成薄膜晶体管的有源层图案2和存储电容的第一电极5
步骤c1、在完成步骤b的基板100上形成非晶硅膜层，经过激光退火晶化后，形成多晶硅膜层，对所述多晶硅膜层进行构图工艺(包括光刻胶的涂覆、曝光和显影，以及刻蚀工艺)形成有源层图案2和存储电容的第一电极5的图案，如图1所示。
具体的，在完成步骤b的基板100上形成多晶硅膜层后，首先，在多晶硅膜层上涂覆光刻胶，并对光刻胶进行曝光，形成包括光刻胶保留区域和光刻胶不保留区域的图案，其中，光刻胶保留区域对应有源层图案2以及存储 电容的第一电极5所在的区域，光刻胶不保留区域对应其它区域；
然后，通过干法刻蚀去除光刻胶不保留区域对应的多晶硅膜层；
最后，通过显影工艺去除光刻胶保留区域的光刻胶，形成包括有源层图案2和存储电容的第一电极5的图案；
步骤c2、在完成步骤c1的基板100上涂覆光刻胶，并对光刻胶进行曝光、显影，形成光刻胶保留区域102和光刻胶不保留区域，如图2所示；
然后，以上述形成的光刻胶保留区域102为掩膜对暴露出的有源层图案2的两端进行离子注入，形成第一掺杂多晶硅有源层21，以及对存储电容的第一电极5的图案进行离子注入，形成第二掺杂多晶硅有源层，作为存储电容的第一电极5，最后并去除剩余的光刻胶；
步骤d、在完成步骤c2的基板100上形成栅绝缘层103，并在栅绝缘层103上形成栅金属层，对所述栅金属层进行构图工艺，形成栅电极1和存储电容的第二电极6，栅绝缘层103为存储电容的绝缘介质，如图3所示；
其中，栅金属可以是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。可以采用溅射或热蒸发的方法在完成步骤c2的基板100上沉积一层厚度为约
Figure PCTCN2015070885-appb-000001
-约
Figure PCTCN2015070885-appb-000002
的栅金属层。
栅绝缘层103可以为二氧化硅层、氮氧化硅层和氮化硅层中任意两个膜层的复合层或二氧化硅层、氮氧化硅层和氮化硅层三个膜层的复合层。可选的，将二氧化硅层设置在靠近有源层图案2的位置，因为SiO2中H含量比较小，从而避免对有源层图案的半导体特性产生影响。具体可以通过涂覆、化学沉积、溅射等工艺在完成步骤c2的基板100上形成栅绝缘层103。
步骤e、在完成步骤d的基板100上形成层间绝缘层104，通过刻蚀工艺在栅绝缘层103和层间绝缘层104中形成第一过孔8，以暴露出第一掺杂多晶硅有源层21，如图4所示。
具体可以通过涂覆、化学沉积、溅射等工艺在栅电极1和存储电容的第二电极6上形成层间绝缘层104，其中，层间绝缘层104可以为无机绝缘层，如二氧化硅层、氮氧化硅层和氮化硅层中任意两个膜层的复合层或二氧化硅层、氮氧化硅层和氮化硅层三个膜层的复合层。
然后，采用一定百分比过刻的方式形成贯穿栅绝缘层103和层间绝缘层104的第一过孔8，第一掺杂多晶硅有源层21厚度的40％被刻蚀掉，从而使得第一过孔8延伸至暴露出的第一掺杂多晶硅有源层21内部，保证完全刻蚀 掉贯穿栅绝缘层103和层间绝缘层104中的第一过孔8。
步骤f、经由第一过孔8对暴露出的第一掺杂多晶硅有源层21进行离子注入，形成离子注入区22，如图5所示，使得有源层图案2包括多晶硅有源层20、位于多晶硅有源层20两侧的第一掺杂多晶硅有源层21，以及位于第一掺杂多晶硅有源层21中并对应于第一过孔8位置的离子注入区22。
步骤g、在完成步骤f的基板100上形成源漏金属层，对所述源漏金属层进行构图工艺，形成源电极3和漏电极4，如图6所示。
其中，源漏金属层可以是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。
具体地，可以在经过步骤f的基板100上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度为约
Figure PCTCN2015070885-appb-000003
-约
Figure PCTCN2015070885-appb-000004
的源漏金属层，
然后在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光、显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于源电极3和漏电极4的所在区域，光刻胶不保留区域对应于其他区域；通过湿法刻蚀完全刻蚀掉光刻胶不保留区域的源漏金属层，然后剥离剩余的光刻胶，形成源电极3和漏电极4。
步骤h、如图7所示，在完成步骤g的基板100上形成平坦层105，通过刻蚀工艺在平坦层105中形成第二过孔9，以暴露出漏电极4。
可选地，平坦层105为有机绝缘层，能够降低显示面板的寄生电容。
步骤i、如图8所示，在完成步骤h的基板100上形成有机发光二极管器件(Organic light emitting diode，OLED)的阴极7，并在阴极7上形成钝化层106，钝化层106覆盖在薄膜晶体管的上方。
其中，阴极7通过第二过孔9与漏电极4电性接触，且阴极7通过电性连接结构与作为存储电容的第二电极6连接，从而存储电容能够在一帧画面的显示时间内维持阴极7上的像素电压不变，实现稳定显示。
阴极7的材料可以为Ag/ITO(Indium Tin Oxide)，其中，Ag具有反光作用，ITO的透光性较高。
制作AMOLED其他结构的工艺与现有技术相同，如：有机发光层、阳极、电子传输层、空穴传输层，在此不再赘述。
如图8所示，通过上述步骤形成的AMOLED阵列基板具体包括：
位于基板100上的缓冲层101；
设置在缓冲层101上的包含有源层图案2和存储电容的第一电极5，其中，有源层图案2包括多晶硅有源层20和位于多晶硅有源层20两侧的第一掺杂多晶硅有源层21，以及离子注入区22，其中离子注入区22位于第一掺杂多晶硅有源层21中，第二掺杂多晶硅有源层作为存储电容的第一电极5；
覆盖有源层图案2和存储电容的第一电极5的栅绝缘层103，作为存储电容的绝缘介质；
设置在栅绝缘层103上的栅电极1和存储电容的第二电极6，栅电极1和存储电容的第二电极6由同一栅金属层形成；
覆盖栅电极1和存储电容的第二电极6的层间绝缘层104，栅绝缘层103和层间绝缘层104中形成有第一过孔8，所述第一过孔8延伸至离子注入区22中；
设置在层间绝缘层104上的源电极3和漏电极4，源电极3和漏电极4通过所述第一过孔8与离子注入区22表面接触，进而与第一掺杂多晶硅有源层21电性接触；
覆盖源电极3和漏电极4的平坦层105，平坦层105中形成有第二过孔9，以暴露出漏电极4；
设置在平坦层105上的有机发光二极管的阴极7，阴极7通过所述第二过孔9与漏电极4电性接触，存储电容的第一电极5与有机发光二极管的阴极7电性连接；
覆盖所述薄膜晶体管的钝化层106。
同样AMOLED还包括其他结构，如：有机发光层、阳极、电子传输层、空穴传输层，在此不再赘述。
当然，本申请的技术方案也可以应用于液晶显示面板，在制作液晶显示面板的过程中，薄膜晶体管的制作工艺与上述步骤a-i相同，但是液晶显示面板的像素电极只能为ITO等透明材料。至于存储电容、公共电极等结构的制作与现有技术相同，在此不再详述。
本申请第三方面的实施例还提供一种显示装置。根据本申请的实施例，所述显示装置包括上述阵列基板。由于提高了阵列基板上薄膜晶体管的性能，进而保证了显示装置的显示品质。所述显示装置可以为：液晶面板、电子纸、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本申请的技术方案中，薄膜晶体管的源电极和漏电极位于有源层图案的 上方，且所述源电极和所述漏电极通过贯穿所述绝缘层的所述第一过孔与所述有源层图案电性接触，其中在制作所述源电极和所述漏电极之前，经由贯穿绝缘结构的所述过孔对所述暴露出的有源层图案进行离子注入，形成所述离子注入区，从而可以修复形成过孔的刻蚀工艺对有源层图案表面的造成破坏，从而改善了源电极/漏电极与所述有源层图案的金半电性接触性能，提高了薄膜晶体管的电学特性，保证了了显示装置的显示品质。
以上所述仅是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视本公开的保护范围。

Claims (15)

  1. 一种制作阵列基板的方法，包括形成薄膜晶体管的步骤，其中所述形成薄膜晶体管的步骤包括：
    在基板上形成有源层图案；
    在所述有源层图案上形成绝缘结构；
    形成贯穿所述绝缘结构的第一过孔，以暴露出对应于所述第一过孔位置的有源层图案，其中所述第一过孔延伸至暴露出的有源层图案的内部；
    经由所述第一过孔对所述暴露出的有源层图案进行离子注入，形成离子注入区，其中所述离子注入区位于所述有源层图案中；
    在所述绝缘结构上形成源电极和漏电极，其中所述源电极和所述漏电极通过所述第一过孔与所述离子注入区的表面接触，从而与所述有源层图案电性接触。
  2. 根据权利要求1所述的方法，其中所述绝缘结构包括至少两层绝缘层。
  3. 根据权利要求1或2所述的方法，其中在所述有源层图案上形成绝缘结构的步骤包括形成栅绝缘层和层问绝缘层。
  4. 根据权利要求3所述的方法，进一步包括在所述栅绝缘层和所述层问绝缘层之间形成栅电极，其中所述栅电极位于对应于所述有源层图案位置的所述栅绝缘层上。
  5. 根据权利要求1-4任一项所述的方法，还包括形成存储电容的步骤，其中所述栅绝缘层为所述存储电容的绝缘介质。
  6. 根据权利要求5所述的方法，进一步包括：
    Step1：在所述基板上形成多晶硅膜层，通过构图工艺形成包括所述有源层和所述存储电容的第一电极的图案；
    Step2：在包括所述有源层和所述存储电容的所述第一电极的图案上形成光刻胶，通过曝光、显影形成光刻胶图案，以暴露出所述有源层图案中多晶硅有源层以外的区域和所述存储电容的所述第一电极的图案；
    Step3：以所述光刻胶图案为掩膜板，对暴露出所述有源层图案中多晶硅有源层以外的区域和所述存储电容的所述第一电极的图案进行离子注入，分别形成第一掺杂多晶硅有源层和第二掺杂多晶硅有源层，其中所述第二掺杂多晶硅有源层作为所述存储电容的所述第一电极；
    Step4：在完成Step3的包括所述有源层和所述存储电容的所述第一电极 的图案上形成所述栅绝缘层；
    Step5：在所述栅绝缘层上形成栅金属层，通过构图工艺形成包括所述栅电极和所述存储电容的第二电极的图案；
    Step6：在包含所述栅电极和所述存储电容的所述第二电极的图案上形成层问绝缘层；
    Step7：形成贯穿所述栅绝缘层和所述层问绝缘层的所述第一过孔，以暴露出对应于所述第一过孔位置的第一掺杂多晶硅有源层，其中所述第一过孔延伸至暴露出的第一掺杂多晶硅有源层内部；
    Step8：经由所述第一过孔对所述暴露出的第一掺杂多晶硅有源层进行离子注入，形成离子注入区；
    Step9：在所述层问绝缘层上形成所述源电极和所述漏电极，所述源电极和所述漏电极通过所述第一过孔与所述离子注入区的表面接触，进而与所述第一掺杂多晶硅有源层电性接触。
  7. 根据权利要求1-6任一项所述的方法，其中所述阵列基板为有源矩阵有机发光二极管阵列基板，所述制作方法还包括：
    在所述源电极和所述漏电极上形成平坦层；
    在所述平坦层中形成第二过孔，以暴露出所述漏电极；
    在所述平坦层上形成所述有机发光二极管的阴极，其中所述阴极通过所述第二过孔与所述漏电极电性接触，所述存储电容与所述阴极电性连接。
  8. 一种阵列基板，包括薄膜晶体管，其中所述薄膜晶体管包括：
    位于基板上的有源层图案；
    覆盖所述有源层图案的绝缘结构，其中所述绝缘结构中包括第一过孔，所述第一过孔延伸至暴露出的有源层图案内部；
    离子注入区，位于所述有源层图案中且对应于所述第一过孔的位置；
    设置在所述绝缘结构上的源电极和漏电极，所述源电极和所述漏电极通过所述第一过孔与所述离子注入区的表面接触，进而与所述有源层图案电性接触。
  9. 根据权利要求8所述的阵列基板，其中所述绝缘结构包括至少两层绝缘层。
  10. 根据权利要求8或9所述的阵列基板，其中所述绝缘结构包括栅绝缘层和层问绝缘层。
  11. 根据权利要求10所述的阵列基板，其中所述栅电极位于所述栅绝缘 层和所述层问绝缘层之间，并位于对应于所述有源层图案位置的所述栅绝缘层上。
  12. 根据权利要求8-11任一项所述的阵列基板，还包括：
    存储电容，其中所述栅绝缘层为所述存储电容的绝缘介质。
  13. 根据权利要求12所述的阵列基板，进一步包括：
    位于基板上的包括所述有源层和所述存储电容的所述第一电极的图案，所述有源层图案包括多晶硅有源层、位于所述多晶硅有源层两侧的第一掺杂多晶硅有源层以及离子注入区，其中所述离子注入区位于所述第一掺杂多晶硅有源层中，所述存储电容的所述第一电极图案经过离子注入处理后形成第二掺杂多晶硅有源层作为所述存储电容的所述第一电极；
    覆盖包含所述有源层和所述存储电容的所述第一电极的图案的栅绝缘层；
    设置在所述栅绝缘层上的所述栅电极和所述存储电容的第二电极，其中所述栅电极和所述存储电容的所述第二电极由同一栅金属层形成；
    覆盖所述栅电极和所述存储电容的所述第二电极的层问绝缘层，其中贯穿所述栅绝缘层和层问绝缘层形成有第一过孔，所述第一过孔延伸至所述离子注入区内部；
    设置在所述层问绝缘层上的所述源电极和所述漏电极，所述源电极和所述漏电极通过所述第一过孔与所述离子注入区表面接触，进而与第一掺杂多晶硅有源层电性接触。
  14. 根据权利要求8-13任一所述的阵列基板，其中所述阵列基板为有源矩阵有机发光二极管阵列基板，所述阵列基板还包括：
    覆盖所述源电极和所述漏电极的平坦层，其中所述平坦层中形成有第二过孔，以暴露出所述漏电极；
    设置在所述平坦层上的所述有机发光二极管的阴极，其中所述阴极通过所述第二过孔与所述漏电极电性接触，所述存储电容与所述阴极电性连接。
  15. 一种显示装置，包括如权利要求8-14任一项所述的阵列基板。
PCT/CN2015/070885 2014-09-25 2015-01-16 阵列基板及其制作方法、显示装置 WO2016045270A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/771,320 US9627461B2 (en) 2014-09-25 2015-01-16 Array substrate, its manufacturing method and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410498723.9 2014-09-25
CN201410498723.9A CN104362125B (zh) 2014-09-25 2014-09-25 阵列基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2016045270A1 true WO2016045270A1 (zh) 2016-03-31

Family

ID=52529374

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/070885 WO2016045270A1 (zh) 2014-09-25 2015-01-16 阵列基板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US9627461B2 (zh)
CN (1) CN104362125B (zh)
WO (1) WO2016045270A1 (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952934B (zh) * 2015-06-25 2018-05-01 京东方科技集团股份有限公司 薄膜晶体管及制造方法、阵列基板、显示面板
KR20170031313A (ko) * 2015-09-10 2017-03-21 삼성디스플레이 주식회사 디스플레이 장치
CN105097675B (zh) * 2015-09-22 2018-01-30 深圳市华星光电技术有限公司 阵列基板及其制备方法
CN105206626B (zh) * 2015-11-09 2018-11-20 深圳市华星光电技术有限公司 阵列基板及其制备方法、显示装置
KR102566630B1 (ko) 2015-12-30 2023-08-16 엘지디스플레이 주식회사 유기발광표시장치
JP6673731B2 (ja) * 2016-03-23 2020-03-25 株式会社ジャパンディスプレイ 表示装置及びその製造方法
CN105679775B (zh) * 2016-04-21 2019-04-23 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板和显示装置
CN105867037A (zh) * 2016-06-17 2016-08-17 武汉华星光电技术有限公司 阵列基板、阵列基板的制备方法及液晶显示面板
US9704965B1 (en) * 2016-09-27 2017-07-11 International Business Machines Corporation Semiconductor device with self-aligned carbon nanotube gate
CN106601778B (zh) * 2016-12-29 2019-12-24 深圳市华星光电技术有限公司 Oled背板及其制作方法
CN106847743B (zh) * 2017-02-07 2019-12-24 武汉华星光电技术有限公司 Tft基板及其制作方法
KR102536816B1 (ko) * 2017-09-15 2023-05-24 엘지디스플레이 주식회사 박막 트랜지스터 및 표시 장치
US10424628B2 (en) * 2018-01-09 2019-09-24 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Manufacturing method of OLED backplane
CN108461520A (zh) * 2018-01-09 2018-08-28 深圳市华星光电半导体显示技术有限公司 一种oled背板及其制备方法
CN109755260A (zh) * 2018-12-24 2019-05-14 惠科股份有限公司 一种显示面板、显示面板的制造方法和显示装置
WO2020140232A1 (zh) * 2019-01-03 2020-07-09 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
KR20200110554A (ko) 2019-03-14 2020-09-24 삼성디스플레이 주식회사 표시 장치
CN110600369A (zh) * 2019-08-09 2019-12-20 长江存储科技有限责任公司 半导体器件的制备方法及半导体器件
CN110600381A (zh) * 2019-08-26 2019-12-20 深圳市华星光电半导体显示技术有限公司 阵列基板和阵列基板的制备方法
CN110504164B (zh) * 2019-08-27 2022-04-15 京东方科技集团股份有限公司 薄膜晶体管及其制造方法和显示装置
CN113141780A (zh) * 2019-11-01 2021-07-20 京东方科技集团股份有限公司 薄膜晶体管及其制造方法和显示装置
CN111415995B (zh) * 2020-04-01 2023-05-26 合肥鑫晟光电科技有限公司 一种显示面板、其制作方法及显示装置
CN111863839B (zh) * 2020-07-27 2023-09-22 合肥鑫晟光电科技有限公司 一种阵列基板、其制备方法及显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101206325A (zh) * 2006-12-22 2008-06-25 Lg.菲利浦Lcd株式会社 具有光敏元件的液晶显示器件及其制造方法
CN102709185A (zh) * 2011-07-25 2012-10-03 京东方科技集团股份有限公司 含有多晶硅有源层的薄膜晶体管、其制造方法及阵列基板
CN103296034A (zh) * 2013-05-28 2013-09-11 京东方科技集团股份有限公司 一种阵列基板、制备方法以及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05275449A (ja) * 1992-03-26 1993-10-22 Seiko Epson Corp 薄膜半導体装置及びその製造方法
JP3311850B2 (ja) * 1993-12-27 2002-08-05 株式会社東芝 薄膜トランジスタの製造方法
KR100611148B1 (ko) * 2003-11-25 2006-08-09 삼성에스디아이 주식회사 박막트랜지스터, 그의 제조방법 및 이를 사용하는 유기전계발광소자
TWI337754B (en) * 2007-04-20 2011-02-21 Au Optronics Corp Semiconductor structure of display device and method for fabricating the same
CN101681955B (zh) * 2007-07-19 2011-09-14 夏普株式会社 显示装置及其制造方法
JP2009206434A (ja) * 2008-02-29 2009-09-10 Hitachi Displays Ltd 表示装置およびその製造方法
JP2010039393A (ja) * 2008-08-07 2010-02-18 Hitachi Displays Ltd 表示装置及び表示装置の製造方法
JP5323604B2 (ja) * 2009-07-30 2013-10-23 株式会社ジャパンディスプレイ 表示装置及びその製造方法
CN103107095A (zh) * 2013-01-25 2013-05-15 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板、显示装置
CN104143533B (zh) * 2014-08-07 2017-06-27 深圳市华星光电技术有限公司 高解析度amoled背板制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101206325A (zh) * 2006-12-22 2008-06-25 Lg.菲利浦Lcd株式会社 具有光敏元件的液晶显示器件及其制造方法
CN102709185A (zh) * 2011-07-25 2012-10-03 京东方科技集团股份有限公司 含有多晶硅有源层的薄膜晶体管、其制造方法及阵列基板
CN103296034A (zh) * 2013-05-28 2013-09-11 京东方科技集团股份有限公司 一种阵列基板、制备方法以及显示装置

Also Published As

Publication number Publication date
US20160351643A1 (en) 2016-12-01
CN104362125B (zh) 2017-10-13
US9627461B2 (en) 2017-04-18
CN104362125A (zh) 2015-02-18

Similar Documents

Publication Publication Date Title
WO2016045270A1 (zh) 阵列基板及其制作方法、显示装置
US9768323B2 (en) Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
US9478562B2 (en) Array substrate and manufacturing method thereof, display device, thin film transistor and manufacturing method thereof
US9312277B2 (en) Array substrate for display device and method of fabricating the same
US9748280B2 (en) Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device
US9991295B2 (en) Array substrate manufactured by reduced times of patterning processes manufacturing method thereof and display apparatus
US9799677B2 (en) Structure of dual gate oxide semiconductor TFT substrate
US20150214373A1 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
WO2016176881A1 (zh) 双栅极tft基板的制作方法及其结构
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
US20160027813A1 (en) Array substrate and manufacturing method thereof and display apparatus
WO2016000342A1 (zh) 阵列基板及其制作方法、显示装置
WO2017173712A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
US9876038B2 (en) Array substrate and manufacturing method thereof and display device
US10615282B2 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
JP2019537282A (ja) アレイ基板とその製造方法及び表示装置
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
WO2015161523A1 (zh) 薄膜晶体管及有机发光二极管显示器制备方法
WO2016173012A1 (zh) 薄膜晶体管阵列基板及其制作方法
WO2019179137A1 (zh) 阵列基板及其制造方法、显示面板、电子装置
TWI495110B (zh) 顯示面板及其製作方法
WO2017028493A1 (zh) 薄膜晶体管及其制作方法、显示器件
WO2020037850A1 (zh) 阵列基板及其制造方法、显示面板
KR101831080B1 (ko) 박막 트랜지스터 기판의 제조 방법 및 이를 이용하여 제조된 박막 트랜지스터 기판
KR101257928B1 (ko) 박막 트랜지스터 및 그 제조방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14771320

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15844246

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 01.06.2017)

122 Ep: pct application non-entry in european phase

Ref document number: 15844246

Country of ref document: EP

Kind code of ref document: A1