CN105867037A - 阵列基板、阵列基板的制备方法及液晶显示面板 - Google Patents

阵列基板、阵列基板的制备方法及液晶显示面板 Download PDF

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CN105867037A
CN105867037A CN201610431928.4A CN201610431928A CN105867037A CN 105867037 A CN105867037 A CN 105867037A CN 201610431928 A CN201610431928 A CN 201610431928A CN 105867037 A CN105867037 A CN 105867037A
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layer
face
electrode
perforation
channel layer
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秦芳
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/126,381 priority patent/US20180031931A1/en
Priority to PCT/CN2016/089999 priority patent/WO2017215065A1/zh
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    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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Abstract

本发明提供一种阵列基板、阵列基板的制备方法及液晶显示面板。阵列基板包括：基板；沟道层，邻近基板的表面设置；第一绝缘层，覆盖沟道层；栅极，设置在第一绝缘层上；第二绝缘层，覆盖栅极，开设有第一、第二贯孔；源极，设置在第二绝缘层上且通过第一贯孔与沟道层电连接；漏极，设置在第二绝缘层上，与漏极间隔设置且通过第二贯孔与沟道层电连接；平坦层，覆盖源极及漏极，开设第三贯孔；公共电极，设置在平坦层上；钝化层，覆盖公共电极，钝化层包括HfO2，钝化层开设有与第三贯孔连通的第四贯孔；像素电极，设置在钝化层上，通过第三、第四贯孔与漏极电连接，且像素电极对应公共电极设置，像素电极、钝化层及公共电极构成存储电容。

Description

阵列基板、阵列基板的制备方法及液晶显示面板
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板、阵列基板的制备方法及液晶显示面板。
背景技术
显示设备，比如液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。液晶显示面板通常包括阵列基板、彩膜基板及液晶层。所述阵列基板和所述彩膜基板相对且间隔设置，所述液晶层夹设在所述阵列基板及所述彩膜基板之间。所述阵列基板包括呈阵列状分布的薄膜晶体管，每个薄膜晶体管均与一个存储电容相连。现有技术中，由于构成存储电容中的介质层的通常为SiOx，因此，所述介质层的通常较小，从而导致存储电容的电容值较小。
发明内容
本发明提供一种阵列基板，所述阵列基板包括：
基板；
沟道层，邻近所述基板的表面设置；
第一绝缘层，覆盖所述沟道层；
栅极，设置在所述第一绝缘层远离所述沟道层的表面；
第二绝缘层，覆盖所述栅极，且所述第二绝缘层上开设有间隔设置的第一贯孔和第二贯孔；
源极，设置在所述第二绝缘层上，且所述源极通过所述第一贯孔与所述沟道层电连接；
漏极，设置在所述第二绝缘层上，且所述漏极通过所述第二贯孔与所述沟道层电连接，且所述漏极与所述源极间隔设置；
平坦层，覆盖所述源极及所述漏极，所述平坦层对应所述漏极开设第三贯孔；
公共电极，设置在所述平坦层上；
钝化层，覆盖所述公共电极，且所述钝化层包括HfO2，所述钝化层对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
像素电极，设置在所述钝化层上，所述像素电极通过所述第三贯孔及所述第四贯孔与所述漏极电连接，且所述像素电极对应所述公共电极设置，所述像素电极、所述钝化层及所述公共电极构成存储电容。
其中，所述阵列基板还包括：
缓冲层，设置在所述基板上；
所述沟道层设置在所述缓冲层远离所述基板的表面。
其中，所述阵列基板还包括：
第一接触部和第二接触部，所述第一接触部和所述第二接触部分别与所述沟道层接触，且所述第一接触部与所述第二接触部间隔设置；
所述源极通过所述第一贯孔与所述第一接触部相连，所述第一接触部用于减小所述源极与所述沟道层之间的接触电阻；
所述漏极通过所述第二贯孔与所述第二接触部相连，所述第二接触部用于减小所述漏极与所述沟道层之间的接触电阻。
其中，所述沟道层包括相对设置的第一端面和第二端面，所述第一端面和所述第二端面均与所述沟道层邻近所述基板设置的表面相交，所述第一绝缘层包括相对设置的第三端面和第四端面，所述第三端面和所述第四端面均与所述第一绝缘层覆盖所述沟道层的表面相交，所述栅极包括相对设置的第五端面和第六端面，所述第五端面和所述第六端面均与所述栅极设置在所述第一绝缘层上的表面相交，
且所述第一端面、所述第三端面及所述第五端面共面，所述第二端面、所述第四端面及所述第六端面共面。
其中，所述第五端面相较于所述第六端面邻近所述源极设置，所述第六端面相较于所述第五端面邻近所述漏极设置，所述第五端面与所述源极邻近所述栅极的表面所在的平面之间的距离大于或者等于零；所述第六端面与所述漏极邻近所述栅极的表面所在的平面之间的距离大于或者等于零。
相较于现有技术，本发明的阵列基板中的钝化层中包括HfO2，所述HfO2具有较高的介电常数和较高的透光率。当所述公共电极、所述钝化层及所述像素电极形成存储电容时，在所述公共电极和所述钝化层的正对面积不变时，且所述钝化层厚度一定的情况下，可以提高所述存储电容的电容大小。当所述存储电容的电容大小不变，且所述钝化层的厚度不变时，可以减小存储电容的面积，因此，可以提高所述阵列基板所应用的显示面板的画素稳定性及所述阵列基板的开口率。
本发明还提供了一种阵列基板的制备方法，所述阵列基板的制备方法包括：
提供基板；
邻近所述基板的表面形成沟道层；
形成覆盖所述沟道层的第一绝缘层；
形成设置在所述第一绝缘层远离所述沟道层的栅极；
形成覆盖所述栅极的第二绝缘层，且在所述第二绝缘层上开设间隔设置的第一贯孔和第二贯孔；
在所述第二绝缘层上形成间隔设置的源极和漏极，且所述源极通过所述第一贯孔与所述沟道层电连接，所述漏极通过所述第二贯孔与所述沟道层电连接；
形成覆盖所述源极和所述漏极的平坦层，所述平坦层对应所述漏极开设第三贯孔；
形成设置在所述平坦层的公共电极；
形成覆盖所述公共电极且包括HfO2的钝化层，且在所述钝化层上对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
形成设置在所述钝化层上，对应所述公共电极设置，且通过所述第三贯孔及所述第四贯孔与所述漏极电连接的像素电极，所述像素电极、所述钝化层及所述公共电极构成存储电容。
其中，所述阵列基板的制备方法还包括：
形成设置在所述基板上的缓冲层；
所述步骤“邻近所述基板的表面形成沟道层”包括：
在所述缓冲层远离所述基板的表面形成所述沟道层。
其中，所述步骤“邻近所述基板的表面形成沟道层”，“形成覆盖所述沟道层的第一绝缘层；”及“形成设置在所述第一绝缘层远离所述沟道层的栅极”包括：
邻近所述基板的表面依次形成层叠设置的氧化物半导体层、第一绝缘材料层及第一金属层；
形成覆盖所述第一金属层的第一光刻胶层；
图案化所述第一光刻胶层以保留设置在所述第一金属层中部的第一光刻胶图案；
以所述第一光刻胶图案为掩膜，蚀刻未被所述第一光刻胶图案保护的第一金属层及第一绝缘材料层以分别形成栅极及第一绝缘层；
对裸露的氧化物半导体层进行离子处理，以形成第一接触部及第二接触部，未进行离子处理的氧化物半导体层为所述沟道层；
剥离所述第一光刻胶图案。
其中，所述步骤“在所述第二绝缘层上形成间隔设置的源极和漏极，且所述源极通过所述第一贯孔与所述沟道层电连接，所述漏极通过所述第二贯孔与所述沟道层电连接”包括：
在所述第二绝缘层上形成第二金属层；
形成覆盖所述第二金属层的第二光刻胶层；
移除正对所述栅极的第二光刻胶层，且移除的第二光刻胶层的尺寸大于或等于所述栅极的长度，第二光刻胶层形成第二光刻胶图案；
以所述第二光刻胶图案为掩膜，蚀刻未被所述第二光刻胶图案覆盖的第二金属层以形成所述源极及所述漏极；
剥离所述第二光刻胶图案。
本发明还提供了一种液晶显示面板，所述液晶显示面板包括前述任意实施方式所述的阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的剖面结构示意图。
图2为本发明一较佳实施方式的阵列基板的制备方法的流程图。
图3至图18为本发明阵列基板的制备方法中各步骤对应的结构示意图。
图19为本发明一较佳实施方式的液晶显示面板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的阵列基板的剖面结构示意图。所述阵列基板10包括基板100、沟道层110、第一绝缘层120、栅极130、第二绝缘层140、源极150a、漏极150b、平坦层160、公共电极170、钝化层180及像素电极190。所述沟道层110邻近所述基板10的表面设置。所述第一绝缘层120覆盖所述沟道层110。所述栅极130设置在所述第一绝缘层120远离所述沟道层110的表面。所述第二绝缘层140覆盖所述栅极130，且所述第二绝缘层140开设有间隔设置的第一贯孔141和第二贯孔142。所述源极150a设置在所述第二绝缘层140上，且所述源极141通过所述第一贯孔141与所述沟道层110电连接。所述漏极150b设置在所述第二绝缘层140上，且所述漏极150b通过所述第二贯孔142与所述沟道层110电连接，且所述漏极150b与所述源极141间隔设置。所述平坦层160覆盖所述源极150a及所述漏极150b，且所述平坦层160对应所述漏极150b开设第三贯孔161。所述公共电极170设置在所述平坦层160上。所述钝化层180覆盖所述公共电极170，且所述钝化层180包括HfO2，所述钝化层180对应所述漏极150b开设第四贯孔181，且所述第四贯孔181与所述第三贯孔161连通。所述像素电极190设置在所述钝化层180上，所述像素电极190通过所述第三贯孔161及所述第四贯孔181与所述漏极150b电连接，且所述像素电极190对应所述公共电极170设置。所述像素电极190、所述钝化层180及所述公共电极170构成存储电容。
在这里，所述栅极130、所述源极150a及所述漏极150b分别为薄膜晶体管中的栅极、源极及漏极。
所述基板100的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板110为绝缘层衬底能够减小所述基板110的高频损耗。
所述阵列基板10还包括缓冲层101，所述缓冲层101设置在所述基板100上。此时，所述沟道层110设置在所述缓冲层101远离所述基板100的表面。所述缓冲层101可以减小所述阵列基板10在制备的过程中对所述基板100的损伤。
所述沟道层110的材料可以为氧化半导体材料，比如，非晶铟镓锌氧化物(Amorphous Indium Gallium Zinc Oxide，a-IGZO)。
所述第一绝缘层120包括但不仅限于氮化硅(SiNx)、氧化硅(SiOx)材料等。
所述栅极130的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
所述第二绝缘层140包括但不仅限于氮化硅(SiNx)、氧化硅(SiOx)材料等。
所述源极150a及所述漏极150b的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
所述公共电极170包括透明导电材料，比如，所述公共电极170可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。
所述像素电极190包括透明导电材料，比如，所述像素电极190可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。
在本实施方式中，所述阵列基板10还包括第一接触部102和第二接触部103。所述第一接触部102和所述第二接触部103分别与所述沟道层110接触，且所述第一接触部102与所述第二接触部103间隔设置。所述源极150a通过所述第一贯孔141与所述第一接触部102相连，所述第一接触部102用于减小所述源极150a与所述沟道层110之间的接触电阻。所述漏极150b通过所述第二贯孔142与所述第二接触部103相连，所述第二接触部103用于减小所述漏极150b与所述沟道层110之间的接触电阻。所述第一接触部102和所述第二接触部103可以由氧化半导体材料进行离子处理而得到。比如，可以用a-IGZO进行H2或者Ar离子处理而形成。
所述沟道层110包括相对设置的第一端面111和第二端面112。所述第一端面111和所述第二端面112均与所述沟道层110邻近所述基板100的表面相交。所述第一绝缘层120包括相对设置的第三端面121和第四端面122。所述第三端面121和所述第四端面122均与所述第一绝缘层120覆盖所述沟道层110的表面相交。所述栅极130包括相对设置的第五端面131和第六端面132。所述第五端面131和所述第六端面132均与所述栅极130设置在所述第一绝缘层120上的表面相交。所述第一端面111、所述第二端面121及所述第五端面131共面，所述第二端面112、所述第四端面122及所述第六端面132共面。
所述第五端面131相较于所述第六端面132邻近所述源极150a设置，所述第六端面132相较于所述第五端面131邻近所述漏极150b设置。所述第五端面131与所述源极150a邻近所述栅极130的表面所在的平面之间的距离大于或者等于零。所述第六端面132与所述漏极150b邻近所述栅极130的表面所在的平面之间的距离大于或者等于零。
相较于现有技术，本发明的阵列基板10中的钝化层180中包括HfO2，所述HfO2具有较高的介电常数和较高的透光率。当所述公共电极170、所述钝化层180及所述像素电极190形成存储电容时，在所述公共电极170和所述钝化层180的正对面积不变时，且所述钝化层180厚度一定的情况下，可以提高所述存储电容的电容大小。当所述存储电容的电容大小不变，且所述钝化层180的厚度不变时，可以减小存储电容的面积，因此，可以提高所述阵列基板10所应用的显示面板的画素稳定性及所述阵列基板10的开口率。
进一步地，由于所述第五端面131相较于所述第六端面132邻近所述源极150a设置，且所述第五端面131与所述源极150a邻近所述栅极130的表面所在的平面之间的距离大于等于零。即，所述栅极130与所述源极150a之间没有重合的面积，因此，所述栅极130与所述源极150a之间不存在寄生电容。且，由于所述第六端面132相较于所述第五端面131邻近所述漏极150b设置，所述第六端面132与所述漏极150b邻近所述栅极130的表面所在的平面之间的距离大于或等于零。即，所述栅极130与所述漏极150b之间没有重合面积，因此，所述栅极130与所述漏极150b之间不存在寄生电容。
下面结合前面描述的阵列基板10，对本发明的阵列基板的制备方法进行介绍。请一并参阅图2，图2为本发明一较佳实施方式的阵列基板的制备方法的流程图。所述阵列基板10的制备方法包括但不仅限于以下步骤。
步骤S101，提供基板100,请参阅图3。
在本实施方式中，所述阵列基板的制备方法还包括步骤I。
步骤I，形成设置在所述基板10上的缓冲层101，请参阅图4。
步骤S102，邻近所述基板100的表面形成沟道层110。当所述阵列基板的制备方法中包括步骤I时，所述步骤S102具体包括：在所述缓冲层101远离所述基板10的表面形成所述沟道层110，请参阅图5。
步骤S103，形成覆盖所述沟道层110的第一绝缘层120。
步骤S104，形成设置在所述第一绝缘层120远离所述沟道层110的栅极130。
在本实施方式中，所述步骤S102、所述步骤S103及所述步骤S104可以具体包括如下步骤。
步骤S1，邻近所述基板100的表面依次形成层叠设置的氧化物半导体层210、第一绝缘材料层220及第一金属层230，请参阅图6。
步骤S2，形成覆盖所述第一金属层230的第一光刻胶层240，请参阅图7。
步骤S3，图案化所述第一光刻胶层240以保留设置在所述第一金属层230中部的第一光刻胶图案241，请参阅图8。
步骤S4，以所述第一光刻胶图案241为掩膜，蚀刻未被所述第一光刻胶图案241保护的第一金属层230及第一绝缘材料层220以分别形成栅极130及第一绝缘层120，请一并参阅图9。
步骤S5，对裸露的氧化物半导体层210进行离子处理，以形成第一接触部102及第二接触部103，未进行离子处理的氧化物半导体层210为所述沟道层110，请参阅图10。
相较于现有技术，本发明阵列基板的制备方法中采用步骤S1～步骤S5，利用第一光刻胶图案241及栅极1130和第一绝缘层120为掩膜，形成了第一接触部102、第二接触部103及所述沟道层110，没有增加光罩。
步骤S6，剥离所述第一光刻胶图案241，请参阅图11。
步骤S105，形成覆盖所述栅极130的第二绝缘层140，且在所述第二绝缘层140上开设间隔设置的第一贯孔141和第二贯孔142，请参阅图12。
步骤S106，在所述第二绝缘层140上形成间隔设置的源极150a和漏极150b，且所述源极150a通过所述第一贯孔141与所述沟道层110电连接，所述漏极150b通过所述第二贯孔142与所述沟道层110电连接。
具体地，所述步骤S106包括如下步骤。
步骤S1061，在所述第二绝缘层140上形成第二金属层250，请参阅图13。
步骤S1062，形成覆盖所述第二金属层250的第二光刻胶层260，请参阅图14。
步骤S1063，移除正对所述栅极130的第二光刻胶层260，且移除的第二光刻胶层260的尺寸大于或等于所述栅极130的长度，第二光刻胶层260形成第二光刻胶图案261，请一并参阅图15。
步骤S1064，以所述第二光刻胶图案261为掩膜，蚀刻未被所述第二光刻胶图案261覆盖的第二金属层250以形成所述源极150a及所述漏极150b，请参阅图16。
步骤S1065，剥离所述第二光刻胶图案261，请参阅图17。
步骤S107，形成覆盖所述源极150a和所述漏极150b的平坦层160，所述平坦层160对应所述漏极150b开设第三贯孔161。
步骤S108，形成设置在所述平坦层160的公共电极170。
步骤S109，形成覆盖所述公共电极170且包括HfO2的钝化层180，且在所述钝化层180上对应所述漏极150b开设第四贯孔181。
步骤S110，形成设置在所述钝化层180上，对应所述公共电极170设置，且通过所述第三贯孔161及所述第四贯孔181与所述漏极150b电连接的像素电极190，所述像素电极190、所述钝化层180及所述公共电极170构成存储电容，所述步骤S107～步骤S110请参阅图18。
请参阅图19，图19为本发明一较佳实施方式的液晶显示面板的结构示意图。所述液晶显示面板1包括阵列基板10，所述阵列基板10如前面所述，在此不再赘述。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

1.一种阵列基板，其特征在于，所述阵列基板包括：
基板；
沟道层，邻近所述基板的表面设置；
第一绝缘层，覆盖所述沟道层；
栅极，设置在所述第一绝缘层远离所述沟道层的表面；
第二绝缘层，覆盖所述栅极，且所述第二绝缘层上开设有间隔设置的第一贯孔和第二贯孔；
源极，设置在所述第二绝缘层上，且所述源极通过所述第一贯孔与所述沟道层电连接；
漏极，设置在所述第二绝缘层上，且所述漏极通过所述第二贯孔与所述沟道层电连接，且所述漏极与所述源极间隔设置；
平坦层，覆盖所述源极及所述漏极，所述平坦层对应所述漏极开设第三贯孔；
公共电极，设置在所述平坦层上；
钝化层，覆盖所述公共电极，且所述钝化层包括HfO2，所述钝化层对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
像素电极，设置在所述钝化层上，所述像素电极通过所述第三贯孔及所述第四贯孔与所述漏极电连接，且所述像素电极对应所述公共电极设置，所述像素电极、所述钝化层及所述公共电极构成存储电容。
2.如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括：
缓冲层，设置在所述基板上；
所述沟道层设置在所述缓冲层远离所述基板的表面。
3.如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括：
第一接触部和第二接触部，所述第一接触部和所述第二接触部分别与所述沟道层接触，且所述第一接触部与所述第二接触部间隔设置；
所述源极通过所述第一贯孔与所述第一接触部相连，所述第一接触部用于减小所述源极与所述沟道层之间的接触电阻；
所述漏极通过所述第二贯孔与所述第二接触部相连，所述第二接触部用于减小所述漏极与所述沟道层之间的接触电阻。
4.如权利要求3所述的阵列基板，其特征在于，所述沟道层包括相对设置的第一端面和第二端面，所述第一端面和所述第二端面均与所述沟道层邻近所述基板设置的表面相交，所述第一绝缘层包括相对设置的第三端面和第四端面，所述第三端面和所述第四端面均与所述第一绝缘层覆盖所述沟道层的表面相交，所述栅极包括相对设置的第五端面和第六端面，所述第五端面和所述第六端面均与所述栅极设置在所述第一绝缘层上的表面相交，
且所述第一端面、所述第三端面及所述第五端面共面，所述第二端面、所述第四端面及所述第六端面共面。
5.如权利要求4所述的阵列基板，其特征在于，所述第五端面相较于所述第六端面邻近所述源极设置，所述第六端面相较于所述第五端面邻近所述漏极设置，所述第五端面与所述源极邻近所述栅极的表面所在的平面之间的距离大于或者等于零；所述第六端面与所述漏极邻近所述栅极的表面所在的平面之间的距离大于或者等于零。
6.一种阵列基板的制备方法，其特征在于，所述阵列基板的制备方法包括：
提供基板；
邻近所述基板的表面形成沟道层；
形成覆盖所述沟道层的第一绝缘层；
形成设置在所述第一绝缘层远离所述沟道层的栅极；
形成覆盖所述栅极的第二绝缘层，且在所述第二绝缘层上开设间隔设置的第一贯孔和第二贯孔；
在所述第二绝缘层上形成间隔设置的源极和漏极，且所述源极通过所述第一贯孔与所述沟道层电连接，所述漏极通过所述第二贯孔与所述沟道层电连接；
形成覆盖所述源极和所述漏极的平坦层，所述平坦层对应所述漏极开设第三贯孔；
形成设置在所述平坦层的公共电极；
形成覆盖所述公共电极且包括HfO2的钝化层，且在所述钝化层上对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
形成设置在所述钝化层上，对应所述公共电极设置，且通过所述第三贯孔及所述第四贯孔与所述漏极电连接的像素电极，所述像素电极、所述钝化层及所述公共电极构成存储电容。
7.如权利要求6所述的阵列基板的制备方法，其特征在于，所述阵列基板的制备方法还包括：
形成设置在所述基板上的缓冲层；
所述步骤“邻近所述基板的表面形成沟道层”包括：
在所述缓冲层远离所述基板的表面形成所述沟道层。
8.如权利要求6所述的阵列基板的制备方法，其特征在于，所述步骤“邻近所述基板的表面形成沟道层”，“形成覆盖所述沟道层的第一绝缘层；”及“形成设置在所述第一绝缘层远离所述沟道层的栅极”包括：
邻近所述基板的表面依次形成层叠设置的氧化物半导体层、第一绝缘材料层及第一金属层；
形成覆盖所述第一金属层的第一光刻胶层；
图案化所述第一光刻胶层以保留设置在所述第一金属层中部的第一光刻胶图案；
以所述第一光刻胶图案为掩膜，蚀刻未被所述第一光刻胶图案保护的第一金属层及第一绝缘材料层以分别形成栅极及第一绝缘层；
对裸露的氧化物半导体层进行离子处理，以形成第一接触部及第二接触部，未进行离子处理的氧化物半导体层为所述沟道层；
剥离所述第一光刻胶图案。
9.如权利要求6所述的阵列基板的制备方法，其特征在于，所述步骤“在所述第二绝缘层上形成间隔设置的源极和漏极，且所述源极通过所述第一贯孔与所述沟道层电连接，所述漏极通过所述第二贯孔与所述沟道层电连接”包括：
在所述第二绝缘层上形成第二金属层；
形成覆盖所述第二金属层的第二光刻胶层；
移除正对所述栅极的第二光刻胶层，且移除的第二光刻胶层的尺寸大于或等于所述栅极的长度，第二光刻胶层形成第二光刻胶图案；
以所述第二光刻胶图案为掩膜，蚀刻未被所述第二光刻胶图案覆盖的第二金属层以形成所述源极及所述漏极；
剥离所述第二光刻胶图案。
10.一种液晶显示面板，其特征在于，所述液晶显示面板包括如权利要求1～5任意一项所述的阵列基板。
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