WO2019080223A1 - Oled面板及其制作方法 - Google Patents
Oled面板及其制作方法Info
- Publication number
- WO2019080223A1 WO2019080223A1 PCT/CN2017/111970 CN2017111970W WO2019080223A1 WO 2019080223 A1 WO2019080223 A1 WO 2019080223A1 CN 2017111970 W CN2017111970 W CN 2017111970W WO 2019080223 A1 WO2019080223 A1 WO 2019080223A1
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- WIPO (PCT)
- Prior art keywords
- layer
- deposited
- metal
- oled panel
- semiconductor
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 304
- 229910052751 metal Inorganic materials 0.000 claims abstract description 72
- 239000002184 metal Substances 0.000 claims abstract description 72
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 238000003860 storage Methods 0.000 claims abstract description 41
- 238000002161 passivation Methods 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 239000011521 glass Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 28
- 238000000151 deposition Methods 0.000 claims description 22
- 238000000059 patterning Methods 0.000 claims description 17
- 239000010408 film Substances 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 12
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910004205 SiNX Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000007641 inkjet printing Methods 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
- H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/84—Passivation; Containers; Encapsulations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
Definitions
- the present invention relates to the field of display technologies, and in particular, to an OLED panel and a method of fabricating the same.
- the organic light emitting diode (OLED) display device has self-luminous, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180° viewing angle, wide temperature range, and flexible display and large-area full-color display. And many other advantages, recognized by the industry as the most promising display device.
- the OLED display device can be classified into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED) according to the driving method.
- PMOLED passive matrix OLED
- AMOLED active matrix OLED
- the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
- a pixel driving circuit of an existing OLED panel generally includes a switching thin film transistor (Switch TFT), a driving thin film transistor (Driver TFT), and a storage capacitor (Cst); the switching TFT is controlled by a scanning signal for controlling entry of a data signal, driving the TFT For controlling the current through the OLED, the storage capacitor is generally used to store the gray scale voltage to determine the drive current of the driving TFT.
- Switch TFT switching thin film transistor
- Driver TFT driving thin film transistor
- Cst storage capacitor
- the switching TFT is controlled by a scanning signal for controlling entry of a data signal, driving the TFT
- the storage capacitor is generally used to store the gray scale voltage to determine the drive current of the driving TFT.
- FIG. 1 it is a schematic structural diagram of an existing OLED panel, and can be divided into a switching TFT region, a driving TFT region, and a storage capacitor region according to a functional region.
- the existing OLED panel mainly comprises: a glass substrate 10; a light shielding layer (LS) 11 deposited on the glass substrate 10; a buffer layer 12 deposited on the light shielding layer 11; and a semiconductor layer 13 deposited on the buffer layer 12,
- the semiconductor layer 13 may be an amorphous oxide semiconductor (AOS), and a region where the semiconductor layer 13 is in contact with the TFT electrode may increase a doping concentration, for example, an N+ conductor layer may be formed; and a gate insulating layer deposited on the semiconductor layer 13 ( GI) 14; a first metal layer (ie, a gate metal layer) 15 deposited on the gate insulating layer 14 for forming a gate electrode (G) of the TFT; an interlayer insulating layer deposited on the first metal layer 15 (ILD) 16; a
- the storage capacitor is composed of an indium tin oxide (ITO)-second metal layer (Metal2)-amorphous oxide semiconductor (AOS) structure, but between Metal2 and ITO.
- the interlayer is a layer of passivation layer (PV) and flat layer (PLN) (see Figure 1), and the thickness of both layers is large.
- PV passivation layer
- PPN flat layer
- an object of the present invention to provide an OLED panel that increases the storage capacitance of an OLED panel.
- Another object of the present invention is to provide a method for fabricating an OLED panel, which improves the storage capacitance of the OLED panel.
- the present invention provides an OLED panel comprising: a glass substrate; a TFT light shielding layer formed on the glass substrate; a buffer layer deposited on the TFT light shielding layer; and a semiconductor layer deposited on the buffer layer Forming, by the patterning process, a TFT active layer; depositing a patterned gate insulating layer and a first metal layer on the semiconductor layer, and the semiconductor layer outside the first metal layer covering region is subjected to a conductor An interlayer insulating layer deposited on the first metal layer, wherein the interlayer insulating layer is provided with a source/drain contact region opening; and a second patterned pattern is deposited on the interlayer insulating layer a metal layer; a passivation layer deposited on the second metal layer by atomic layer deposition, the passivation layer being a thin film of high dielectric constant material and provided with via holes; color filter fabricated on the passivation layer a sheet, a flat layer, an anode, and a pixel defining layer,
- the passivation layer has a thickness of less than 500 angstroms.
- the high dielectric constant material is Al 2 O 3 .
- the invention also provides a method for manufacturing an OLED panel, comprising:
- Step 1 providing a glass substrate, depositing a layer of metal on the glass substrate and patterning the layer of metal as a TFT light shielding layer;
- Step 2 sequentially depositing a buffer layer and a semiconductor layer, and patterning the semiconductor layer as a TFT active layer;
- Step 3 sequentially depositing a gate insulating layer and a first metal layer, patterning the gate insulating layer and the first metal layer, and performing a conductor treatment on the semiconductor layer outside the first metal layer covering region;
- Step 4 depositing an interlayer insulating layer, and making a source/drain contact region opening on the interlayer insulating layer;
- Step 5 depositing a second metal layer, and patterning the second metal layer
- Step 6 depositing a film of a high dielectric constant material as a passivation layer by atomic layer deposition, and etching a via hole;
- Step 7 sequentially fabricating a color filter, a flat layer, an anode, and a pixel defining layer, wherein the flat layer is provided with a via hole corresponding to the passivation layer, and is an open structure in the storage capacitor region;
- Step 8 Prepare a light-emitting layer and a cathode.
- the passivation layer has a thickness of less than 500 angstroms.
- the high dielectric constant material is Al 2 O 3 .
- the material of the TFT light shielding layer is Mo, Al, Cu, Ti or an alloy.
- the buffer layer is an SiOx film, a SiNx film or a laminated structure film.
- the material of the semiconductor layer is an amorphous oxide semiconductor.
- the material of the semiconductor layer is IGZO, IZTO or IGZTO.
- the present invention also provides an OLED panel comprising: a glass substrate; a TFT light shielding layer formed on the glass substrate; a buffer layer deposited on the TFT light shielding layer; a semiconductor layer deposited on the buffer layer, the semiconductor layer undergoing Forming a TFT active layer; depositing a patterned gate insulating layer and a first metal layer on the semiconductor layer, and the semiconductor layer outside the first metal layer coverage region undergoes a conductor treatment; An interlayer insulating layer on the first metal layer, on the interlayer insulating layer, a source/drain contact region opening; a second metal layer subjected to patterning on the interlayer insulating layer; a passivation layer deposited on the second metal layer by a layer deposition method, the passivation layer being a thin film of a high dielectric constant material and provided with via holes; a color filter, a flat layer, and a flat layer formed on the passivation layer An anode and a pixel defining layer, wherein the flat layer is provided with an
- the passivation layer has a thickness of less than 500 angstroms
- the high dielectric constant material is Al 2 O 3 .
- the OLED panel of the present invention and the manufacturing method thereof can effectively improve the storage capacitance of the OLED panel, and can reduce the design area of the storage capacitor, thereby facilitating the improvement of the panel aperture ratio.
- FIG. 1 is a schematic structural view of a conventional OLED panel
- FIG. 2 is a schematic structural view of a preferred embodiment of an OLED panel of the present invention.
- 3A-3H are schematic flow charts of a preferred embodiment of a method for fabricating an OLED panel of the present invention.
- the OLED panel of the present invention mainly comprises: a glass substrate 20; a TFT light shielding layer 21 formed on the glass substrate 20; a buffer layer 22 deposited on the TFT light shielding layer 21; a semiconductor layer 23 deposited on the buffer layer 22, and a semiconductor layer 23 Patterned as a TFT active layer; a gate insulating layer 24 deposited on the semiconductor layer 23 and a first metal layer 25, the gate insulating layer 24 and the first metal layer 25 are patterned to form a gate of the TFT And conducting the semiconductor layer 23 outside the coverage area of the first metal layer 25, for example, increasing the doping concentration in a region where the semiconductor layer 23 is in contact with the TFT electrode, and forming an N+ conductor layer; depositing on the first metal layer 25
- the upper interlayer insulating layer 26 is provided with a source/d
- the thickness of the passivation layer 28 can be designed to be less than 500 angstroms (
- the high dielectric constant (high k value) material used may be Al 2 O 3 .
- the present invention starts in two aspects of design and process selection.
- the PV layer adopts a material with high k value of Al 2 O 3 , and adopts a good coverage method to greatly reduce PV.
- the thickness increases the storage capacitance.
- the original PLN design is changed to the way of the PLN opening at the storage capacitor to reduce the influence of PLN.
- the invention can effectively increase the storage capacitance, thereby reducing the storage capacitor design area, and has great benefits for increasing the aperture ratio.
- 3A to 3H are schematic flowcharts of a preferred embodiment of a method for fabricating an OLED panel of the present invention.
- the manufacturing method of the OLED panel of the present invention mainly includes the following steps: through the PV material and the process improvement and the change of the PLN design.
- Step 1 Providing a glass substrate, depositing a layer of metal on the glass substrate and patterning the layer of metal As a TFT light shielding layer.
- the glass substrate 20 is cleaned and a layer of metal having a thickness of 500-2000 angstroms is deposited, and the layer of metal can be patterned as a TFT light-shielding layer 21 by a yellow light process and etching, which may be Mo, Al, Cu, Ti, etc., or an alloy.
- Step 2 sequentially depositing a buffer layer and a semiconductor layer, and patterning the semiconductor layer as a TFT active layer.
- a film is deposited as the buffer layer 22, which may be a SiOx, SiNx single layer film or a stacked structure, and may have a thickness of 1000 to 5000 angstroms.
- a metal oxide (Oxide) semiconductor material is deposited as the semiconductor layer 23, and the semiconductor layer 23 can be made of an amorphous oxide semiconductor (AOS) material, which can be IGZO, IZTO, IGZTO, etc., and can have a thickness of 100 to 1000.
- AOS amorphous oxide semiconductor
- An erg, and the patterned semiconductor layer 23 is made to be an active layer.
- Step 3 sequentially depositing a gate insulating layer and a first metal layer, patterning the gate insulating layer and the first metal layer, and conducting a conductor treatment on the semiconductor layer outside the first metal layer covering region.
- a gate insulating layer 24 is deposited, which may be a SiOx, SiNx film or a laminated structure film having a thickness of 1000 to 3000 angstroms; and a metal layer is deposited as the first metal layer 25, that is, the gate metal layer.
- Step 4 Deposit an interlayer insulating layer, and make a source/drain contact region opening on the interlayer insulating layer.
- an interlayer insulating layer 26 may be deposited, which may be a SiOx, SiNx film or a stacked structure, having a thickness of 3000 to 10000 angstroms, and a source/drain (S/D) contact region is opened by a yellow light process. hole.
- Step 5 Deposit a second metal layer and pattern the second metal layer.
- a layer of metal is deposited as the second metal layer 27, that is, the source and drain metal layers, which may be Mo, Al, Cu, Cu, or an alloy having a thickness of 2000 to 8000 angstroms, and then passed through a yellow light process and etching.
- a pattern is defined, a portion serving as a source (S) and a drain (D) of the TFT, and a portion serving as a storage capacitor (corresponding to a storage capacitor region).
- Step 6 depositing a thin film of high dielectric constant material as a passivation layer by atomic layer deposition. And the via holes are etched.
- a passivation layer 28 is deposited, which is deposited by ALD.
- the material may be a high-k material such as Al 2 O 3 , the thickness is designed to be thin, can be designed to be less than 500 angstroms, and is etched by a yellow process. Out of the hole.
- Step 7 The color filter, the flat layer, the anode, and the pixel defining layer are sequentially formed.
- the flat layer is provided with a via hole corresponding to the passivation layer, and has an open structure in the storage capacitor region.
- a color filter 29 is formed; a flat layer 30 is formed, which may be a photoresist layer of different composition, having a thickness of 10000-20000 A, a via hole is formed by a yellow light process, and an opening structure is formed in the storage capacitor region.
- the deposition anode 31 may be a transparent oxide such as ITO and has a thickness of 500 to 1000 angstroms; the pixel defining layer 32 may be formed as a photoresist layer having different compositions, and the thickness is 10,000 to 20,000 angstroms, and the illuminating region is defined by a yellow light process. Finish the backboard production.
- Step 8 Prepare a light-emitting layer and a cathode.
- the luminescent layer 33 is formed by an evaporation or inkjet printing (IJP) technique, and the cathode 34 is fabricated to complete the fabrication of the OLED panel.
- IJP evaporation or inkjet printing
- the PV adopts a high-k material such as Al 2 O 3 , and deposition by ALD technology can greatly reduce the thickness of the PV and increase the storage capacitance; the PLN layer is designed to use the storage capacitor region to open the hole. The way to reduce the distance between the two electrodes and increase the storage capacitance.
- the OLED panel of the present invention and the manufacturing method thereof can effectively improve the storage capacitance of the OLED panel, and can reduce the design area of the storage capacitor, thereby facilitating the improvement of the panel aperture ratio.
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Abstract
一种OLED面板及其制作方法,OLED面板包括:玻璃基板(20);TFT遮光层(21);缓冲层(22);半导体层(23);沉积在半导体层(23)上经图形化处理的栅极绝缘层(24)和第一金属层(25);沉积于第一金属层(25)上的层间绝缘层(26);沉积于层间绝缘层(26)上的经历图形化处理的第二金属层(27);以原子层沉积方式沉积于第二金属层(27)上的钝化层(28),钝化层(28)为高介电常数材料的薄膜并且设有过孔;制作于钝化层(28)上的彩色滤光片(29)、平坦层(30)、阳极(31)以及像素限定层(32),平坦层(30)对应于储存电容区域设有开孔结构;制作于阳极(31)上的发光层(33);制作于发光层(33)上的阴极(34),该OLED面板及其制作方法能够有效提高OLED面板的储存电容,可以减小储存电容设计面积,从而有利于提高面板开口率。
Description
本发明涉及显示技术领域,尤其涉及一种OLED面板及其制作方法。
有机发光二极管(OLED)显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽,可实现柔性显示与大面积全色显示等诸多优点,被业界公认为是最有发展潜力的显示装置。OLED显示装置按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED,PMOLED)和有源矩阵型OLED(Active Matrix OLED,AMOLED)两大类。其中,AMOLED具有呈阵列式排布的像素,属于主动显示类型,发光效能高,通常用作高清晰度的大尺寸显示装置。
现有OLED面板的像素驱动电路一般包括开关薄膜晶体管(Switch TFT),驱动薄膜晶体管(Driver TFT),以及存储电容(Cst);开关TFT由扫描信号控制,用于控制数据信号的进入,驱动TFT用于控制通过OLED的电流,存储电容一般用于存储灰阶电压以决定驱动TFT的驱动电流。
如图1所示,其为现有OLED面板结构示意图,按照功能区域可划分为开关TFT区域,驱动TFT区域,以及存储电容区域。现有OLED面板主要包括:玻璃基板10;沉积于玻璃基板10上的遮光层(LS)11;沉积在遮光层11上的缓冲层(Buffer)12;沉积在缓冲层12上的半导体层13,该半导体层13可以为非晶氧化物半导体(AOS),半导体层13与TFT电极相接触的区域可以提高掺杂浓度,例如可以形成N+导体层;沉积在半导体层13上的栅极绝缘层(GI)14;沉积在栅极绝缘层14上的第一金属层(即栅极金属层)15,用于形成TFT的栅极(G);沉积于第一金属层15上的层间绝缘层(ILD)16;沉积于层间绝缘层16上的第二金属层(即源漏极金属层)17,第二金属层17经图案化一部分形成TFT的源极(S)和漏极(D),一部分形成存储电容(对应于存储电容区域);沉积于第二金属层17上的钝化层(PV)18,现有技术中钝化层18一般由SiOx制成;制作于钝化层18上的彩色滤光片(CF-RGB)19;制作于彩色滤光片上的平坦层(PLN)40;沉积于平坦层40上的阳极(Anode)41,可以是氧化铟锡(ITO)等透明氧化物;制作于阳极41上的像素限定层(PDL)42,用以界定OLED器件的发光区;利用蒸镀或喷墨打印(IJP)技术制作于阳极41上的发光层
43;制作于发光层43上的阴极44;其它如封装结构等在此不再赘述。
目前顶栅极(Top gate)氧化物TFT设计中,储存电容采用氧化铟锡(ITO)-第二金属层(Metal2)-非晶氧化物半导体(AOS)结构构成,但由于Metal2与ITO之间夹层为钝化层(PV)和平坦层(PLN)两层(可参见图1),而且两层厚度都较大,同样面积时储存电容容量较小,为了达到提高存储电容的需求只能增大储存电容面积,这样就会严重影响开口率。
发明内容
因此,本发明的目的在于提供一种OLED面板,提高OLED面板的储存电容。
本发明的另一目的在于提供一种OLED面板的制作方法,提高OLED面板的储存电容。
为实现上述目的,本发明提供了一种OLED面板,包括:玻璃基板;制作于该玻璃基板上的TFT遮光层;沉积在该TFT遮光层上的缓冲层;沉积在该缓冲层上的半导体层,该半导体层经历图形化处理形成TFT有源层;沉积在该半导体层上经图形化处理的栅极绝缘层和第一金属层,并且该第一金属层覆盖区域以外的该半导体层经历导体化处理;沉积于该第一金属层上的层间绝缘层,在该层间绝缘层上设有源漏极接触区开孔;沉积于该层间绝缘层上的经历图形化处理的第二金属层;以原子层沉积方式沉积于该第二金属层上的钝化层,该钝化层为高介电常数材料的薄膜并且设有过孔;制作于该钝化层上的彩色滤光片、平坦层、阳极以及像素限定层,该平坦层对应于储存电容区域设有开孔结构;制作于该阳极上的发光层;制作于该发光层上的阴极。
其中,所述钝化层厚度小于500埃。
其中,所述高介电常数材料为Al2O3。
本发明还提供了一种OLED面板的制作方法,包括:
步骤1、提供玻璃基板,在玻璃基板上沉积一层金属并图形化该层金属作为TFT遮光层;
步骤2、依次沉积缓冲层以及半导体层,图形化该半导体层作为TFT有源层;
步骤3、依次沉积栅极绝缘层和第一金属层,图形化该栅极绝缘层和第一金属层,并且对第一金属层覆盖区域以外的半导体层进行导体化处理;
步骤4、沉积层间绝缘层,并且在该层间绝缘层上做出源漏极接触区开孔;
步骤5、沉积第二金属层,并且图形化该第二金属层;
步骤6、以原子层沉积方式沉积一层高介电常数材料的薄膜作为钝化层,并且蚀刻出过孔;
步骤7、依次完成彩色滤光片、平坦层、阳极及像素限定层的制作,该平坦层对应于钝化层设有过孔,并且在储存电容区域为开孔结构;
步骤8、制作发光层及阴极。
其中,所述钝化层厚度小于500埃。
其中,所述高介电常数材料为Al2O3。
其中,所述TFT遮光层的材料为Mo,Al,Cu,Ti或者合金。
其中,所述缓冲层为SiOx薄膜、SiNx薄膜或叠层结构薄膜。
其中,所述半导体层的材料为非晶氧化物半导体。
其中,所述半导体层的材料为IGZO,IZTO或IGZTO。
本发明还提供一种OLED面板,包括:玻璃基板;制作于该玻璃基板上的TFT遮光层;沉积在该TFT遮光层上的缓冲层;沉积在该缓冲层上的半导体层,该半导体层经历图形化处理形成TFT有源层;沉积在该半导体层上经图形化处理的栅极绝缘层和第一金属层,并且该第一金属层覆盖区域以外的该半导体层经历导体化处理;沉积于该第一金属层上的层间绝缘层,在该层间绝缘层上设有源漏极接触区开孔;沉积于该层间绝缘层上的经历图形化处理的第二金属层;以原子层沉积方式沉积于该第二金属层上的钝化层,该钝化层为高介电常数材料的薄膜并且设有过孔;制作于该钝化层上的彩色滤光片、平坦层、阳极以及像素限定层,该平坦层对应于储存电容区域设有开孔结构;制作于该阳极上的发光层;制作于该发光层上的阴极;
其中,所述钝化层厚度小于500埃;
其中,所述高介电常数材料为Al2O3。
综上,本发明的OLED面板及其制作方法能够有效提高OLED面板的储存电容,可以减小储存电容设计面积,从而有利于提高面板开口率。
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其他有益效果显而易见。
附图中,
图1现有OLED面板结构示意图;
图2为本发明OLED面板一较佳实施例的结构示意图;
图3A至图3H为本发明OLED面板的制作方法一较佳实施例的流程示意图。
参见图2,其为本发明OLED面板一较佳实施例的结构示意图,按照功能区域可划分为开关TFT区域,驱动TFT区域,以及存储电容区域。本发明的OLED面板主要包括:玻璃基板20;制作于玻璃基板20上的TFT遮光层21;沉积在TFT遮光层21上的缓冲层22;沉积在缓冲层22上的半导体层23,半导体层23经图形化作为TFT有源层;沉积在半导体层23上的栅极绝缘层24和第一金属层25,该栅极绝缘层24和第一金属层25经图形化处理,形成TFT的栅极,并且对第一金属层25覆盖区域以外的半导体层23进行导体化处理,例如使半导体层23与TFT电极相接触的区域提高掺杂浓度,可以形成N+导体层;沉积于第一金属层25上的层间绝缘层26,在该层间绝缘层26上设有源漏极接触区开孔;沉积于层间绝缘层26上的第二金属层27,该第二金属层27经图形化处理,一部分形成TFT的源极(S)和漏极(D),一部分形成存储电容(对应于存储电容区域);以原子层沉积(ALD)方式沉积于第二金属层27上的钝化层28,该钝化层28为高介电常数材料的薄膜并且设有过孔;制作于钝化层28上的彩色滤光片29、平坦层30、阳极31以及像素限定层32,该平坦层30对应于钝化层28的过孔设有过孔,并且在储存电容区域为开孔结构;制作于阳极31上的发光层33;制作于发光层33上的阴极34;其它如通常的封装结构等在此不再赘述。
为了解决现有技术所存在的问题,本发明在设计和制程选择两方面入手,一方面PV层采用高k值的Al2O3等材料,采用覆盖性好的沉积方式,大幅减小PV的厚度,进而提高储存电容,另一方面将原有PLN设计,改为储存电容处PLN开孔的方式,减少PLN的影响。本发明可以有效提高储存电容,进而减小储存电容设计面积,对提高开口率有很大益处。
参见图3A至图3H,其为本发明OLED面板的制作方法一较佳实施例的流程示意图。通过PV材料及制程改进及改变PLN设计,本发明的OLED面板的制作方法主要包括如下步骤:
步骤1、提供玻璃基板,在玻璃基板上沉积一层金属并图形化该层金属
作为TFT遮光层。
参见图3A,清洗玻璃基板20,并沉积一层500-2000埃厚度的金属,并且可以利用一道黄光制程和蚀刻图形化该层金属作为TFT遮光层21,该层金属可以是Mo,Al,Cu,Ti等,或者是合金。
步骤2、依次沉积缓冲层以及半导体层,图形化该半导体层作为TFT有源层。
参见图3B,沉积一层薄膜,作为缓冲层22,可以是SiOx、SiNx单层薄膜或叠层结构,厚度可以为1000~5000埃。沉积一层金属氧化物(Oxide)半导体材料作为半导体层23,半导体层23可以由非晶氧化物半导体(AOS)材料制成,可以是IGZO,IZTO,IGZTO等等材料,厚度可以为100~1000埃,并图形化半导体层23做出有源层。
步骤3、依次沉积栅极绝缘层和第一金属层,图形化该栅极绝缘层和第一金属层,并且对第一金属层覆盖区域以外的半导体层进行导体化处理。
参见图3C,沉积一层栅极绝缘层24,可以是SiOx、SiNx薄膜或叠层结构薄膜,厚度1000~3000埃;再沉积一层金属作为第一金属层25也就是栅极金属层,可以是Mo、Al、Cu,Cu,或者是合金,厚度为2000~8000埃;利用一道黄光制程,先蚀刻第一金属层25以蚀刻出栅极金属的图形,再利用栅极金属图形为自对准,蚀刻栅极绝缘层24,只在有栅极金属图形的膜层下方,才有栅极绝缘层24存在,其余地方栅极绝缘层24均被蚀刻掉;进行整面的等离子体(Plasma)处理,使上方没有栅极绝缘层24和栅极金属保护的氧化物(Oxide)电阻明显降低,形成N+导体层,以作为源/漏极(S/D)接触区域;栅极绝缘层24下方的氧化物没有被处理到,保持半导体特性,作为TFT沟道。
步骤4、沉积层间绝缘层,并且在该层间绝缘层上做出源漏极接触区开孔。
参见图3D,沉积层间绝缘层26,可以是SiOx、SiNx薄膜或叠层结构农民,厚度在3000~10000埃,并且利用一道黄光制程做出源/漏极(S/D)接触区域开孔。
步骤5、沉积第二金属层,并且图形化该第二金属层。
参见图3E,沉积一层金属作为第二金属层27,即源漏极金属层,可以是Mo、Al、Cu,Cu,或者是合金,厚度2000~8000埃,然后通过一道黄光制程和蚀刻定义出图形,一部分作为TFT的源极(S)和漏极(D),一部分作为存储电容(对应于存储电容区域)。
步骤6、以原子层沉积方式沉积一层高介电常数材料的薄膜作为钝化层,
并且蚀刻出过孔。
参见图3F,沉积钝化层28,该层采用ALD进行沉积,材料可以是Al2O3等高k值的材料,厚度设计为很薄,可以设计为小于500埃,并通过黄光制程蚀刻出过孔。
步骤7、依次完成彩色滤光片、平坦层、阳极及像素限定层的制作,该平坦层对应于钝化层设有过孔,并且在储存电容区域为开孔结构。
参见图3G,制作彩色滤光片29;制作平坦层30,可以是不同成分的光阻层,厚度在10000-20000A,通过黄光制程做出过孔,并在储存电容区域设有开孔结构;沉积阳极31,可以是ITO等透明氧化物,厚度为500~1000埃;制作像素限定层32,可以为不同成分的光阻层,厚度在10000~20000埃,通过黄光制程定义发光区,完成背板制作。
步骤8、制作发光层及阴极。
参见图3H,利用蒸镀或喷墨打印(IJP)技术制作发光层33,再制作阴极34,即完成OLED面板的制作。
本发明的OLED面板的制作方法中PV采用高k值的Al2O3等材料,用ALD技术进行沉积,可以大幅降低PV的厚度,增大储存电容;PLN层设计时采用储存电容区开孔的方式,减小两电极之间的距离,提高储存电容。
综上,本发明的OLED面板及其制作方法能够有效提高OLED面板的储存电容,可以减小储存电容设计面积,从而有利于提高面板开口率。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (11)
- 一种OLED面板,包括:玻璃基板;制作于该玻璃基板上的TFT遮光层;沉积在该TFT遮光层上的缓冲层;沉积在该缓冲层上的半导体层,该半导体层经历图形化处理形成TFT有源层;沉积在该半导体层上经图形化处理的栅极绝缘层和第一金属层,并且该第一金属层覆盖区域以外的该半导体层经历导体化处理;沉积于该第一金属层上的层间绝缘层,在该层间绝缘层上设有源漏极接触区开孔;沉积于该层间绝缘层上的经历图形化处理的第二金属层;以原子层沉积方式沉积于该第二金属层上的钝化层,该钝化层为高介电常数材料的薄膜并且设有过孔;制作于该钝化层上的彩色滤光片、平坦层、阳极以及像素限定层,该平坦层对应于储存电容区域设有开孔结构;制作于该阳极上的发光层;制作于该发光层上的阴极。
- 如权利要求1所述的OLED面板,其中,所述钝化层厚度小于500埃。
- 如权利要求1所述的OLED面板,其中,所述高介电常数材料为Al2O3。
- 一种OLED面板的制作方法,包括:步骤1、提供玻璃基板,在玻璃基板上沉积一层金属并图形化该层金属作为TFT遮光层;步骤2、依次沉积缓冲层以及半导体层,图形化该半导体层作为TFT有源层;步骤3、依次沉积栅极绝缘层和第一金属层,图形化该栅极绝缘层和第一金属层,并且对第一金属层覆盖区域以外的半导体层进行导体化处理;步骤4、沉积层间绝缘层,并且在该层间绝缘层上做出源漏极接触区开孔;步骤5、沉积第二金属层,并且图形化该第二金属层;步骤6、以原子层沉积方式沉积一层高介电常数材料的薄膜作为钝化层,并且蚀刻出过孔;步骤7、依次完成彩色滤光片、平坦层、阳极及像素限定层的制作,该平坦层对应于钝化层设有过孔,并且在储存电容区域为开孔结构;步骤8、制作发光层及阴极。
- 如权利要求4所述的OLED面板的制作方法,其中,所述钝化层厚度小于500埃。
- 如权利要求4所述的OLED面板的制作方法,其中,所述高介电常数材料为Al2O3。
- 如权利要求4所述的OLED面板的制作方法,其中,所述TFT遮光层的材料为Mo,Al,Cu,Ti或者合金。
- 如权利要求4所述的OLED面板的制作方法,其中,所述缓冲层为SiOx薄膜、SiNx薄膜或叠层结构薄膜。
- 如权利要求4所述的OLED面板的制作方法,其中,所述半导体层的材料为非晶氧化物半导体。
- 如权利要求9所述的OLED面板的制作方法,其中,所述半导体层的材料为IGZO,IZTO或IGZTO。
- 一种OLED面板,包括:玻璃基板;制作于该玻璃基板上的TFT遮光层;沉积在该TFT遮光层上的缓冲层;沉积在该缓冲层上的半导体层,该半导体层经历图形化处理形成TFT有源层;沉积在该半导体层上经图形化处理的栅极绝缘层和第一金属层,并且该第一金属层覆盖区域以外的该半导体层经历导体化处理;沉积于该第一金属层上的层间绝缘层,在该层间绝缘层上设有源漏极接触区开孔;沉积于该层间绝缘层上的经历图形化处理的第二金属层;以原子层沉积方式沉积于该第二金属层上的钝化层,该钝化层为高介电常数材料的薄膜并且设有过孔;制作于该钝化层上的彩色滤光片、平坦层、阳极以及像素限定层,该平坦层对应于储存电容区域设有开孔结构;制作于该阳极上的发光层;制作于该发光层上的阴极;其中,所述钝化层厚度小于500埃;其中,所述高介电常数材料为Al2O3。
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