WO2015196633A1 - 一种阵列基板的制造方法、阵列基板及显示装置 - Google Patents

一种阵列基板的制造方法、阵列基板及显示装置 Download PDF

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WO2015196633A1
WO2015196633A1 PCT/CN2014/088530 CN2014088530W WO2015196633A1 WO 2015196633 A1 WO2015196633 A1 WO 2015196633A1 CN 2014088530 W CN2014088530 W CN 2014088530W WO 2015196633 A1 WO2015196633 A1 WO 2015196633A1
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region
photoresist
source
drain
gate
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PCT/CN2014/088530
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English (en)
French (fr)
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龙春平
梁逸南
刘政
田雪雁
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京东方科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, and a display device.
  • organic light emitting diode displays Compared with liquid crystal displays (LCDs), organic light emitting diode displays (OLEDs) have the advantages of fast response speed, light weight, flexibility, and wide viewing angle.
  • Active matrix organic light-emitting diodes AMOLEDs
  • the active matrix OLED architecture can be driven using amorphous silicon, polysilicon, oxide semiconductor or organic thin film transistors, wherein low temperature polysilicon has a mobility of up to 100 cm 2 /Vs, and its high current characteristics meet the stringent requirements of organic light emitting diodes.
  • the low operating voltage and high-density driving architecture make the organic light-emitting diodes have a long life. Therefore, most of the currently successfully commercialized AMOLEDs use array substrates of low-temperature polysilicon.
  • a buffer layer 2 of a silicon oxide (SiO 2 ) and silicon nitride (SiN) film is formed on the entire base substrate 1 by plasma enhanced chemical vapor deposition (PECVD). Thereafter, an amorphous silicon film (a-Si) is formed on the buffer layer 2 by PECVD or other chemical (or physical) vapor deposition method.
  • the amorphous silicon film is made into a polysilicon film by laser annealing (ELA) or solid phase crystallization (SPC).
  • ELA laser annealing
  • SPC solid phase crystallization
  • the polysilicon active layer 4 and the polysilicon storage capacitor 3 are formed using a conventional patterning process. And a low concentration ion doping is performed by an ion implantation process to form a semiconductor channel required for the thin film transistor in the polysilicon active layer 4.
  • a photoresist 5 composed of a photoresist material is formed on the polysilicon active layer 4 by a patterning process to protect the polysilicon active layer 4 from ion implantation.
  • An ion implantation process is performed to form a low-resistance doped polysilicon film on the polysilicon storage capacitor 3.
  • a gate insulating layer 6 is formed on the polysilicon active layer 4, the polysilicon storage capacitor 3, and the buffer layer 2 by depositing SiO 2 or SiO 2 and SiN thin films by PECVD.
  • a gate metal film is deposited on the gate insulating layer 6 by a physical vapor deposition method such as magnetron sputtering, and the gate electrode 7 is formed by a patterning process.
  • the polysilicon active layer 4 is ion doped using the gate electrode 7 as an ion implantation blocking layer to form a low impedance source/drain contact region.
  • an interlayer insulating layer 8 is formed by depositing SiO 2 and SiN thin films by PECVD, and source and drain contact holes are formed on the interlayer insulating layer 8 by a patterning process.
  • a source-drain metal film is deposited by magnetron sputtering, a source 9 and a drain 10 are formed by a patterning process, and a source 9 and a drain 10 pass through source-drain contact holes on the interlayer insulating layer 8 and The polysilicon active layer 4 is in contact. Then, the doping ions in the polysilicon active layer 4 are activated using rapid thermal annealing or heat treatment furnace annealing to form an effective conductive channel.
  • a SiN film is deposited using PECVD to form a passivation layer 11, and via holes are formed on the passivation layer 11 by a patterning process.
  • the hydrogenation process is performed using rapid thermal annealing or heat treatment furnace annealing to repair defects in the inside and interface of the polysilicon active layer 4.
  • An organic planarization layer having the same via holes is formed over the passivation layer 11 by one patterning process, and the depressions filling the surface of the device form a flat surface.
  • a transparent conductive film is deposited by magnetron sputtering, and the pixel electrode 12 of the pixel region is formed by a patterning process.
  • the pixel defining layer 13 shown in FIG. 1 is formed by the last patterning process.
  • the present disclosure provides a method for fabricating an array substrate, an array substrate, and a display device to solve the problem of long manufacturing process, low process yield, and high cost of the existing low temperature polysilicon array substrate. Defects.
  • the present disclosure provides a method for manufacturing an array substrate, including:
  • a pattern of data lines, source, drain, and pixel electrodes is formed on the substrate on which the passivation layer is formed by one patterning process, and the drain contacts the active layer through the via holes.
  • the step of forming a pattern of the active layer, the gate insulating layer, the gate, and the gate line on the substrate by using one patterning process specifically includes:
  • the photoresist in the fully retained region of the photoresist is stripped.
  • the array substrate is a top emission type
  • the step of forming a pattern of data lines, source, drain, and pixel electrodes on the substrate on which the passivation layer is formed by one patterning process includes:
  • a source/drain metal film and a transparent conductive film of the photoresist removal region by an etching process to form a pattern of a source, a drain, a data line, and a pixel electrode; wherein the source is located at the source a source-drain metal film and a transparent conductive film, the drain is composed of a source-drain metal film and a transparent conductive film located in the drain region, and the data line is a source-drain metal film located in the data line region And a transparent conductive film;
  • the photoresist of the photoresist retention region is stripped.
  • the array substrate is a bottom emission type
  • the step of forming a pattern of data lines, source, drain, and pixel electrodes on the substrate on which the passivation layer is formed by one patterning process includes:
  • composition Removing a source/drain metal film and a transparent conductive film of the photoresist removal region by an etching process to form a pattern of a source, a drain, and a data line, wherein the source is source and drain located in the source region
  • the metal film and the transparent conductive film are composed of a source-drain metal film and a transparent conductive film located in the drain region
  • the data line is composed of a source-drain metal film and a transparent conductive film located in the data line region.
  • the photoresist in the fully retained region of the photoresist is stripped.
  • the step of forming a pattern of data lines, source, drain, and pixel electrodes on the substrate on which the passivation layer is formed by one patterning process further includes:
  • a pixel definition layer is formed by one patterning process.
  • the present disclosure also provides an array substrate, including:
  • a passivation layer covering the active layer, the gate insulating layer, the gate and the gate line, and a via hole is disposed thereon;
  • a source, a drain, a data line, and a pixel electrode wherein the source is composed of a source-drain metal film and a transparent conductive film located in a source region, and the drain is made of a source-drain metal film and a transparent region located in the drain region
  • the conductive film is composed of a source-drain metal film and a transparent conductive film located in a data line region, wherein the pixel electrode is a transparent conductive film located in a pixel electrode region, and the drain passes through the via hole and the Active layer contact.
  • the array substrate is a top emission type
  • the source/drain metal film is located under the transparent conductive film
  • the drain passes through the source/drain metal film located in the drain region and is connected to the via hole Active layer contact.
  • the array substrate is a bottom emission type
  • the source/drain metal film is located on a transparent conductive film
  • the drain passes through a transparent conductive film located in the drain region and is Active layer contact.
  • the array substrate further includes:
  • the present disclosure also provides a display device including the above array substrate.
  • the number of patterning processes in the manufacturing process of the low-temperature polysilicon array substrate is reduced, thereby reducing the process complexity, reducing the manufacturing process time and reducing the process cost.
  • FIG. 1 is a schematic structural view of a conventional low temperature polysilicon array substrate
  • FIG. 2A to 2G are schematic views showing a method of manufacturing the low temperature polysilicon array substrate of FIG. 1;
  • FIG. 3 is a schematic diagram of a method of fabricating an array substrate according to an embodiment of the present disclosure
  • 4A to 4E are schematic views showing a manufacturing method for forming an active layer, a gate insulating layer, a gate electrode, and a gate line by a patterning process using a semi-transmissive mask;
  • 5A to 5D are schematic diagrams showing a method of manufacturing a data line, a source drain, and a pixel electrode by a patterning process for a top emission type array substrate;
  • 6A-6E are schematic diagrams showing a manufacturing method for forming a data line, a source drain, and a pixel electrode by a patterning process for a bottom emission type array substrate;
  • FIG. 7 is a schematic structural diagram of a top emission type array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural view of a bottom emission type array substrate according to an embodiment of the present disclosure.
  • 9A to 9C are schematic views showing a method of manufacturing the top emission type low temperature polysilicon array substrate of FIG. 7;
  • FIGS. 10A to 10B are schematic views showing a method of manufacturing the bottom emission type low temperature polysilicon array substrate of Fig. 8.
  • the embodiment of the present disclosure provides a method for fabricating an array substrate, including the following steps, in order to solve the problem of long manufacturing process, low process yield, and high cost of the low-temperature polysilicon array substrate.
  • Step S11 forming a pattern of an active layer, a gate insulating layer, a gate, and a gate line on the substrate by one patterning process;
  • the substrate may be a base substrate or a base substrate provided with other layers such as a buffer layer.
  • a pattern of an active layer, a gate insulating layer, a gate electrode, and a gate line is formed on the substrate by a patterning process using a semi-transmissive mask.
  • the semi-transmissive mask may be a half-tone mask or a gray-tone mask.
  • Step S12 forming a passivation layer on the substrate on which the active layer, the gate insulating layer, the gate and the gate line are formed, and forming a via hole on the passivation layer by one patterning process;
  • Step S13 forming a pattern of data lines, source and drain electrodes and pixel electrodes on the substrate on which the passivation layer is formed by one patterning process, and the drain contacts the active layer through the via holes;
  • Step S14 forming a pixel definition layer by one patterning process.
  • the fabrication process of the low temperature polysilicon array substrate of the embodiment of the present disclosure requires only four patterning processes, and the existing low temperature of 8 to 9 patterning processes is required due to the use of the semi-transmissive mask.
  • the number of patterning processes in the manufacturing process of the low temperature polysilicon array substrate is reduced, thereby reducing the process complexity, reducing the manufacturing process time and reducing the process cost.
  • the film thickness of the passivation layer may be increased such that the passivation layer may serve as a planarization layer at the same time, and in this case, the step of forming a planarization layer on the passivation layer is not required.
  • a planarization layer may be formed on the passivation layer.
  • a specific method of forming a pattern of an active layer, a gate insulating layer, a gate electrode, and a gate line on a substrate by a patterning process using a transflective mask will be described in detail below.
  • the step of forming a pattern of an active layer, a gate insulating layer, a gate, and a gate line on a substrate by a patterning process using a semi-transmissive mask specifically includes the following steps:
  • the step shown in FIG. 4A is to sequentially form a polysilicon film 40, a gate insulating film 60, and a gate metal film 70 on the substrate, and apply a photoresist 50 on the gate metal film 70.
  • the gate metal film 70 may be a single-layer metal film such as Al, Cu, Mo, Ti, or AlNd, or may be a multilayer metal film such as Mo/Al/Mo or Ti/Al/Ti.
  • the polysilicon film 40 can be formed using the following method:
  • the a-Si film is subjected to a dehydrogenation process to prevent hydrogen explosion during crystallization;
  • the a-Si film treated by the dehydrogenation process is subjected to a crystallization process to form a polysilicon film 40.
  • the crystallization process may be laser annealing crystallization, metal induced crystallization or solid phase crystallization.
  • the polysilicon film 40 can also be cleaned using diluted hydrofluoric acid to reduce the surface roughness of the polysilicon film and reduce the defects of the transistor interface.
  • the thin film transistor channel doping may be performed on the formed polysilicon film 40 by using ion implantation or ion cloud implantation, thereby effectively adjusting the threshold voltage of the thin film transistor and improving the switching characteristics of the transistor.
  • the step shown in FIG. 4B is: exposing and developing the photoresist 50 by using a semi-transmissive mask to form a photoresist full-retention region, a photoresist semi-reserved region, and a photoresist removal region, wherein
  • the photoresist fully reserved region corresponds to the gate and the gate line region
  • the photoresist semi-reserved region corresponds to the active region a source-drain contact region of the layer
  • the photoresist removal region corresponding to a region other than the photoresist-retained region and the photoresist semi-reserved region
  • 5a is a photoresist-retained region
  • the photoresist, 5b is a photoresist of a semi-reserved area of the photoresist.
  • the step shown in FIG. 4C is to remove the polysilicon film 40, the gate insulating film 60 and the gate metal film 70 of the photoresist removal region by an etching process to form a pattern of the active layer 4 and the gate insulating layer 6.
  • the step shown in FIG. 4D is to remove the photoresist 5b of the photoresist semi-reserved region by an ashing process.
  • the step shown in FIG. 4E removing the gate metal film 70 of the photoresist semi-reserved region by an etching process to form a pattern of gate electrodes and gate lines (not shown);
  • the method further includes: using the gate 7 as a source drain
  • the source and drain contact regions of the active layer 4 are ion doped by a method of ion implantation or ion cloud implantation by doping a barrier layer.
  • a specific method of forming a pattern of a data line, a source drain, and a pixel electrode by one patterning process will be described in detail below.
  • the step of forming a pattern of data lines, source and drain electrodes and pixel electrodes by one patterning process includes:
  • the step shown in FIG. 5A the source/drain metal film 90 and the transparent conductive film 120 are sequentially formed, and the photoresist 140 is coated on the transparent conductive film 120.
  • 11 is a passivation layer.
  • the source/drain metal film 90 may be a single-layer metal film such as Al, Cu, Mo, Ti or AlNd, or may be a multilayer metal film such as Mo/Al/Mo or Ti/Al/Ti.
  • the transparent conductive film may be a single-layer oxide conductive film such as ITO (indium tin oxide) or IZO (indium zinc oxide), or may be ITO (indium tin oxide) / Ag / ITO, IZO (indium zinc oxide) /Ag and other composite films.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the step shown in FIG. 5B after exposing and developing the photoresist 140 on the transparent conductive film 120, forming a photoresist retention region corresponding to the source and drain, the data line and the pixel electrode region, and removing the photoresist a photoresist removal region outside the glue retention region; wherein 14a is the light of the photoresist retention region Engraved.
  • the step shown in FIG. 5C is: removing the source/drain metal film 90 and the transparent conductive film 120 of the photoresist removal region by an etching process to form a source 9, a drain 10, a data line (not shown), and a pattern of the pixel electrode 12; wherein the source electrode 9 is composed of a source/drain metal film 9a and a transparent conductive film 12a located in the source region, and the drain electrode 10 is a source/drain metal film located in the drain region 9b and a transparent conductive film 12b, the data line is composed of a source-drain metal film and a transparent conductive film located in the data line region; the drain 10 contacts the active layer through a low-resistance metal film, thereby reducing the drain Contact resistance with the active layer.
  • the step shown in FIG. 5D stripping the photoresist 14a of the photoresist remaining region to expose the source 9, the drain 10, and the pixel electrode 12.
  • the step of forming a pattern of data lines, source and drain electrodes and pixel electrodes by one patterning process includes:
  • the step shown in FIG. 6A is to sequentially form the transparent conductive film 120 and the source/drain metal film 90, and apply the photoresist 150 on the source/drain metal film 90.
  • the step shown in FIG. 6B exposing and developing the photoresist 150 by using a semi-transparent mask to form a photoresist full-retention region, a photoresist semi-reserved region, and a photoresist removal region, wherein
  • the photoresist fully-retained area corresponds to the source drain and the data line area
  • the photoresist semi-reserved area corresponds to the pixel electrode area
  • the photoresist removal area corresponds to the photoresist full-retention area and the light Other regions than the semi-reserved region
  • 15a is a photoresist for the photoresist-retained region
  • 15b is a photoresist for the photoresist semi-reserved region.
  • the step shown in FIG. 6C is to remove the source/drain metal film 90 and the transparent conductive film 120 of the photoresist removal region by an etching process to form a pattern of the source electrode 9, the drain electrode 10, and the data line (not shown).
  • the source 9 is composed of a source/drain metal film 9a and a transparent conductive film 12a located in the source region
  • the drain 10 is composed of a source/drain metal film 9b and a transparent conductive film located in the drain region.
  • the data line is composed of a source-drain metal film and a transparent conductive film located in the data line region.
  • the step shown in FIG. 6D is: removing the photoresist 15b of the photoresist semi-reserved region by an ashing process, and removing the transparent conductive film 120 of the photoresist semi-reserved region by an etching process to form the pixel electrode 12 picture of;
  • the step shown in FIG. 6E stripping the photoresist 15a of the photoresist full-retention region to expose the source 9, drain 10, and data lines.
  • the source-drain metal film and the transparent conductive film may be formed in a vacuum environment, for example, a source-drain metal film is deposited in one sputtering chamber, and transported to another through a robot of a Transfer Chamber.
  • the transparent conductive film is deposited in the cavity, and there is no photolithography process, etching process and cleaning process in the middle, so the interface between the source and drain metal film and the transparent conductive film is not affected by the photoresist, the etching liquid or the gas and the stripping liquid.
  • an embodiment of the present disclosure further provides an array substrate, including:
  • An active layer 4 is located above the substrate 1;
  • a gate electrode 7 and a gate line are located above the gate insulating layer 6;
  • a passivation layer 8 covering the active layer 4, the gate insulating layer 6, the gate electrode 7 and the gate line, and a via hole is disposed thereon;
  • the source 9 is composed of a source/drain metal film 9a and a transparent conductive film 12a located in a source region
  • the drain 10 is composed of a source-drain metal film 9b and a transparent conductive film 12b located in a drain region
  • the data line being composed of a source-drain metal film and a transparent conductive film located in a data line region
  • the pixel electrode 12 is located at the pixel electrode A transparent conductive film of a region through which the drain electrode 10 is in contact with the active layer 4.
  • the substrate 1 may be a base substrate or a base substrate provided with other layers such as a buffer layer.
  • the active layer 4, the gate insulating layer 6, the gate electrode 7, and the gate line are formed by one patterning process, and the source 9, drain 10, data line, and pixel electrode 12 are formed by one patterning process.
  • the source electrode 9, the drain electrode 10, and the data line are all multi-layer film structures, including a source-drain metal film and a transparent conductive film, thereby reducing wire resistance and resulting resistance delay and contact resistance. Improve the picture uniformity quality of the display device.
  • the array substrate may further include:
  • the pixel defines the layer 13.
  • the film thickness of the passivation layer can be increased, so that the passivation layer can simultaneously serve as a planarization layer, and the planarization layer does not need to be separately formed, and the structure and process of the array substrate can be simplified.
  • the array substrate may further include:
  • the buffer layer 2 is located between the substrate 1 and the active layer 4.
  • the buffer layer may be a SiN and SiO 2 film.
  • the SiN film has a strong diffusion barrier property and can suppress the influence of metal ions on the polysilicon film.
  • the SiO 2 film and the polysilicon film have an excellent interface, which can prevent the damage of the SiN film defect to the quality of the polysilicon film.
  • the source/drain metal film is located under the transparent conductive film, and the drain 10 passes through the source/drain metal film 9b located in the drain region and is The via is in contact with the active layer 4.
  • the contact resistance of the drain and the active layer can be reduced by contacting the active layer with a low-resistance metal film.
  • the transparent conductive film is optionally a composite film such as ITO/Ag/ITO or IZO/Ag, and the source-drain metal film in the pixel region has a high light reflectivity, and a metal film in the transparent conductive film (such as Ag, etc. together can increase the light emission rate of the top emission and improve the luminous efficiency of the organic light emitting diode.
  • the source/drain metal film is located on a transparent conductive film, and the drain 10 passes through the transparent conductive film 12b located in the drain region The via hole is in contact with the active layer 4.
  • the present disclosure also provides a display device including the above array substrate.
  • the substrate 1 is initially cleaned to remove foreign particles on the surface of the substrate, and a thin film of SiN and SiO 2 is deposited on the substrate 1 by PECVD as the buffer layer 2.
  • the thickness of the SiN is 50 to 100 nm, and the thickness of the SiO 2 is 100. ⁇ 400nm.
  • the first patterning process (shown in Figure 9A):
  • A-Si (amorphous silicon) film having a thickness of 40 to 100 nm is continuously deposited by PECVD, and the a-Si film is subjected to a dehydrogenation process using a heat treatment furnace to prevent hydrogen explosion during crystallization. Then, the a-Si film is subjected to a crystallization process, and specifically, a crystallization process such as laser annealing crystallization, metal induced crystallization, solid phase crystallization, or the like can be used to form a polycrystalline silicon film. Specifically, the polysilicon film can be cleaned by using diluted hydrofluoric acid to reduce the surface roughness of the polysilicon film and reduce the defects of the transistor interface.
  • the thin film transistor channel doping may be performed on the formed polysilicon film by ion implantation or ion cloud implantation.
  • the doping ions are generally PH 3 /H 2 or B 2 H 6 /H 2 , ions.
  • the implantation dose is between 10 ⁇ 11 and 10 ⁇ 16 ions/cm 2 and the implantation energy is between 10 and 100 KeV.
  • Channel doping can effectively adjust the threshold voltage of the thin film transistor and improve the switching characteristics of the transistor.
  • Forming a gate insulating film depositing a gate insulating film on the polysilicon film by PECVD, generally SiO 2 having a thickness of 30-100 nm and a SiN film having a thickness of 20-100 nm, wherein the SiO 2 film is a bottom layer, SiN The film is the top layer.
  • Forming a gate metal film depositing a gate metal film having a thickness of 200-500 nm on the gate insulating film by magnetron sputtering, and the gate metal film may be a single-layer metal film such as Al, Cu, Mo, Ti or AlNd. It may also be a multilayer metal film such as Mo/Al/Mo or Ti/Al/Ti.
  • Patterning process Using a semi-transparent mask, two different thicknesses of photoresist are formed on the surface of the gate metal film.
  • the semi-transmissive mask can be a half-tone mask or a gray mask. (Gray-tone mask), thicker photoresist thickness between 1 and 3 microns, corresponding to the gate and gate line regions.
  • the thinner photoresist has a thickness of 0.5 to 1 micron, corresponding to the pattern of source and drain vias.
  • the gate metal film without photoresist protection is removed by an etching process. According to different materials of the metal film, the etching process may be wet etching or dry etching, for example, using wet etching to remove Mo/Al/Mo.
  • the multilayer metal film may also be subjected to inductively coupled plasma etching of a mixed gas of CCl 2 /BCl 3 and CF 4 /O 2 to remove the Ti/Al/Ti multilayer metal film.
  • the exposed gate insulating film is etched by plasma or inductively coupled plasma using a gas such as CF 4 , CF 4 /O 2 , or CHF 3 /O 2 to form a gate insulating layer 6 without O 2 or Lower O 2 flow.
  • a gas such as CF 4 , CF 4 /O 2 , or CHF 3 /O 2 to form a gate insulating layer 6 without O 2 or Lower O 2 flow.
  • the polysilicon active layer 4 is formed by etching a polysilicon film by a plasma or an inductively coupled plasma method using a mixed gas such as CF 4 /O 2 , CHF 3 /O 2 or SF 6 /O 2 .
  • the etching is performed to completely remove the polysilicon film not protected by the photoresist, and the transistor characteristics due to the connection of the polysilicon film are prevented from deteriorating.
  • the thin photoresist is removed by an ashing process, and the gate is left over and The photoresist connected to the gate line removes the gate metal film not covered by the photoresist by wet etching or dry etching to form a pattern of the gate electrode 7 and the gate line. Finally, the residual photoresist is completely removed using a stripper to expose the gate 7 and the gate lines.
  • the gate 7 is used as a source-drain doping barrier layer, and the source-drain contact regions of the polysilicon active layer 4 are ion-doped by ion implantation or ion cloud implantation.
  • the dopant ions are generally PH 3 /H 2 or B. 2 H 6 /H 2 , the ion implantation dose is between 10 ⁇ 15 and 10 ⁇ 16 ions/cm 2 , and the implantation energy is between 10 and 100 KeV.
  • the channel doping and source-drain doping ions are activated by a rapid thermal annealing process to enhance the conductive properties of the polysilicon active layer.
  • the second patterning process (shown in Figure 9B):
  • a dielectric film is deposited on the gate 7 and the gate line by PECVD to form a passivation layer 11, typically a SiN film containing hydrogen between 200 and 500 nm. Then, a rapid thermal annealing or a heat treatment furnace annealing process is performed, and the Si 2 film of the passivation layer 11 and the gate insulating layer 6 is used to realize the SO 2 interface inside the polysilicon active layer 4 and the polysilicon active layer 4 and the gate insulating layer 6. The hydrogenation, passivating internal defects and interface defects, improves the transistor characteristics of the polysilicon active layer 4.
  • Passivation layer vias are formed by plasma or inductively coupled plasma etching using a mask mask process.
  • the third patterning process (shown in Figure 9C):
  • a source-drain metal film having a thickness of 200 to 500 nm is deposited on the passivation layer 11 by magnetron sputtering.
  • the source/drain metal film may be a single-layer metal film such as Al, Cu, Mo, Ti or AlNd, or may be A multilayer metal film such as Mo/Al/Mo or Ti/Al/Ti.
  • a transparent conductive film is deposited on the source/drain metal film by magnetron sputtering.
  • the transparent conductive film is a composite film of ITO/Ag/ITO or IZO/Ag.
  • the thickness of ITO is 10 to 50 nm, which is 10 to 50 nm.
  • a pattern of source and drain, data lines, and pixel electrodes is formed on the transparent conductive film by a photomask process.
  • the source/drain metal film and the transparent conductive film not protected by the photoresist are removed by an etching process to form the source electrode 9, the drain electrode 10, and the connected data lines and the pixel electrode 12.
  • the source electrode 9 is composed of a source/drain metal film 9a and a transparent conductive film 12a located in a source region
  • the drain electrode 10 is composed of a source/drain metal film 9b and a transparent conductive film 12b located in a drain region, the data line It consists of a source-drain metal film and a transparent conductive film located in the data line region.
  • the metal etching process can It is wet etching, or dry etching such as inductively coupled plasma etching, etching the oxide transparent conductive film using wet etching.
  • the data line, the source and drain of the thin film transistor and the pixel electrode are simultaneously formed by one patterning process, and the source and the drain of the data line and the thin film transistor each comprise a low resistance metal film and a transparent conductive film, wherein the drain 10 passes through a low resistance source and drain
  • the metal thin film contacts the polysilicon active layer 4 to form a drain of low contact resistance.
  • the transparent conductive film of the pixel electrode 12 forms an anode electrode that is in contact with the organic light-emitting material.
  • the source-drain metal film of the pixel region has a high light reflectivity, and together with the metal film (such as Ag) in the transparent conductive film 120, the light emission rate of the top emission can be increased, and the luminous efficiency of the AMOLED can be improved.
  • the pixel defining layer 13 is formed by one patterning process, and the pixel defining layer may be made of, for example, Acrylic or the like, and has a thickness of 1 to 4 ⁇ m.
  • a final thermal annealing process is performed using a rapid thermal annealing or heat treatment furnace to stabilize low temperature polysilicon thin film transistor characteristics.
  • the gate line/gate 7, the gate insulating layer 6, the polysilicon active layer 4, and the passivation layer 11 are formed by the same process as the top emission type low temperature polysilicon array substrate.
  • a transparent conductive film 120 is deposited on the passivation layer 11 by magnetron sputtering, and the transparent conductive film is indium tin oxide (ITO), indium zinc oxide (IZO) process, tin oxide aluminum (ZTO).
  • the oxide transparent conductive film has a thickness of 20 to 100 nm.
  • a source/drain metal film 90 having a thickness of 200 to 500 nm is deposited on the transparent conductive film 120 by magnetron sputtering.
  • the metal film may be a single metal film such as Al, Cu, Mo, Ti or AlNd, or may be Mo.
  • Multilayer metal film such as /Al/Mo or Ti/Al/Ti.
  • Two different thicknesses of photoresist 5a and 5b are formed on the surface of the source/drain metal film 90 using a semi-transmissive mask, which may be a half-tone mask or a gray mask. Gray-tone mask.
  • the photoresist 5a has a thickness of between 1 and 3 ⁇ m, covering the source 9, the drain 10 and the data line, and the photoresist 5b has a thickness of 0.5 to 1.5 ⁇ m and covers the pixel electrode 12.
  • the source/drain metal film 90 and the transparent conductive film 120b which are not protected by the photoresist are removed by etching to form the drain 10, the source 9 and their connected data lines.
  • the source 9 is composed of a source/drain metal film 9a and a transparent conductive film 12a located in a source region
  • the drain 10 is composed of a source/drain metal film 9b and a transparent conductive film 12b located in a drain region
  • the data line is composed of a source-drain metal film and a transparent conductive film located in the data line region, wherein the metal etching process may be wet etching, or dry etching such as inductively coupled plasma etching, etching the oxide using wet etching.
  • the thin photoresist 5b is removed by a plasma ashing process, the photoresist 5a is left as an etch barrier, and the source/drain metal film 90 is etched by plasma or an inductively coupled plasma method to remove the source covered by the pixel region.
  • the metal film 90 is leaked to form the pixel electrode 12.

Abstract

一种阵列基板的制造方法、阵列基板及显示装置，该阵列基板的制造方法包括：通过一次构图工艺在基板(1)上形成有源层(40)、栅极绝缘层(60)、栅极和栅线(7)的图案；在形成有所述有源层(40)、栅极绝缘层(60)、栅极和栅线(7)的基板(1)上形成钝化层(11)，并通过一次构图工艺在所述钝化层(11)上形成过孔；通过一次构图工艺在形成有所述钝化层(11)的基板(1)上形成数据线、源极(9)、漏极(10)及像素电极(12)的图案，所述漏极(10)通过所述过孔与所述有源层(40)接触。

Description

一种阵列基板的制造方法、阵列基板及显示装置
相关申请的交叉引用
本申请主张在2014年6月24日在中国提交的中国专利申请号No.201410289560.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板的制造方法、阵列基板及显示装置。
背景技术
相对于液晶显示器(LCD)，有机发光二极管显示器(OLED)具有反应速度快、重量轻、可弯曲和广视角等优点。而有源矩阵有机发光二极管(AMOLED)更具有驱动电流小和功耗低的优势，适合于高解析度显示器。有源矩阵有机发光二极管架构可使用非晶硅、多晶硅、氧化物半导体或有机薄膜晶体管驱动，其中，低温多晶硅具有高达100cm2/V-s的迁移率，其高电流特性正好符合有机发光二极管严格的要求，低操作电压与高密度的驱动架构使得有机发光二极管寿命较长，因而目前成功商业化生产的AMOLED绝大部分使用低温多晶硅的阵列基板。
在传统的低温多晶硅阵列基板制造工艺过程中，一般需要8～9道构图工艺。下面参照图2A～图2G，对图1所示的现有的低温多晶硅阵列基板的制造工艺进行说明。
如图2A所示，通过等离子体增强化学气相沉积(PECVD)艺，在整个衬底基板1上形成二氧化硅(SiO2)和氮化硅(SiN)薄膜的缓冲层2。其后，利用PECVD或者其它化学(或物理)气相沉积方法在缓冲层2上形成非晶硅薄膜(a-Si)。通过激光退火(ELA)或者固相结晶(SPC)方法，使得非晶硅薄膜成为多晶硅薄膜。而后，使用传统构图工艺形成多晶硅有源层4和多晶硅存储电容3。并利用离子注入工艺进行低浓度离子掺杂，在多晶硅有源层4中形成薄膜晶体管要求的半导体沟道。
如图2B所示，通过构图工艺在多晶硅有源层4上形成光阻材料组成的光刻胶5，以保护多晶硅有源层4不被离子注入。进行离子注入工艺，在多晶硅存储电容3上形成低电阻的掺杂多晶硅薄膜。
如图2C所示，使用PECVD沉积SiO2或SiO2和SiN薄膜，在多晶硅有源层4、多晶硅存储电容3和缓冲层2上形成栅极绝缘层6。通过磁控溅射等物理气相沉积方法在栅极绝缘层6上沉积栅金属薄膜，利用构图工艺形成栅极7。使用栅极7作为离子注入阻挡层，对多晶硅有源层4进行离子掺杂，形成低阻抗的源漏极接触区。
如图2D所示，使用PECVD沉积SiO2和SiN薄膜形成层间绝缘层8，并通过构图工艺在层间绝缘层8上形成源漏极接触孔。
如图2E所示，使用磁控溅射沉积源漏金属薄膜，通过构图工艺形成源极9和漏极10，源极9和漏极10通过层间绝缘层8上的源漏极接触孔与多晶硅有源层4接触。然后，使用快速热退火或热处理炉退火，激活多晶硅有源层4中掺杂的离子，形成有效的导电沟道。
如图2F所示，使用PECVD沉积一层SiN薄膜，形成钝化层11，并通过构图工艺在钝化层11上形成过孔。使用快速热退火或热处理炉退火进行氢化工艺，修复多晶硅有源层4内部和界面的缺陷。通过一次的构图工艺，在钝化层11之上形成具有相同过孔的有机平坦化层，填充器件表面的低凹形成平坦表面。
如图2G所示，使用磁控溅射沉积一层透明导电薄膜，通过构图工艺形成像素区域的像素电极12。
最后，通过最后一道构图工艺形成图1中所示的像素定义层13。
综上所述，现有技术中至少需要8～9道构图工艺才能形成图1所示的低温多晶硅阵列基板，导致较长的工艺时间和较低的工艺良率，使得阵列基板成本较高。
发明内容
有鉴于此，本公开提供一种阵列基板的制造方法、阵列基板及显示装置，以解决现有的低温多晶硅阵列基板的制造工艺时间长、工艺良率低及成本高 的缺陷。
为解决上述技术问题，本公开提供一种阵列基板的制造方法，包括：
通过一次构图工艺在基板上形成有源层、栅极绝缘层、栅极和栅线的图案；
在形成有所述有源层、栅极绝缘层、栅极和栅线的基板上形成钝化层，并通过一次构图工艺在所述钝化层上形成过孔；
通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源极、漏极及像素电极的图案，所述漏极通过所述过孔与所述有源层接触。
可选地，所述通过一次构图工艺在基板上形成有源层、栅极绝缘层、栅极和栅线的图案的步骤具体包括：
依次形成多晶硅薄膜、栅极绝缘薄膜及栅金属薄膜；
在所述栅金属薄膜上涂覆光刻胶；
采用半透式掩膜版对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域以及光刻胶去除区域，其中，所述光刻胶全保留区域对应栅极和栅线区域，所述光刻胶半保留区域对应有源层的源漏接触区域，所述光刻胶去除区域对应除所述光刻胶全保留区域及所述光刻胶半保留区域之外的其他区域；
采用刻蚀工艺去除所述光刻胶去除区域的多晶硅薄膜、栅极绝缘薄膜及栅金属薄膜，形成栅极绝缘层和有源层的图案；
利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
利用刻蚀工艺去除所述光刻胶半保留区域的栅金属薄膜，形成栅极及栅线的图案；
剥离所述光刻胶全保留区域的光刻胶。
可选地，所述阵列基板为顶发射型，所述通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源极、漏极及像素电极的图案的步骤包括：
依次形成源漏金属薄膜和透明导电薄膜；
在所述透明导电薄膜上涂覆光刻胶；
对所述透明导电薄膜上的光刻胶进行曝光、显影后，形成对应源极区域、漏极区域、数据线区域及像素电极区域的光刻胶保留区域及除所述光刻胶保 留区域之外的光刻胶去除区域；
采用刻蚀工艺去除所述光刻胶去除区域的源漏极金属薄膜以及透明导电薄膜，形成源极、漏极、数据线及像素电极的图案；其中，所述源极由位于所述源极区域的源漏金属薄膜及透明导电薄膜组成，所述漏极由位于所述漏极区域的源漏金属薄膜及透明导电薄膜组成，所述数据线由位于所述数据线区域的源漏金属薄膜及透明导电薄膜组成；
剥离所述光刻胶保留区域的光刻胶。
可选地，所述阵列基板为底发射型，所述通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源极、漏极及像素电极的图案的步骤包括：
依次形成透明导电薄膜和源漏金属薄膜；
在所述源漏金属薄膜上涂覆光刻胶；
采用半透式掩膜版对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域以及光刻胶去除区域，其中，所述光刻胶全保留区域对应源极区域、漏极区域和数据线区域，所述光刻胶半保留区域对应像素电极区域，所述光刻胶去除区域对应除所述光刻胶全保留区域及所述光刻胶半保留区域之外的其他区域；
采用刻蚀工艺去除所述光刻胶去除区域的源漏金属薄膜和透明导电薄膜，形成源极、漏极和数据线的图案，其中，所述源极由位于所述源极区域的源漏金属薄膜及透明导电薄膜组成，所述漏极由位于所述漏极区域的源漏金属薄膜及透明导电薄膜组成，所述数据线由位于所述数据线区域的源漏金属薄膜及透明导电薄膜组成；
利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
利用刻蚀工艺去除所述光刻胶半保留区域的透明导电薄膜，形成像素电极的图案；
剥离所述光刻胶全保留区域的光刻胶。
可选地，所述通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源极、漏极及像素电极的图案的步骤之后还包括：
通过一次构图工艺形成像素定义层。
本公开还提供一种阵列基板，包括：
基板；
有源层，位于所述基板之上；
栅极绝缘层，位于所述有源层之上；
栅极和栅线，位于所述栅极绝缘层之上；
钝化层，覆盖所述有源层、栅极绝缘层、栅极及栅线，其上设置有过孔；
源极、漏极、数据线及像素电极，其中，所述源极由位于源极区域的源漏金属薄膜和透明导电薄膜构成，所述漏极由位于漏极区域的源漏金属薄膜和透明导电薄膜构成，所述数据线由位于数据线区域的源漏金属薄膜和透明导电薄膜构成，所述像素电极为位于像素电极区域的透明导电薄膜，所述漏极通过所述过孔与所述有源层接触。
可选地，所述阵列基板为顶发射型，所述源漏金属薄膜位于透明导电薄膜之下，所述漏极通过位于所述漏极区域的源漏金属薄膜并借助所述过孔与所述有源层接触。
可选地，所述阵列基板为底发射型，所述源漏金属薄膜位于透明导电薄膜之上，所述漏极通过位于所述漏极区域的透明导电薄膜并借助所述过孔与所述有源层接触。
可选地，所述阵列基板还包括：
像素定义层。
本公开还提供一种显示装置，包括上述阵列基板。
本公开的上述技术方案的有益效果如下：
减少了低温多晶硅阵列基板制造工艺过程中的构图工艺的次数，从而降低了工序复杂度，在缩短制造工艺时间的同时降低了工艺成本。
附图说明
图1为现有的低温多晶硅阵列基板的结构示意图；
图2A～2G为图1中的低温多晶硅阵列基板的制造方法示意图；
图3为本公开实施例的阵列基板的制造方法示意图；
图4A～4E为采用半透式掩膜版通过一次构图工艺形成有源层、栅极绝缘层、栅极和栅线的制造方法示意图；
图5A～5D为针对顶发射型的阵列基板，通过一次构图工艺形成数据线、源漏极及像素电极的一制造方法示意图；
图6A～6E为针对底发射型的阵列基板，通过一次构图工艺形成数据线、源漏极及像素电极的一制造方法示意图；
图7为本公开实施例的顶发射型的阵列基板的结构示意图；
图8为本公开实施例的底发射型的阵列基板的结构示意图；
图9A～9C为图7中的顶发射型的低温多晶硅阵列基板的制造方法示意图；
图10A～10B为图8中的底发射型的低温多晶硅阵列基板的制造方法示意图。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
为解决现有的低温多晶硅阵列基板的制造工艺时间长、工艺良率低及成本高的问题，如图3所示，本公开实施例提供一种阵列基板的制造方法，包括以下步骤：
步骤S11：通过一次构图工艺在基板上形成有源层、栅极绝缘层、栅极和栅线的图案；
其中，所述基板可以为衬底基板，也可以为设置有其他层(如缓冲层)的衬底基板。
具体的，采用半透式掩膜版，通过一次构图工艺在基板上形成有源层、栅极绝缘层、栅极和栅线的图案。所述半透式掩膜版可以为半色调掩膜版(Half-tone mask)或者灰色调掩膜版(Gray-tone mask)。
步骤S12：在形成有所述有源层、栅极绝缘层、栅极和栅线的基板上形成钝化层，并通过一次构图工艺在所述钝化层上形成过孔；
步骤S13：通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源漏极及像素电极的图案，所述漏极通过所述过孔与所述有源层接触；
步骤S14：通过一次构图工艺形成像素定义层。
从上述实施例可以看出，由于采用了半透式掩膜版，本公开实施例的低温多晶硅阵列基板的制造工艺仅需要4道构图工艺，与现有的需要8～9道构图工艺的低温多晶硅阵列基板的制造工艺相比，减少了低温多晶硅阵列基板制造工艺过程中的构图工艺的次数，从而降低了工序复杂度，在缩短制造工艺时间的同时降低了工艺成本。
在本公开的其他实施例中，可以增加钝化层的膜厚度，使得钝化层可同时作为平坦化层，此时，则不需要再在钝化层上形成平坦化层的步骤。或者，也可以在钝化层上再制作一平坦化层。
下面对采用半透式掩膜版，通过一次构图工艺在基板上形成有源层、栅极绝缘层、栅极和栅线的图案的具体方法进行详细说明。
如图4A～4E所示，采用半透式掩膜版，通过一次构图工艺在基板上形成有源层、栅极绝缘层、栅极和栅线的图案的步骤具体包括如下步骤：
图4A所示的步骤：在基板上依次形成多晶硅薄膜40、栅极绝缘薄膜60及栅金属薄膜70，并在所述栅金属薄膜70上涂覆光刻胶50。
该栅金属薄膜70可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。
具体的，可以使用以下方法形成多晶硅薄膜40：
形成a-Si(非晶硅)薄膜；
对a-Si薄膜进行脱氢工艺处理，以防止结晶过程中的氢爆；
对脱氢工艺处理后的a-Si薄膜进行结晶工艺处理，形成多晶硅薄膜40。
其中，结晶工艺可以为激光退火结晶、金属诱导结晶或固相结晶等。
在形成多晶硅薄膜40之后，还可以使用稀释的氢氟酸对多晶硅薄膜40进行清洗，以降低多晶硅薄膜的表面粗糙度，减少晶体管界面的缺陷。
另外，可选地，还可以使用离子注入或者离子云注入的方法，对形成的多晶硅薄膜40进行薄膜晶体管沟道掺杂，从而有效调整薄膜晶体管的阈值电压，改善晶体管的开关特性。
图4B所示的步骤：采用半透式掩膜版对所述光刻胶50进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域以及光刻胶去除区域，其中，所述光刻胶全保留区域对应栅极和栅线区域，所述光刻胶半保留区域对应有源 层的源漏接触区域，所述光刻胶去除区域对应除所述光刻胶全保留区域及所述光刻胶半保留区域之外的其他区域；图中，5a为光刻胶全保留区域的光刻胶，5b为光刻胶半保留区域的光刻胶。
图4C所示的步骤：采用刻蚀工艺去除所述光刻胶去除区域的多晶硅薄膜40、栅极绝缘薄膜60及栅金属薄膜70，形成有源层4和栅极绝缘层6的图案。
图4D所示的步骤：利用灰化工艺去除所述光刻胶半保留区域的光刻胶5b。
图4E所示的步骤：利用刻蚀工艺去除所述光刻胶半保留区域的栅金属薄膜70，形成栅极及栅线(图未示出)的图案；
最后，剥离所述光刻胶全保留区域的光刻胶，以露出所述栅极7和栅线。
为了提高有源层的源漏接触区的导电性能，本公开实施例中，在剥离所述光刻胶全保留区域的光刻胶的步骤之后还可以包括：使用所述栅极7作为源漏掺杂阻挡层，通过离子注入或离子云注入的方法，对所述有源层4的源漏接触区进行离子掺杂。
下面对通过一次构图工艺形成数据线、源漏极及像素电极的图案的具体方法进行详细说明。
如图5A～5D所示，当本公开实施例的阵列基板为顶发射型时，所述通过一次构图工艺形成数据线、源漏极及像素电极的图案的步骤包括：
图5A所示的步骤：依次形成源漏金属薄膜90和透明导电薄膜120，并在所述透明导电薄膜120上涂覆光刻胶140。图中11为钝化层。
该源漏金属薄膜90可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。
该透明导电薄膜可以是单层的氧化物导电薄膜，如ITO(氧化铟锡)或IZO(氧化铟锌)等，也可以是ITO(氧化铟锡)/Ag/ITO、IZO(氧化铟锌)/Ag等复合薄膜。
图5B所示的步骤：对所述透明导电薄膜120上的光刻胶140进行曝光、显影后，形成对应源漏极、数据线及像素电极区域的光刻胶保留区域及除所述光刻胶保留区域之外的光刻胶去除区域；其中，14a为光刻胶保留区域的光 刻胶。
图5C所示的步骤：采用刻蚀工艺去除所述光刻胶去除区域的源漏极金属薄膜90以及透明导电薄膜120，形成源极9、漏极10、数据线(图未示出)及像素电极12的图案；其中，所述源极9由位于所述源极区域的源漏金属薄膜9a及透明导电薄膜12a组成，所述漏极10由位于所述漏极区域的源漏金属薄膜9b及透明导电薄膜12b组成，所述数据线由位于所述数据线区域的源漏金属薄膜及透明导电薄膜组成；漏极10通过低电阻的金属薄膜接触有源层，从而可以减小漏极与有源层的接触电阻。
图5D所示的步骤：剥离所述光刻胶保留区域的光刻胶14a，以露出所述源极9、漏极10及像素电极12。
如图6A～6E所示，当本公开实施例的阵列基板为底发射型时，所述通过一次构图工艺形成数据线、源漏极及像素电极的图案的步骤包括：
图6A所示的步骤：依次形成透明导电薄膜120和源漏金属薄膜90，并在所述源漏金属薄膜90上涂覆光刻胶150。
图6B所示的步骤：采用半透式掩膜版对所述光刻胶150进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域以及光刻胶去除区域，其中，所述光刻胶全保留区域对应源漏极和数据线区域，所述光刻胶半保留区域对应像素电极区域，所述光刻胶去除区域对应除所述光刻胶全保留区域及所述光刻胶半保留区域之外的其他区域；其中，15a为光刻胶全保留区域的光刻胶，15b为光刻胶半保留区域的光刻胶。
图6C所示的步骤：采用刻蚀工艺去除所述光刻胶去除区域的源漏金属薄膜90和透明导电薄膜120，形成源极9、漏极10和数据线(图未示出)的图案，其中，所述源极9由位于所述源极区域的源漏金属薄膜9a及透明导电薄膜12a组成，所述漏极10由位于所述漏极区域的源漏金属薄膜9b及透明导电薄膜12b组成，所述数据线由位于所述数据线区域的源漏金属薄膜及透明导电薄膜组成。
图6D所示的步骤：利用灰化工艺去除所述光刻胶半保留区域的光刻胶15b，并利用刻蚀工艺去除所述光刻胶半保留区域的透明导电薄膜120，形成像素电极12的图案；
图6E所示的步骤：剥离所述光刻胶全保留区域的光刻胶15a，以露出所述源极9、漏极10和数据线。
本公开实施例中，源漏金属薄膜和透明导电薄膜可以在一次真空环境下形成，例如在一个溅射腔内沉积源漏金属薄膜，通过真空传递室(Transfer Chamber)的机器人运输到另一个溅射腔内沉积透明导电薄膜，中间没有光刻工艺、刻蚀工艺和清洗工艺等，因而源漏金属薄膜和透明导电薄膜界面不受光刻胶、刻蚀液或气体以及剥离液等的影响。
对应于上述制造方法，如图7和图8所示，本公开实施例还提供一种阵列基板，包括：
基板1；
有源层4，位于所述基板1之上；
栅极绝缘层6，位于所述有源层4之上；
栅极7和栅线(图未示出)，位于所述栅极绝缘层6之上；
钝化层8，覆盖所述有源层4、栅极绝缘层6、栅极7及栅线，其上设置有过孔；
源极9、漏极10、数据线(图未示出)及像素电极12，其中，所述源极9由位于源极区域的源漏金属薄膜9a和透明导电薄膜12a构成，所述漏极10由位于漏极区域的源漏金属薄膜9b和透明导电薄膜12b构成，所述数据线由位于数据线区域的源漏金属薄膜和透明导电薄膜构成，所述像素电极12为位于所述像素电极区域的透明导电薄膜，所述漏极10通过所述过孔与所述有源层4接触。
其中，所述基板1可以为衬底基板，也可以为设置有其他层(如缓冲层)的衬底基板。
本公开实施例中，有源层4、栅极绝缘层6、栅极7和栅线通过一次构图工艺形成，源极9、漏极10、数据线及像素电极12通过一次构图工艺形成。
本公开实施例中，源极9、漏极10及数据线均为多层薄膜结构，即包括源漏金属薄膜和透明导电薄膜，从而可以降低导线电阻和由此导致的阻容延迟以及接触电阻，改善显示装置的画面均匀性品质。
可选地，所述阵列基板还可以包括：
像素定义层13。
本公开实施例中，可增加钝化层的膜厚，使得钝化层可同时作为平坦化层，则不需要单独制作平坦化层，可以简化阵列基板的结构和工艺。当然，也可以在钝化层上单独制作一次平坦化层。
可选地，所述阵列基板还可以包括：
缓冲层2，位于所述基板1与所述有源层4之间。
缓冲层可以为SiN和SiO2薄膜。SiN薄膜具有很强的扩散阻挡特性，可以抑制金属离子对于多晶硅薄膜的影响。SiO2薄膜与多晶硅薄膜具有优良的界面，可以防止SiN薄膜缺陷对多晶硅薄膜质量的损害。
如图7所示，当所述阵列基板为顶发射型时，所述源漏金属薄膜位于透明导电薄膜之下，所述漏极10通过位于漏极区域的源漏金属薄膜9b并借助所述过孔与有源层4接触。通过低电阻的金属薄膜接触有源层，可以减小漏极与有源层的接触电阻。本实施例中，透明导电薄膜可选地为ITO/Ag/ITO或IZO/Ag等复合薄膜，像素区域的源漏金属薄膜具有较高的光反射率，和透明导电薄膜中的金属薄膜(如Ag等)一起可以增加顶发射的出光率，提高有机发光二极管的发光效率。
如图8所示，当所述阵列基板为底发射型时，所述源漏金属薄膜位于透明导电薄膜之上，所述漏极10通过位于所述漏极区域的透明导电薄膜12b并借助所述过孔与有源层4接触。
本公开还提供一种显示装置，包括上述阵列基板。
下面，参考图9A～9C，对图7所示的顶发射型的低温多晶硅阵列基板的制造工艺进行详细说明。
首先，对基板1进行初始清洗，以清除基板表面的杂质粒子，使用PECVD在基板1上沉积一层SiN和SiO2薄膜作为缓冲层2，SiN的厚度为50～100nm，SiO2的厚度为100～400nm。
第一次构图工艺(如图9A所示)：
形成多晶硅薄膜：使用PECVD连续沉积一层厚度在40～100nm的a-Si(非晶硅)薄膜，使用热处理炉对a-Si薄膜进行脱氢工艺处理，以防止结晶过程中的氢爆。然后，进行a-Si薄膜进行结晶工艺处理，具体的，可以使用 激光退火结晶、金属诱导结晶、固相结晶等结晶工艺，形成多晶硅薄膜。具体的，还可以使用稀释的氢氟酸对多晶硅薄膜进行清洗，以降低多晶硅薄膜的表面粗糙度，减少晶体管界面的缺陷。此外，还可以使用离子注入或者离子云注入的方法，对形成的多晶硅薄膜进行薄膜晶体管沟道掺杂，具体的，掺杂离子一般为PH3/H2或者B2H6/H2，离子注入剂量在10^11～10^16ions/cm2之间，注入能量在10～100KeV之间。沟道掺杂可以有效调整薄膜晶体管的阈值电压，改善晶体管的开关特性。
形成栅极绝缘薄膜：使用PECVD在多晶硅薄膜上沉积一层栅极绝缘薄膜，一般是厚度在30～100nm的SiO2和厚度在20～100nm的SiN两层薄膜，其中SiO2薄膜为底层，SiN薄膜为顶层。
形成栅金属薄膜：使用磁控溅射在栅极绝缘薄膜上沉积一层厚度为200～500nm的栅金属薄膜，该栅金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。
构图工艺：使用一种半透式掩膜版，在栅金属薄膜表面形成两种不同厚度的光刻胶，半透式掩膜版可以是半色调(Half-tone mask)或者灰色调掩膜版(Gray-tone mask)，较厚的光刻胶的厚度在1～3微米之间，对应栅极和栅线区域。较薄的光刻胶的厚度是0.5～1微米，对应源漏极过孔的图案。通过刻蚀工艺去除没有光刻胶保护的栅金属薄膜，根据金属薄膜的不同材料，刻蚀工艺可以是湿法腐蚀，也可以是干法腐蚀，例如使用湿法腐蚀方法去除Mo/Al/Mo多层金属薄膜，也可以采用CCl2/BCl3和CF4/O2等混合气体的电感耦合等离子体刻蚀，去除Ti/Al/Ti多层金属薄膜。
使用CF4、CF4/O2、或者CHF3/O2等气体，通过等离子体或者电感耦合等离子方法，刻蚀去除暴露的栅极绝缘薄膜，形成栅极绝缘层6，不需要O2或者较低的O2流量。
使用CF4/O2、CHF3/O2或者SF6/O2等混合气体，通过等离子体或者电感耦合等离子方法进行多晶硅薄膜的刻蚀，形成多晶硅有源层4。刻蚀以完全去除未被光刻胶保护的多晶硅薄膜为终点，防止因为多晶硅薄膜相连导致的晶体管特性下降。
而后，在光刻设备里通过灰化工艺去除较薄的光刻胶，保留覆盖栅极及 其相连栅线的光刻胶，通过湿法腐蚀或者干法腐蚀去除未被光刻胶覆盖的栅金属薄膜，形成栅极7和栅线的图案。最后，使用剥离机完全去除残留的光刻胶，以露出栅极7和栅线。
使用栅极7作为源漏掺杂阻挡层，通过离子注入或者离子云注入的方法，对多晶硅有源层4的源漏接触区进行离子掺杂，掺杂离子一般为PH3/H2或者B2H6/H2，离子注入剂量在10^15～10^16ions/cm2之间，注入能量在10～100KeV之间。通过快速热退火工艺，激活沟道掺杂和源漏掺杂离子，增强多晶硅有源层的导电特性。
第二次构图工艺(如图9B所示)：
使用PECVD在栅极7及栅线上沉积一层介质薄膜形成钝化层11，一般是厚度在200～500nm之间含氢的SiN薄膜。而后，进行快速热退火或者热处理炉退火工艺，利用钝化层11和栅极绝缘层6的SiN薄膜，实现多晶硅有源层4内部以及多晶硅有源层4与栅极绝缘层6的SO2界面的氢化，钝化内部缺陷和界面缺陷，提高多晶硅有源层4的晶体管特性。
使用掩膜版光罩工艺，通过等离子体或者电感耦合等离子刻蚀方法，形成钝化层过孔。
第三次构图工艺(如图9C所示)：
使用磁控溅射在钝化层11上沉积一层厚度为200～500nm的源漏金属薄膜，该源漏金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。
使用磁控溅射在源漏金属薄膜上沉积一层透明导电薄膜，该透明导电薄膜为ITO/Ag/ITO或IZO/Ag等复合薄膜，当透明导电薄膜为ITO/Ag/ITO时，ITO厚度为10～50nm，Ag金属薄膜厚度为20～100nm。
通过光罩工艺在透明导电薄膜上形成源漏极、数据线和像素电极的图案。
连续进行刻蚀工艺去除未被光刻胶保护的源漏金属薄膜和透明导电薄膜，形成源极9、漏极10及其相连的数据线和像素电极12。所述源极9由位于源极区域的源漏金属薄膜9a和透明导电薄膜12a构成，所述漏极10由位于漏极区域的源漏金属薄膜9b和透明导电薄膜12b构成，所述数据线由位于数据线区域的源漏金属薄膜和透明导电薄膜构成。其中，金属刻蚀工艺可以 是湿法腐蚀，或者干法腐蚀如电感耦合等离子体刻蚀，使用湿法腐蚀刻蚀氧化物透明导电薄膜。以一次构图工艺同时形成数据线、薄膜晶体管的源漏极和像素电极，数据线和薄膜晶体管的源漏极均包含低电阻的金属薄膜和透明导电薄膜，其中漏极10通过低电阻的源漏金属薄膜接触多晶硅有源层4，形成低接触电阻的漏极。像素电极12的透明导电薄膜形成和有机发光材料接触的阳电极。而，像素区域的源漏金属薄膜具有较高的光反射率，和透明导电薄膜120中的金属薄膜(如Ag等)一起可以增加顶发射的出光率，提高AMOLED的发光效率。
第四次构图工艺：
通过一次构图工艺形成像素定义层13，像素定义层可以采用如亚克力(Acrylic)等，厚度是1～4微米。
最后，使用快速热退火或热处理炉，进行最后的退火处理，以稳定低温多晶硅薄膜晶体管特性。
下面，参考图10A～10B，对图8所示的底发射型的低温多晶硅阵列基板的制造工艺进行详细说明。
第一次和第二次构图工艺：
如图9A-9B所示，采用与顶发射型的低温多晶硅阵列基板相同的工艺形成栅线/栅极7、栅极绝缘层6、多晶硅有源层4和钝化层11。
第三次构图工艺：
如图10A所示，使用磁控溅射在钝化层11上沉积一层透明导电薄膜120，该透明导电薄膜为氧化铟锡(ITO)、氧化铟锌(IZO)工艺氧化锡铝(ZTO)等氧化物透明导电薄膜，厚度为20～100nm。
使用磁控溅射在透明导电薄膜120上沉积一层厚度为200～500nm的源漏金属薄膜90，该金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。使用一种半透式掩膜版在源漏金属薄膜90表面形成两种不同厚度的光刻胶5a和5b，半透式掩膜版可以是半色调(Half-tone mask)或者灰色调掩膜版(Gray-tone mask)。光刻胶5a的厚度在1～3微米之间，覆盖源极9、漏极10及数据线，光刻胶5b的厚度是0.5～1.5微米，覆盖像素电极12。
如图10B所示，刻蚀去除未被光刻胶保护的源漏金属薄膜90和透明导电薄膜120b，形成漏极10、源极9及其相连的数据线。其中，所述源极9由位于源极区域的源漏金属薄膜9a和透明导电薄膜12a构成，所述漏极10由位于漏极区域的源漏金属薄膜9b和透明导电薄膜12b构成，所述数据线由位于数据线区域的源漏金属薄膜和透明导电薄膜构成，其中，金属刻蚀工艺可以是湿法腐蚀，或者干法腐蚀如电感耦合等离子体刻蚀，使用湿法腐蚀刻蚀氧化物透明导电薄膜。使用等离子体灰化工艺去除较薄的光刻胶5b，保留光刻胶5a作为刻蚀阻挡层，通过等离子体或者电感耦合等离子方法进行源漏金属薄膜90的刻蚀，去除像素区域覆盖的源漏金属薄膜90，形成像素电极12。
第四次构图工艺：
最后，采用与顶发射AMOLED的低温多晶硅阵列相同的工艺和材料，形成像素定义层，完成底发射AMOLED的低温多晶硅阵列基板。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (10)

  1. 一种阵列基板的制造方法，包括：
    通过一次构图工艺在基板上形成有源层、栅极绝缘层、栅极和栅线的图案；
    在形成有所述有源层、栅极绝缘层、栅极和栅线的基板上形成钝化层，并通过一次构图工艺在所述钝化层上形成过孔；
    通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源极、漏极及像素电极的图案，所述漏极通过所述过孔与所述有源层接触。
  2. 根据权利要求1所述的阵列基板的制造方法，其中，所述通过一次构图工艺在基板上形成有源层、栅极绝缘层、栅极和栅线的图案的步骤具体包括：
    依次形成多晶硅薄膜、栅极绝缘薄膜及栅金属薄膜；
    在所述栅金属薄膜上涂覆光刻胶；
    采用半透式掩膜版对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域以及光刻胶去除区域，其中，所述光刻胶全保留区域对应栅极和栅线区域，所述光刻胶半保留区域对应有源层的源漏接触区域，所述光刻胶去除区域对应除所述光刻胶全保留区域及所述光刻胶半保留区域之外的其他区域；
    采用刻蚀工艺去除所述光刻胶去除区域的多晶硅薄膜、栅极绝缘薄膜及栅金属薄膜，形成栅极绝缘层和有源层的图案；
    利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
    利用刻蚀工艺去除所述光刻胶半保留区域的栅金属薄膜，形成栅极及栅线的图案；
    剥离所述光刻胶全保留区域的光刻胶。
  3. 根据权利要求1或2所述的阵列基板的制造方法，其中，所述阵列基板为顶发射型，所述通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源极、漏极及像素电极的图案的步骤包括：
    依次形成源漏金属薄膜和透明导电薄膜；
    在所述透明导电薄膜上涂覆光刻胶；
    对所述透明导电薄膜上的光刻胶进行曝光、显影后，形成对应源极区域、漏极区域、数据线区域及像素电极区域的光刻胶保留区域及除所述光刻胶保留区域之外的光刻胶去除区域；
    采用刻蚀工艺去除所述光刻胶去除区域的源漏极金属薄膜以及透明导电薄膜，形成源极、漏极、数据线及像素电极的图案；其中，所述源极由位于所述源极区域的源漏金属薄膜及透明导电薄膜组成，所述漏极由位于所述漏极区域的源漏金属薄膜及透明导电薄膜组成，所述数据线由位于所述数据线区域的源漏金属薄膜及透明导电薄膜组成；
    剥离所述光刻胶保留区域的光刻胶。
  4. 根据权利要求1或2所述的阵列基板的制造方法，其中，所述阵列基板为底发射型，所述通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源极、漏极及像素电极的图案的步骤包括：
    依次形成透明导电薄膜和源漏金属薄膜；
    在所述源漏金属薄膜上涂覆光刻胶；
    采用半透式掩膜版对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域以及光刻胶去除区域，其中，所述光刻胶全保留区域对应源极区域、漏极区域和数据线区域，所述光刻胶半保留区域对应像素电极区域，所述光刻胶去除区域对应除所述光刻胶全保留区域及所述光刻胶半保留区域之外的其他区域；
    采用刻蚀工艺去除所述光刻胶去除区域的源漏金属薄膜和透明导电薄膜，形成源极、漏极和数据线的图案，其中，所述源极由位于所述源极区域的源漏金属薄膜及透明导电薄膜组成，所述漏极由位于所述漏极区域的源漏金属薄膜及透明导电薄膜组成，所述数据线由位于所述数据线区域的源漏金属薄膜及透明导电薄膜组成；
    利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
    利用刻蚀工艺去除所述光刻胶半保留区域的透明导电薄膜，形成像素电极的图案；
    剥离所述光刻胶全保留区域的光刻胶。
  5. 根据权利要求1至4中任一项所述的阵列基板的制造方法，其中，所述通过一次构图工艺在形成有所述钝化层的基板上形成数据线、源极、漏极及像素电极的图案的步骤之后还包括：
    通过一次构图工艺形成像素定义层。
  6. 一种阵列基板，包括：
    基板；
    有源层，位于所述基板之上；
    栅极绝缘层，位于所述有源层之上；
    栅极和栅线，位于所述栅极绝缘层之上；
    钝化层，覆盖所述有源层、栅极绝缘层、栅极及栅线，其上设置有过孔；
    源极、漏极、数据线及像素电极，其中，所述源极由位于源极区域的源漏金属薄膜和透明导电薄膜构成，所述漏极由位于漏极区域的源漏金属薄膜和透明导电薄膜构成，所述数据线由位于数据线区域的源漏金属薄膜和透明导电薄膜构成，所述像素电极为位于像素电极区域的透明导电薄膜，所述漏极通过所述过孔与所述有源层接触。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板为顶发射型，所述源漏金属薄膜位于透明导电薄膜之下，所述漏极通过位于所述漏极区域的源漏金属薄膜并借助所述过孔与所述有源层接触。
  8. 根据权利要求6所述的阵列基板，其中，所述阵列基板为底发射型，所述源漏金属薄膜位于透明导电薄膜之上，所述漏极通过位于所述漏极区域的透明导电薄膜并借助所述过孔与所述有源层接触。
  9. 根据权利要求6所述的阵列基板，其中，还包括：
    像素定义层。
  10. 一种显示装置，包括如权利要求6-9任一项所述的阵列基板。
PCT/CN2014/088530 2014-06-24 2014-10-14 一种阵列基板的制造方法、阵列基板及显示装置 WO2015196633A1 (zh)

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