WO2020042834A1 - 静电放电保护电路、显示面板及显示装置 - Google Patents

静电放电保护电路、显示面板及显示装置 Download PDF

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Publication number
WO2020042834A1
WO2020042834A1 PCT/CN2019/097230 CN2019097230W WO2020042834A1 WO 2020042834 A1 WO2020042834 A1 WO 2020042834A1 CN 2019097230 W CN2019097230 W CN 2019097230W WO 2020042834 A1 WO2020042834 A1 WO 2020042834A1
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Prior art keywords
thin film
film transistor
line
protected
signal line
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PCT/CN2019/097230
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English (en)
French (fr)
Inventor
龙春平
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京东方科技集团股份有限公司
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Priority to EP19853266.5A priority Critical patent/EP3846206A4/en
Priority to US16/638,549 priority patent/US11502112B2/en
Publication of WO2020042834A1 publication Critical patent/WO2020042834A1/zh
Priority to US17/889,528 priority patent/US11837609B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the technical field of display product manufacturing, and in particular, to an electrostatic discharge protection circuit, a display panel, and a display device.
  • Display devices have been widely used as display screens for consumer electronics products such as mobile phones, notebook computers, personal computers, and personal digital assistants.
  • the display device generally includes an active matrix array substrate and a color filter substrate, or an upper substrate.
  • electrostatic deposition is easily generated due to processes such as plasma deposition, etching, and friction, or static electricity is generated during use, resulting in electrostatic breakdown and electrostatic damage on the array substrate, resulting in defects.
  • Electro-Static Discharge (ESD) protection circuits are distributed around the panel, which is an important part of the display device. It can ensure that the display device is protected from static electricity during production, transportation and work.
  • the thin film transistor in the ESD structure is generally designed with a longer channel and a lower channel width-to-length ratio to enhance the ESD resistance.
  • the channel direction of the thin film transistor is generally the direction of extension of the data line or gate line. Vertically, the space for thin film transistors is limited, which limits the length of the channel and naturally limits the resistance of ESD.
  • the present disclosure provides an electrostatic discharge protection circuit, a display panel, and a display device.
  • an electrostatic discharge protection circuit including a thin film transistor, the thin film transistor is disposed between a signal line to be protected and a discharge line providing protection, and a channel of the thin film transistor The length direction is parallel to the extending direction of the signal line to be protected.
  • the channel width-to-length ratio of the thin film transistor is less than 0.2.
  • the signal line to be protected is a data line or a gate line.
  • the thin film transistor includes a first thin film transistor and a second thin film transistor
  • the discharge line includes a first discharge line and a second discharge line
  • a drain of the first thin film transistor is electrically connected to the first discharge line, and a source and a gate of the first thin film transistor are electrically connected to a signal line to be protected;
  • a drain of the second thin film transistor is electrically connected to a signal line to be protected, and a source and a gate of the second thin film transistor are electrically connected to the second discharge line.
  • first discharge line and the second discharge line are short-circuited by a connection line.
  • first discharge line and the second discharge line are arranged to intersect the signal line to be protected, and the first thin film transistor and the second thin film transistor are provided to the first discharge line and the first discharge line. Between two discharge lines.
  • first to-be-protected signal line and the second to-be-protected signal line are arranged adjacent to each other in a side-by-side or side-by-side signal line, and the first to-be-protected signal line is connected to the first discharge line and the first through a thin film transistor.
  • Two discharge lines, the second signal line to be protected is connected to a third discharge line and a fourth discharge line through a thin film transistor, the first discharge line, the second discharge line, the third discharge line, the The fourth discharge line is short-circuited by a connecting line, wherein the second discharge line and the third discharge line are the same line.
  • a thin film transistor connected to the first to-be-protected signal line and a thin film transistor connected to the second to-be-protected signal line are arranged in columns along an extending direction of the to-be-protected signal line.
  • the thin film transistor includes a first thin film transistor and a second thin film transistor
  • the discharge line includes a fifth discharge line
  • the gate and source of the first thin film transistor are electrically connected to the signal line to be protected, the drain of the first thin film transistor is electrically connected to the gate and source of the second thin film transistor, and the second thin film The drain of the transistor is electrically connected to the signal line to be protected, and the gate of the second thin film transistor is electrically connected to the fifth discharge line.
  • first to-be-protected signal line and the second-to-be-protected signal line are adjacent to each other in the side-by-side or side-by-side to-be-protected signal lines, and two sides of the fifth discharge line are respectively provided to the first A thin film transistor electrically connected to the protection signal line and a thin film transistor electrically connected to the second signal line to be protected.
  • a thin film transistor connected to the first to-be-protected signal line and a thin film transistor connected to the second to-be-protected signal line are arranged in columns along an extending direction of the to-be-protected signal line.
  • the active layer of the thin film transistor is made of an oxide semiconductor, amorphous silicon, or low temperature polysilicon.
  • an insulating film is disposed on a channel of the thin film transistor.
  • the present disclosure provides a display panel including the above-mentioned electrostatic discharge protection circuit.
  • the display panel further includes the signal line to be protected and the discharge line.
  • the present disclosure provides a display device including the above-mentioned display panel.
  • FIG. 1 shows a schematic diagram of an ESD circuit in the present disclosure
  • FIG. 2 is a schematic diagram of an ESD wiring structure in some embodiments of the present disclosure
  • FIG. 3 is a schematic diagram of another ESD wiring structure in some embodiments of the present disclosure.
  • FIG. 4 shows a first schematic view of a structure of a first thin film transistor in some embodiments of the present disclosure
  • FIG. 5 shows a second schematic diagram of a structure of a first thin film transistor in some embodiments of the present disclosure
  • FIG. 6 is a schematic cross-sectional view of a thin film transistor in some embodiments of the present disclosure.
  • the channel direction of the current TFT is perpendicular to the extension direction of the data line or gate line.
  • the space between the data lines or the gate lines is limited, so the length of the channel of the TFT is limited, the width-to-length ratio of the TFT is limited, and the ESD resistance cannot be improved.
  • this embodiment provides an electrostatic discharge protection circuit including a thin film transistor 03, which is disposed between a signal line 01 to be protected and a discharge line 02 providing protection, and a trench of the thin film transistor 03.
  • the track length direction is parallel to the extending direction of the signal line 01 to be protected.
  • the channel refers to a thin semiconductor layer between a source and a drain of a TFT.
  • FIG. 1 is a schematic diagram of an ESD circuit of the present disclosure
  • FIG. 2 and FIG. 3 respectively show ESD wiring diagrams in this embodiment.
  • the channel length direction of the thin film transistor is parallel to the extending direction of the signal line to be protected.
  • the length of the channel of the thin film transistor is reduced to reduce the width-to-length ratio of the channel of the thin film transistor, thereby enhancing the ESD resistance.
  • the ESD wiring structure is not limited to the wiring structure shown in FIG. 2 and FIG. 3, as long as the channel length direction of the thin film transistor of the ESD circuit is parallel to the extending direction of the signal line to be protected.
  • the channel width-to-length ratio of the thin film transistor is less than 0.2, which effectively enhances the ESD resistance.
  • the signal line to be protected is a data line or a gate line.
  • the thin film transistor includes a first thin film transistor and a second thin film transistor
  • the discharge circuit includes a first discharge line and a second discharge line.
  • a drain of the first thin film transistor is electrically connected to the first discharge line, and a source and a gate of the first thin film transistor are electrically connected to a signal line to be protected;
  • a drain of the second thin film transistor is electrically connected to a signal line to be protected, and a source and a gate of the second thin film transistor are electrically connected to the second discharge line.
  • the first discharge line and the second discharge line are short-circuited by a connection line. Ensure that the voltages of the first discharge line and the second discharge line are consistent.
  • the first discharge line and the second discharge line are disposed to intersect the signal line to be protected, and the first thin film transistor and the second thin film transistor are disposed on the first discharge line and the Said between the second discharge lines.
  • the extension direction of the first discharge line and the second discharge line is perpendicular to the extension direction of the signal line to be protected.
  • the first to-be-protected signal line and the second-to-be-protected signal line are arranged adjacent to each other in a side-by-side or side-by-side signal line, and the first to-be-protected signal line is connected to a first discharge line through a thin film transistor.
  • a second discharge line, the second to-be-protected signal line is connected to a third discharge line and a fourth discharge line through a thin film transistor, the first discharge line, the second discharge line, the third discharge line, The fourth discharge line is short-circuited by a connection line, wherein the second discharge line and the third discharge line are the same line.
  • the thin film transistor connected to the first signal line to be protected and the thin film transistor connected to the second signal line to be protected are lined up along the extending direction of the signal line to be protected. Settings. The space occupied by the thin film transistor is reduced in a direction perpendicular to the extending direction of the signal line to be protected.
  • the connection line (short connection 4) shorted by the fourth discharge line 3 is formed in the same layer as the gate of the thin film transistor.
  • a first thin film transistor and a second thin film transistor are disposed between the first discharge line 1, the second discharge line (the third discharge line) 2, and the first to-be-protected signal line 5, and the second discharge line (the third discharge line) 2.
  • a third thin film transistor and a fourth thin film transistor are disposed between the fourth discharge line 3 and the second signal line 6 to be protected, and the first signal line 5 to be protected and the second signal line 6 to be protected are disposed adjacently.
  • the second discharge line and the third discharge line are the same line.
  • the first end of the second connection line 20 is connected to the first signal line 5 to be protected, one end of the first connection line 12 is connected to the first discharge line 1 through the first via 11, and the other end of the first connection line 12 is connected through the first
  • the two vias 13 are connected to the first active layer 15 to form the drain of the first thin film transistor; the second end of the second connection line 20 is connected to the first active layer 15 through the third via 16 to form the first thin film transistor.
  • the source, the second end of the second connection line 20 is connected to the first gate electrode 14 of the first thin film transistor through the fourth via 17; the third end of the second connection line 20 is connected to the second through the fifth via 21
  • the active layer 23 forms the drain of the second thin film transistor; one end of the third connection line 25 is connected to the second active layer 23 through the sixth via 24 to form the source of the second thin film transistor.
  • One end is connected to the second discharge line 2 through the seventh via 26; wherein the gate electrode 22 of the second thin film transistor is directly connected to the second discharge line (third discharge line) 2.
  • the ESD circuit of the first to-be-protected signal line 5 includes a first thin film transistor and a second thin film transistor.
  • the first end of the fourth connection line 40 is connected to the second signal line 6 to be protected, and the third connection line 25 is connected to the third active layer 33 through the eighth via 31 to form the source of the third thin film transistor; the fourth connection The second end of the line 40 is connected to the third active layer 33 through the ninth via 34 to form the drain of the third thin film transistor; the third gate 32 and the second discharge line (third discharge line) of the third thin film transistor.
  • the third end of the fourth connection line 40 is connected to the fourth gate 43 of the fourth thin film transistor through the tenth via 41, and the third end of the fourth connection line 40 is connected to the eleventh via 42
  • the fourth active layer 44 forms the source of the fourth thin film transistor
  • the fifth connection line 46 is connected to the fourth active layer 44 through the twelfth via 45 to form the drain of the fourth thin film transistor, and the fifth connection line 46 passes through
  • the thirteenth via hole 47 is connected to the fourth discharge line 3;
  • the ESD circuit of the second to-be-protected signal line 6 includes a third thin film transistor and a fourth thin film transistor.
  • the thin film transistor includes a first thin film transistor and a second thin film transistor, and the discharge line includes a fifth discharge line.
  • the gate and source of the first thin film transistor are electrically connected to the signal line to be protected, the drain of the first thin film transistor is electrically connected to the gate and source of the second thin film transistor, and the second thin film The drain of the transistor is electrically connected to the signal line to be protected, and the gate of the second thin film transistor is electrically connected to the fifth discharge line.
  • the first to-be-protected signal line and the second-to-be-protected signal line are adjacent to each other in the side-by-side or side-by-side to-be-protected signal lines, and two sides of the fifth discharge line are respectively provided with the first A thin film transistor electrically connected to the signal line to be protected and a thin film transistor electrically connected to the second signal line to be protected.
  • the thin film transistor connected to the first signal line to be protected and the thin film transistor connected to the second signal line to be protected are lined up along the extending direction of the signal line to be protected. Settings. The space occupied by the thin film transistor is reduced in a direction perpendicular to the extending direction of the signal line to be protected.
  • one end of the sixth connection line 200 is connected to the third signal line 100 to be protected, and the other end of the sixth connection line 200 is connected to the gate 500 of the fifth thin film transistor through the fourteenth via hole 300, and The other end of the sixth connection line 200 is connected to the fifth thin film transistor active layer 600 through the fifteenth via hole 400 to form the source of the fifth thin film transistor; one end of the seventh connection line 800 is connected through the sixteenth via hole 700.
  • the active layer 600 to the fifth thin film transistor forms the drain of the fifth thin film transistor
  • the other end of the seventh connection line 800 is connected to the gate 1001 of the sixth thin film transistor through the seventeenth via 900 and the seventh connection line 800
  • the other end is connected to the sixth thin film transistor active layer 1002 through the eighteenth via 1000 to form the source of the sixth thin film transistor; one end of the eighth connection line 1003 is connected to the third signal line 100 to be protected, and the eighth connection
  • the other end of the line 1003 is connected to the active layer 1002 of the sixth thin film transistor through the nineteenth via 1004 to form the drain of the sixth thin film transistor, and the gate 1001 of the sixth thin film transistor is connected to the fifth discharge line 2000.
  • the active layer of the thin film transistor is made of an oxide semiconductor, but other semiconductor materials such as amorphous silicon, low temperature polysilicon, etc. may also be used.
  • an insulating film is disposed on a portion of the active layer of the thin film transistor corresponding to a gap between a source and a drain.
  • the thin film transistor includes a source S, a drain D, and a gate G.
  • An insulating film is provided on a channel of the thin film transistor, and the insulating film can be used as an etch barrier layer or a channel.
  • the protective layer is provided on a portion of the active layer of the thin film transistor corresponding to a gap between a source and a drain.
  • connection relationship between the source and the drain, the setting position, and the like in the above embodiments are all interchangeable and can be set according to actual needs.
  • the bottom-gate structure TFT is taken as an example to introduce the TFT structure and manufacturing process in this embodiment, as shown in FIG. 4.
  • a gate metal thin film on a transparent substrate Forming a gate metal thin film on a transparent substrate, and forming a gate pattern through a photolithography process using a mask, including a gate line 81 and a gate electrode 84 and a gate protrusion 87 forming a storage capacitor;
  • a gate insulating film Continuously and sequentially form a gate insulating film, a semiconductor layer (including an intrinsic semiconductor film and a doped semiconductor film) and a source-drain metal film, and use a GrayTone mask to define a stepped photoresist pattern and a TFT channel
  • the upper photoresist (GrayTone photoresist is partially retained) is thinner than the photoresist on the source and drain electrodes and the data line (FullTone photoresist is fully retained).
  • the source electrode 83, the drain electrode 85, and the data line 82 are formed by an etching process. After completely removing the photoresist in the photoresist partially-retained area (GrayTone), the source-drain metal film and the doped semiconductor film are continuously etched to form a TFT conductive channel;
  • a layer of transparent conductive film is formed on the passivation protective film, and the pixel electrode 86 is formed by a mask plate.
  • the gate metal film and the source-drain metal film are prepared by the same or similar methods, such as magnetron sputtering, evaporation, etc. They use similar low-resistance metal materials, such as molybdenum, aluminum, aluminum-nickel alloy, and chromium. Or copper.
  • the gate metal film may be a single-layer metal film such as Al, Cu, Mo, Ti, or AlNd, or may be a multi-layer metal film such as Mo / Al / Mo or Ti / Al / Ti.
  • the gate insulating film, the intrinsic semiconductor film, and the doped semiconductor film can be continuously formed on the same equipment by the same method.
  • the gate insulating film usually uses materials such as silicon oxide, silicon nitride, and silicon oxynitride, and the intrinsic semiconductor layer and the doped semiconductor film use materials such as amorphous silicon, microcrystalline silicon, and polysilicon.
  • etching liquids and etching gases need to be used to ensure that the selection ratio of different materials, slope angle (Profile), and critical dimension (CD) control are achieved.
  • the gate insulating dielectric layer, the intrinsic semiconductor film, and the doped semiconductor film can be removed using a similar method, that is, plasma etching or reactive ion etching.
  • plasma etching or reactive ion etching By adjusting the etching gas and etching conditions, the three layers of film can be etched in the same equipment.
  • the above-mentioned different films can be etched in the same equipment.
  • sulfur hexafluoride, chlorine and helium etch semiconductor films sulfur hexafluoride, oxygen and helium etch insulating films; chlorine and oxygen etch metal films.
  • the corrosion conditions of different films such as plasma power, air pressure, and electrode spacing, are different.
  • the corrosion of semiconductor thin films is generally performed in a plasma chamber with a lower pressure and a higher power, and has a stronger effect of ion bombardment and sputtering corrosion.
  • Insulating films and metal films are generally in a higher pressure and a lower power plasma chamber. It is carried out in the chamber and has a strong chemical reaction ion corrosion effect. For example, if you pass tens of sccm of sulfur hexafluoride and thousands of sccm of chlorine gas to the device, the semiconductor film can be efficiently removed by etching at a power of more than several kilowatts and a pressure of several tens of millitorr. Sulfur fluoride and hundreds of sccm of chlorine gas can be efficiently etched to remove insulating films under several kilowatts of power and hundreds of millitorr pressure.
  • the source and drain metal materials can be removed by chemical etching solution etching according to the source and drain metal materials. Plasma etching or reactive ion etching can also be used. Methods. For example, if hundreds to thousands of sccm of chlorine gas and thousands of sccm of oxygen gas are passed into the dry etching equipment, the metal film can be efficiently etched and removed under thousands of power and hundreds of millitorr pressure.
  • the method of plasma etching or reactive ion etching and the conditions described above are used to source and drain in the same device.
  • the metal thin film and the doped semiconductor layer are continuously etched and removed. Wet etching is only used for the removal of metal thin films.
  • a mixed solution of nitric acid, hydrochloric acid and acetic acid in a certain concentration ratio is used for immersion and spraying at a temperature of tens of degrees.
  • top-gate TFT The structure and manufacturing process of the top-gate TFT are described below, as shown in FIG. 5.
  • a silicon nitride (SiN) film and a silicon dioxide (SiO2) film are sequentially deposited on the entire insulating substrate 94 to form a buffer layer 95 composed of silicon nitride and silicon dioxide.
  • an amorphous silicon (a-Si) film is formed on the buffer layer 95 by using PECVD or other chemical or physical vapor deposition methods.
  • the laser annealing (ELA) or solid phase crystallization (SPC) method is used to make the a-Si crystal into a polysilicon film.
  • a photoresist layer pattern is formed on the polysilicon film by using a mask process in the related art.
  • the photoresist layer is used as an etching barrier layer, and the polysilicon film not protected by the photoresist layer is etched by plasma to form polysilicon An active layer 904 and a polysilicon storage capacitor.
  • a low-concentration ion doping is performed on the transistor channel in the polysilicon active layer 904 by using an ion implantation process to form a conductive channel required by the thin film transistor in the polysilicon active layer 904.
  • a photoresist composed of a photoresist material is formed on the polysilicon active layer 904 through a mask process to protect the polysilicon active layer 904 from ion implantation.
  • a high-concentration ion implantation process is performed on the polysilicon storage capacitor without the protection of the photoresist layer to convert the polysilicon storage capacitor into a low-resistance doped polysilicon film.
  • the photoresist on the polysilicon active layer 904 is removed by a photoresist stripping process, and a SiO2 film or a composite film of SiO2 and SiN is deposited using PECVD to form a gate on the polysilicon storage capacitor, the polysilicon active layer 904, and the entire buffer layer 95.
  • Insulation layer 96 One or more low-resistance metal material films are deposited on the gate insulating layer 96 by a physical vapor deposition method such as magnetron sputtering, and the gate 92 is formed by a photolithography process.
  • the gate metal film may be a single-layer metal film such as Al, Cu, Mo, Ti, or AlNd, or may be a multi-layer metal film such as Mo / Al / Mo or Ti / Al / Ti.
  • the gate electrode 92 is used as an ion implantation blocking layer, and the polysilicon active layer 904 is ion-doped to form a low-impedance source electrode and drain electrode contact region in a region of the polysilicon active layer that is not blocked by the gate.
  • a SiO2 film and a SiN film are sequentially deposited using PECVD to form an interlayer insulating layer 93.
  • the interlayer insulating layer 93 is etched through a mask and an etching process to form source and drain electrode contact holes.
  • the source electrode 902 and the drain electrode 97 are formed by a mask and an etching process.
  • the electrode 902 and the drain electrode 97 form an ohmic contact with the polysilicon active layer 904 through a contact hole.
  • the source-drain metal thin film may be a single-layer metal thin film such as Al, Cu, Mo, Ti, or AlNd, or may be a multilayer metal thin film such as Mo / Al / Mo or Ti / Al / Ti.
  • a layer of SiN film is deposited on the entire surface including the source electrode 902 and the drain electrode 97 using PECVD, and a passivation layer 901 including a via is formed by a mask and an etching process.
  • the rapid thermal annealing or heat treatment furnace annealing is used to perform the hydrogenation process to repair defects in the interior and interface of the polysilicon active layer 904.
  • an organic planarization layer having the same vias as the vias is formed on the SiN passivation layer 901, and the depressions on the surface of the device are filled to form a flat surface.
  • a magnetron sputtering is used to deposit a transparent conductive film on the organic planarization layer and the via hole, and the transparent conductive film is etched by a photolithography process to form a pixel electrode 98 of a pixel region on the via hole and a part of the organic planarization layer. Then, a layer of a photosensitive organic material similar to the organic planarization layer is coated on the organic planarization layer and the pixel electrode 98, and a part of the pixel electrode 98 is exposed through the last mask process to form the pixel shown in FIG. 5
  • the definition layer 99, the pixel definition layer 99 covers the organic planarization layer and a part of the pixel electrode 98 area.
  • the transparent conductive film may be a single-layer oxide conductive film, such as ITO (indium tin oxide) or IZO (indium zinc oxide), etc., or it may be ITO (indium tin oxide) / Ag / ITO, IZO (indium zinc oxide). / Ag and other composite films.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • lithography processes are required to form the low-temperature polysilicon thin film field effect transistor array substrate shown in FIG. 5, including the realization of a polysilicon active layer, storage capacitor doping, gate, and interlayer through a photolithography process. Insulating layer contact holes, source and drain electrodes, passivation layer vias, planarization layers, pixel electrodes.
  • the present disclosure provides a display panel including the above-mentioned electrostatic discharge protection circuit.
  • the display panel further includes the signal line to be protected and the discharge line.
  • the present disclosure provides a display device including the display panel.

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Abstract

一种静电放电保护电路及包括该静电放电保护电路的显示面板和显示装置，该静电放电保护电路包括薄膜晶体管(03)，所述薄膜晶体管(03)设置于待保护信号线(01)与放电线路(02)之间，所述薄膜晶体管(03)的沟道长度方向与待保护信号线(01)的延伸方向平行。

Description

静电放电保护电路、显示面板及显示装置
相关申请的交叉引用
本申请主张在2018年8月30日在中国提交的中国专利申请No.201821413041.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示产品制作技术领域，尤其涉及一种静电放电保护电路、显示面板及显示装置。
背景技术
显示装置已被大量地用作于手机、笔记本电脑、个人电脑及个人数字助理等消费电子产品的显示屏幕。显示装置一般包括有源矩阵阵列基板和彩膜基板，或者上基板。在阵列基板制造过程，由于等离子体沉积、刻蚀和摩擦等工艺容易产生静电积累，或者在使用过程中产生静电，导致在阵列基板上发生静电击穿和静电损伤，产生不良。
静电放电(Electro-Static Discharge，ESD)保护电路分布于面板(Panel)的四周，是显示装置的重要组成部分，可以保证显示装置在生产、运输及工作过程中免受静电伤害。ESD结构内的薄膜晶体管一般设计成较长的沟道和较低的沟道宽长比，以增强ESD的抵抗能力，但是，薄膜晶体管的沟道方向一般是与数据线或栅线的延伸方向垂直，设置薄膜晶体管的空间有限，限制了沟道的长度，自然限制了ESD的抵抗能力。
发明内容
本公开提供一种静电放电保护电路、显示面板及显示装置。
为了达到上述目的，本公开采用的技术方案是：一种静电放电保护电路，包括薄膜晶体管，所述薄膜晶体管设置于待保护信号线与提供保护的放电线路之间，所述薄膜晶体管的沟道长度方向与待保护信号线的延伸方向平行。
进一步地，所述薄膜晶体管的沟道宽长比小于0.2。
进一步地，待保护信号线为数据线或栅线。
进一步地，所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述放电线路包括第一放电线和第二放电线，
所述第一薄膜晶体管的漏极与所述第一放电线电连接，所述第一薄膜晶体管的源极和栅极与待保护信号线电连接；
所述第二薄膜晶体管的漏极与待保护信号线电连接，所述第二薄膜晶体管的源极和栅极与所述第二放电线电连接。
进一步地，所述第一放电线和所述第二放电线之间通过一连接线短接。
进一步地，所述第一放电线和所述第二放电线与待保护信号线相交设置，且所述第一薄膜晶体管和所述第二薄膜晶体管设置于所述第一放电线和所述第二放电线之间。
进一步地，并排或并列设置的待保护信号线中具有相邻的第一待保护信号线和第二待保护信号线，所述第一待保护信号线通过薄膜晶体管连接有第一放电线和第二放电线，所述第二待保护信号线通过薄膜晶体管连接有第三放电线和第四放电线，所述第一放电线、所述第二放电线、所述第三放电线、所述第四放电线通过一连接线短接，其中，所述第二放电线与第三放电线为同一线路。
进一步地，与所述第一待保护信号线连接的薄膜晶体管、和与所述第二待保护信号线连接的薄膜晶体管沿着所述待保护信号线的延伸方向成列向设置。
进一步地，所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述放电线路包括第五放电线，
所述第一薄膜晶体管的栅极和源极与待保护信号线电连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的栅极和源极电连接，所述第二薄膜晶体管的漏极与待保护信号线电连接，所述第二薄膜晶体管的栅极与所述第五放电线电连接。
进一步地，所述并排或并列设置的待保护信号线中具有相邻的第一待保护信号线和第二待保护信号线，所述第五放电线的两侧分别设置与所述第一待保护信号线电连接的薄膜晶体管和与所述第二待保护信号线电连接的薄膜 晶体管。
进一步地，与所述第一待保护信号线连接的薄膜晶体管、和与所述第二待保护信号线连接的薄膜晶体管沿着所述待保护信号线的延伸方向成列向设置。
进一步地，所述薄膜晶体管的有源层采用氧化物半导体、非晶硅、或低温多晶硅制成。
进一步地，所述薄膜晶体管的沟道上设置有绝缘薄膜。
本公开提供一种显示面板，包括上述的静电放电保护电路。
进一步地，所述显示面板还包括所述待保护信号线和所述放电线路。
本公开提供一种显示装置，包括上述的显示面板。
附图说明
图1表示本公开中ESD电路原理示意图；
图2表示本公开一些实施例中的一种ESD布线结构示意图；
图3表示本公开一些实施例中的另一种ESD布线结构示意图；
图4表示本公开一些实施例中的第一薄膜晶体管的结构示意图一；
图5表示本公开一些实施例中的第一薄膜晶体管的结构示意图二；
图6表示本公开一些实施例中的薄膜晶体管的截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
一般情况下，TFT(薄膜晶体管)的沟道的宽长比越低，ESD的抵抗能力越强，但是目前的TFT的沟道方向与数据线或者栅线的延伸方向相垂直设置，相邻两条数据线或栅线之间的空间是有限的，所以限制了TFT的沟道的长度，也就限制了TFT的宽长比，ESD的抵抗能力也就无法提高。
针对上述问题，本实施例提供了一种静电放电保护电路，包括薄膜晶体管03，所述薄膜晶体管03设置于待保护信号线01与提供保护的放电线路02之间，所述薄膜晶体管03的沟道长度方向与待保护信号线01的延伸方向平行。在一个实施例中，所述沟道指的是TFT的源极和漏极之间的一薄半导体层。
图1为本公开ESD电路原理示意图，如图2和图3分别表示本实施例中的ESD布线示意图，所述薄膜晶体管的沟道长度方向与待保护信号线的延伸方向平行，可以通过增加所述薄膜晶体管的沟道的长度来降低所述薄膜晶体管的沟道的宽长比，从而增强ESD的抵抗能力。
需要说明的是，ESD布线结构并不限于图2和图3中所示布线结构，只要保证ESD电路的薄膜晶体管的沟道长度方向与待保护信号线的延伸方向平行即可。
本实施例中，所述薄膜晶体管的沟道宽长比小于0.2，有效的增强ESD的抵抗力。
本实施例中，待保护信号线为数据线或栅线。
所述静电放电保护电路的布线结构可以有多种，本实施例中，所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述放电线路包括第一放电线和第二放电线，
所述第一薄膜晶体管的漏极与所述第一放电线电连接，所述第一薄膜晶体管的源极和栅极与待保护信号线电连接；
所述第二薄膜晶体管的漏极与待保护信号线电连接，所述第二薄膜晶体管的源极和栅极与所述第二放电线电连接。
本实施例中，所述第一放电线和所述第二放电线之间通过一连接线短接。保证所述第一放电线与所述第二放电线的电压一致。
本实施例中，所述第一放电线和所述第二放电线与待保护信号线相交设置，且所述第一薄膜晶体管和所述第二薄膜晶体管设置于所述第一放电线和所述第二放电线之间。
为了便于布局，所述第一放电线和所述第二放电线的延伸方向与待保护信号线的延伸方向相垂直。
本实施例中，并排或并列设置的待保护信号线中具有相邻的第一待保护信号线和第二待保护信号线，所述第一待保护信号线通过薄膜晶体管连接有第一放电线和第二放电线，所述第二待保护信号线通过薄膜晶体管连接有第三放电线和第四放电线，所述第一放电线、所述第二放电线、所述第三放电线、所述第四放电线通过一连接线短接，其中，所述第二放电线与第三放电线为同一线路。
进一步地，本实施例中，与所述第一待保护信号线连接的薄膜晶体管、和与所述第二待保护信号线连接的薄膜晶体管沿着所述待保护信号线的延伸方向成列向设置。在与待保护信号线的延伸方向相垂直的方向上减少了薄膜晶体管占用的空间。
在一个实施例中，具体地，如图2所示，第一放电线1、第二放电线(第三放电线)2、第四放电线3以及将第一放电线1、第二放电线(第三放电线)2、第四放电线3短接的连接线(短接线4)均与薄膜晶体管的栅极同层构成。第一连接线12、第二连接线20、第三连接线25、第四连接线40、第五连接线46与待保护信号线(包括第一待保护信号线5和第二待保护信号线6)同层构成。其中，第一放电线1、第二放电线(第三放电线)2、第一待保护信号线5之间设置第一薄膜晶体管和第二薄膜晶体管，第二放电线(第三放电线)2、第四放电线3、第二待保护信号线6之间设置第三薄膜晶体管、第四薄膜晶体管，第一待保护信号线5和第二待保护信号线6相邻设置。所述第二放电线与第三放电线为同一线路。
第二连接线20的第一端连接至第一待保护信号线5，第一连接线12的一端通过第一过孔11连接至第一放电线1，第一连接线12的另一端通过第二过孔13连接至第一有源层15形成第一薄膜晶体管的漏极；第二连接线20的第二端通过第三过孔16连接至第一有源层15形成第一薄膜晶体管的源极，第二连接线20的第二端通过第四过孔17连接至第一薄膜晶体管的第一栅极14；第二连接线20的第三端通过第五过孔21连接至第二有源层23形成第二薄膜晶体管的漏极；第三连接线25的一端通过第六过孔24连接至第二有源层23形成第二薄膜晶体管的源极，第三连接线25的另一端通过第七过孔26连接至第二放电线2；其中第二薄膜晶体管的栅极22直接和第二放电线(第 三放电线)2连接。第一待保护信号线5的ESD电路包括第一薄膜晶体管和第二薄膜晶体管。
第四连接线40的第一端连接至第二待保护信号线6，第三连接线25通过第八过孔31连接至第三有源层33形成第三薄膜晶体管的源极；第四连接线40的第二端通过第九过孔34连接至第三有源层33形成第三薄膜晶体管的漏极；第三薄膜晶体管的第三栅极32和第二放电线(第三放电线)2直接连接；第四连接线40的第三端通过第十过孔41连接至第四薄膜晶体管的第四栅极43，第四连接线40的第三端通过第十一过孔42连接至第四有源层44形成第四薄膜晶体管的源极；第五连接线46通过第十二过孔45连接至第四有源层44形成第四薄膜晶体管的漏极，第五连接线46通过第十三过孔47连接至第四放电线3；第二待保护信号线6的ESD电路包括第三薄膜晶体管和第四薄膜晶体管。
在另一实施例中，如图3所示，所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述放电线路包括第五放电线。
所述第一薄膜晶体管的栅极和源极与待保护信号线电连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的栅极和源极电连接，所述第二薄膜晶体管的漏极与待保护信号线电连接，所述第二薄膜晶体管的栅极与所述第五放电线电连接。
本实施例中，所述并排或并列设置的待保护信号线中具有相邻的第一待保护信号线和第二待保护信号线，所述第五放电线的两侧分别设置与所述第一待保护信号线电连接的薄膜晶体管和与所述第二待保护信号线电连接的薄膜晶体管。
进一步地，本实施例中，与所述第一待保护信号线连接的薄膜晶体管、和与所述第二待保护信号线连接的薄膜晶体管沿着所述待保护信号线的延伸方向成列向设置。在与待保护信号线的延伸方向相垂直的方向上减少了薄膜晶体管占用的空间。
如图3所示，第六连接线200的一端与第三待保护信号线100连接，第六连接线200的另一端通过第十四过孔300与第五薄膜晶体管的栅极500连接，且第六连接线200的另一端通过第十五过孔400连接至第五薄膜晶体管 的有源层600形成第五薄膜晶体管的源极；第七连接线800的一端通过第十六过孔700连接至第五薄膜晶体管的有源层600形成第五薄膜晶体管的漏极，第七连接线800的另一端通过第十七过孔900连接至第六薄膜晶体管的栅极1001，第七连接线800的另一端通过第十八过孔1000连接至第六薄膜晶体管的有源层1002形成第六薄膜晶体管的源极；第八连接线1003的一端连接至第三待保护信号线100，第八连接线1003的另一端通过第十九过孔1004连接至第六薄膜晶体管的有源层1002形成第六薄膜晶体管的漏极，第六薄膜晶体管的栅极1001与第五放电线2000连接。
本实施例中，所述薄膜晶体管的有源层采用氧化物半导体制成，但是也可以采用其它半导体材料如非晶硅、低温多晶硅等。
本实施例中，所述薄膜晶体管的有源层对应源极和漏极之间间隙的部分上设置有绝缘薄膜。例如，如图6所示，所述薄膜晶体管包括源极S、漏极D和栅极G，在所述薄膜晶体管的沟道上设置绝缘薄膜，该绝缘薄膜可以做为刻蚀阻挡层或者沟道保护层。
需要说明的是，上述实施例中的源极和漏极的连接关系、设置位置等均是可以互换的，可以根据实际需要设定。
以下以底栅结构的TFT为例介绍本实施例中的TFT结构和制作工艺过程，如图4所示。
在透明衬底上形成一层栅金属薄膜，使用掩膜板通过光刻工艺腐蚀形成栅极图案，包括栅线81和栅电极84以及构成存储电容的栅极凸出部87；
连续、依次形成栅极绝缘薄膜、半导体层(包括本征半导体薄膜和掺杂半导体薄膜)和源漏金属薄膜，使用灰色调(GrayTone)掩膜版，定义台阶状光刻胶图案，TFT沟道上部的光刻胶(GrayTone光刻胶部分保留)薄于源漏电极和数据线上部的光刻胶(FullTone光刻胶完全保留)。通过腐蚀工艺形成源电极83、漏电极85和数据线82。完全去除光刻胶部分保留区域(GrayTone)的光刻胶后，连续腐蚀源漏金属薄膜和掺杂半导体薄膜，形成TFT导电沟道；
形成钝化保护膜，通过掩膜板定义钝化保护膜的图案；
在钝化保护膜上形成一层透明导电薄膜，通过掩膜板形成像素电极86。
在上述制作步骤中，栅金属薄膜和源漏金属薄膜采用相同或类似的方法制备，比如磁控溅射、蒸发等，它们使用类似的低电阻金属材料，比如钼、铝、铝镍合金、铬或铜等。该栅金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。而栅极绝缘薄膜、本征半导体薄膜和掺杂半导体薄膜可以采用相同的方法在相同的设备上连续形成。栅极绝缘薄膜通常使用氧化硅、氮化硅、氮氧化硅等材料，而本征半导体层和掺杂半导体薄膜采用非晶硅、微晶硅、多晶硅等材料。
在上述工艺的腐蚀过程中，需要使用不同的腐蚀方法、腐蚀液和腐蚀气体，保证实现不同材料的选择比、坡度角(Profile)、和关键尺寸(CD)的控制。比如在形成数据线82、源电极83和漏电极85的过程中，栅极绝缘介质层、本征半导体薄膜和掺杂半导体薄膜可以使用类似的方法去除，即等离子刻蚀或反应离子刻蚀，调整刻蚀气体和刻蚀条件，可以在同一设备中实现此三层薄膜的腐蚀。如从六氟化硫、氯气、氧气、氦气等气体中选择不同的腐蚀气体组合和不同的气体流量，即可在同一设备里实现上述不同薄膜的腐蚀。如六氟化硫、氯气和氦气刻蚀半导体薄膜；六氟化硫、氧气和氦气刻蚀绝缘薄膜；氯气和氧气腐蚀金属薄膜。为了达成器件结构的最优化和工艺的高效率，不同薄膜的腐蚀条件如等离子功率、气压、电极间距等有所区别。半导体薄膜的腐蚀一般在较低气压和较大功率的等离子腔室里进行，具有较强的离子轰击和溅射腐蚀的效果；绝缘薄膜和金属薄膜一般在较高气压和稍低功率的等离子腔室里进行，具有较强的化学反应离子腐蚀效果。如向设备通入数十sccm的六氟化硫和数千sccm的氯气，在数千瓦功率以上和数十毫托气压，可以高效刻蚀去除半导体薄膜；如向设备通入数百sccm的六氟化硫和数百sccm的氯气，在数千瓦功率以下和数百毫托气压，可以高效刻蚀去除绝缘薄膜。又比如在形成数据线82、源电极83和漏电极85的过程中，根据源漏金属材料可以采用化学腐蚀液刻蚀的方法去除源漏金属薄膜，也可以采用等离子刻蚀或反应离子刻蚀的方法。如向干法腐蚀设备通入数百至数千sccm的氯气和数千sccm的氧气，在数千功率以下和数百毫托气压，可以高效刻蚀去除金属薄膜。在形成栅线81、栅线凸出部87、存储电容的绝缘介质和TFT沟道时，使用等离子刻蚀或反应离子刻蚀的方法和如前所述的条件，在同一 设备中对源漏金属薄膜和掺杂半导体层进行连续地腐蚀而去除。湿法腐蚀仅用于金属薄膜的去除，一般使用一定浓度比例的硝酸、盐酸和醋酸的混合液，在数十度的温度下通过浸入和喷洒方式进行。
以下介绍顶栅结构的TFT的结构和制作工艺过程，如图5所示。
通过等离子体增强化学气相沉积(PECVD)，在整个绝缘基板94上依次沉积氮化硅(SiN)薄膜和二氧化硅(SiO2)薄膜，形成氮化硅和二氧化硅构成的缓冲层95。接着利用PECVD或者其它化学或物理气相沉积方法在缓冲层95上形成非晶硅(a-Si)薄膜。通过激光退火(ELA)或者固相结晶(SPC)方法，使得a-Si结晶成为多晶硅薄膜。然后采用相关技术中的掩模工艺在多晶硅薄膜上形成光刻胶层的图案，以光刻胶层为刻蚀阻挡层，通过等离子体刻蚀没有被光刻胶层保护的多晶硅薄膜，形成多晶硅有源层904和多晶硅存储电容。利用离子注入工艺对多晶硅有源层904中的晶体管沟道进行低浓度离子掺杂，在多晶硅有源层904中形成薄膜晶体管要求的导电沟道。
通过掩模工艺在多晶硅有源层904上形成光阻材料组成的光刻胶，以保护多晶硅有源层904不被离子注入。对没有光刻胶层保护的多晶硅存储电容进行高浓度离子注入工艺，将多晶硅存储电容转化为低电阻的掺杂多晶硅薄膜。
通过光刻胶剥离工艺去除多晶硅有源层904上的光刻胶，使用PECVD沉积SiO2薄膜或SiO2与SiN的复合薄膜，在多晶硅存储电容、多晶硅有源层904以及整个缓冲层95上形成栅极绝缘层96。通过磁控溅射等物理气相沉积方法在栅极绝缘层96上沉积一种或者多种低电阻的金属材料薄膜，利用光刻工艺形成栅极92。该栅金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。使用栅极92作为离子注入阻挡层，对多晶硅有源层904进行离子掺杂，在未被栅极阻挡的多晶硅有源层区域形成低阻抗的源电极和漏极电极接触区。
在包含栅极92的整个表面，使用PECVD依次沉积SiO2薄膜和SiN薄膜形成层间绝缘层93，通过掩模和刻蚀工艺刻蚀层间绝缘层93而形成源电极和漏电极接触孔。使用磁控溅射在层间绝缘层8及源电极和漏电极接触孔之上沉积一种或多种低电阻的金属薄膜，通过掩模和刻蚀工艺形成源电极902 和漏电极97，源电极902和漏电极97通过接触孔与多晶硅有源层904形成欧姆接触。使用快速热退火或热处理炉退火，激活多晶硅有源层904中掺杂的离子，在栅极92之下的多晶硅有源层904中形成有效的导电沟道。该源漏金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。
使用PECVD在包含源电极902和漏电极97的整个表面沉积一层SiN薄膜，通过掩模和刻蚀工艺形成包含过孔的钝化层901。使用快速热退火或热处理炉退火进行氢化工艺，修复多晶硅有源层904内部和界面的缺陷。再一次通过掩模工艺，在SiN钝化层901之上形成具有与过孔相同的过孔的有机平坦化层，填充器件表面的低凹形成平坦表面。
使用磁控溅射在有机平坦化层和过孔之上沉积一层透明导电薄膜，通过光刻工艺刻蚀该透明导电薄膜在过孔及部分有机平坦化层之上形成像素区域的像素电极98，然后在有机平坦化层及像素电极98上涂覆一层与有机平坦化层类似的光敏有机材料，通过最后一道掩模工艺暴露出像素电极98的部分区域，形成图5中所示的像素定义层99，像素定义层99覆盖有机平坦化层及部分的像素电极98区域。该透明导电薄膜可以是单层的氧化物导电薄膜，如ITO(氧化铟锡)或IZO(氧化铟锌)等，也可以是ITO(氧化铟锡)/Ag/ITO、IZO(氧化铟锌)/Ag等复合薄膜。
综上所述，至少需要8～9道光刻工艺形成图5所示的低温多晶硅薄膜场效应晶体管阵列基板，包括通过光刻工艺实现多晶硅有源层、存储电容掺杂、栅极、层间绝缘层接触孔、源电极和漏电极、钝化层过孔、平坦化层、像素电极。
本公开提供一种显示面板，包括上述的静电放电保护电路。
进一步地，所述显示面板还包括所述待保护信号线和所述放电线路。
本公开提供一种显示装置，包括所述显示面板。
以上所述为本公开较佳实施例，应当指出的是，对于本领域普通技术人员来说，在不脱离本公开的所述原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开保护范围。

Claims (16)

  1. 一种静电放电保护电路，包括薄膜晶体管，所述薄膜晶体管设置于待保护信号线与放电线路之间，所述薄膜晶体管的沟道长度方向与待保护信号线的延伸方向平行。
  2. 根据权利要求1所述的静电放电保护电路，其中，所述薄膜晶体管的沟道宽长比小于0.2。
  3. 根据权利要求2所述的静电放电保护电路，其中，所述待保护信号线为数据线或栅线。
  4. 根据权利要求2所述的静电放电保护电路，其中，所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述放电线路包括第一放电线和第二放电线，
    所述第一薄膜晶体管的漏极与所述第一放电线电连接，所述第一薄膜晶体管的源极和栅极与所述待保护信号线电连接；
    所述第二薄膜晶体管的漏极与待保护信号线电连接，所述第二薄膜晶体管的源极和栅极与所述第二放电线电连接。
  5. 根据权利要求4所述的静电放电保护电路，其中，所述第一放电线和所述第二放电线之间通过一连接线短接。
  6. 根据权利要求4所述的静电放电保护电路，其中，所述第一放电线和所述第二放电线与所述待保护信号线相交设置，且所述第一薄膜晶体管和所述第二薄膜晶体管设置于所述第一放电线和所述第二放电线之间。
  7. 根据权利要求6所述的静电放电保护电路，其中，并排或并列设置的所述待保护信号线中具有相邻的第一待保护信号线和第二待保护信号线，所述第一待保护信号线通过薄膜晶体管连接有第一放电线和第二放电线，所述第二待保护信号线通过薄膜晶体管连接有第三放电线和第四放电线，所述第一放电线、所述第二放电线、所述第三放电线、所述第四放电线通过一连接线短接，其中，所述第二放电线与第三放电线为同一线路。
  8. 根据权利要求7所述的静电放电保护电路，其中，与所述第一待保护信号线连接的薄膜晶体管、和与所述第二待保护信号线连接的薄膜晶体管沿 着所述待保护信号线的延伸方向成列向设置。
  9. 根据权利要求2所述的静电放电保护电路，其中，所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述放电线路包括第五放电线，
    所述第一薄膜晶体管的栅极和源极与待保护信号线电连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的栅极和源极电连接，所述第二薄膜晶体管的漏极与待保护信号线电连接，所述第二薄膜晶体管的栅极与所述第五放电线电连接。
  10. 根据权利要求9所述的静电放电保护电路，其中，所述并排或并列设置的所述待保护信号线中具有相邻的第一待保护信号线和第二待保护信号线，所述第五放电线的两侧分别设置与所述第一待保护信号线电连接的薄膜晶体管和与所述第二待保护信号线电连接的薄膜晶体管。
  11. 根据权利要求10所述的静电放电保护电路，其中，与所述第一待保护信号线连接的薄膜晶体管、和与所述第二待保护信号线连接的薄膜晶体管沿着所述待保护信号线的延伸方向成列向设置。
  12. 根据权利要求1所述的静电放电保护电路，其中，所述薄膜晶体管的有源层采用氧化物半导体、非晶硅、或低温多晶硅制成。
  13. 根据权利要求1所述的静电放电保护电路，其中，所述薄膜晶体管的沟道上设置有绝缘薄膜。
  14. 一种显示面板，包括权利要求1-13任一项所述的静电放电保护电路。
  15. 根据权利要求14所述的显示面板，还包括所述待保护信号线和所述放电线路。
  16. 一种显示装置，包括权利要求14或15所述的显示面板。
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