WO2021003767A1 - 薄膜晶体管基板的制作方法及薄膜晶体管基板 - Google Patents

薄膜晶体管基板的制作方法及薄膜晶体管基板 Download PDF

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WO2021003767A1
WO2021003767A1 PCT/CN2019/096604 CN2019096604W WO2021003767A1 WO 2021003767 A1 WO2021003767 A1 WO 2021003767A1 CN 2019096604 W CN2019096604 W CN 2019096604W WO 2021003767 A1 WO2021003767 A1 WO 2021003767A1
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layer
insulating layer
gate
thin film
film transistor
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PCT/CN2019/096604
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English (en)
French (fr)
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卢马才
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/620,515 priority Critical patent/US11374027B2/en
Publication of WO2021003767A1 publication Critical patent/WO2021003767A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technology, in particular to a method for manufacturing a thin film transistor substrate and a thin film transistor substrate.
  • Thin Film Transistor is the current flat-panel display device such as Liquid Crystal Display (LCD), Organic Light-Emitting Diode (OLED) and Micro LED (Micro LED)
  • the main driving components in the CCD are directly related to the development direction of high-performance flat panel display devices.
  • Thin film transistors have a variety of structures, and there are also a variety of materials for preparing the active layer of thin film transistors with corresponding structures.
  • metal oxide TFTs such as indium gallium zinc oxide (IGZO) thin film transistors, have field High effect mobility ( ⁇ 10cm 2 /V ⁇ s), simple preparation process, good uniformity of large-area deposition, fast response speed and high transmittance in the visible light range. It is considered that the display is moving towards large size and flexibility
  • IGZO indium gallium zinc oxide
  • the traditional bottom-gate structure of metal oxide thin film transistors due to the large overlap area between the gate and the source and drain electrodes, produces a large parasitic capacitance, which will cause signal delay, and the size of the transistor produced by it is large. Limits its application.
  • the top gate self-aligned structure has lower parasitic capacitance and better ductility because there is no overlap between the source and drain electrodes and the gate.
  • top-gate IGZO TFTs As current drive devices, OLEDs and Micro LEDs require greater current passing capacity, better device stability, and uniformity of in-plane voltage (Vth). Similar oxide semiconductor thin film transistors such as top-gate IGZO TFTs have higher mobility and are more suitable for current-driven display circuits. Currently known top gate type IGZO During the manufacturing process of TFT, the surface of IGZO needs to be in contact with photoresist and more organic solvents, which makes the contact surface between the active layer of IGZO and the gate insulating layer more defective, which affects the stability of the device in subsequent operations.
  • the object of the present invention is to provide a method for manufacturing a thin film transistor substrate, by depositing a first insulating layer before patterning the metal oxide semiconductor layer, and using the first insulating layer to protect it, so that the active layer is insulated from the gate The layer contact surface defects are reduced, thereby improving device stability.
  • the object of the present invention is also to provide a thin film transistor substrate, by depositing a first insulating layer before patterning the metal oxide semiconductor layer, and using the first insulating layer to protect it, so that the active layer and the gate insulating layer The contact surface defects are reduced, thereby improving device stability.
  • the present invention provides a method for manufacturing a thin film transistor substrate, which includes the following steps:
  • Step S1 providing a substrate, depositing a buffer layer, a metal oxide semiconductor layer, and a first insulating layer on the substrate in sequence, and patterning the first insulating layer and the metal oxide semiconductor layer according to the active layer pattern; Forming an active layer from the metal oxide semiconductor layer;
  • Step S2 Deposit a second insulating layer and a gate metal layer sequentially on the first insulating layer and the buffer layer, and perform patterning treatment on the gate metal layer, the second insulating layer and the first insulating layer.
  • the gate metal layer forms a gate
  • the first insulating layer and the second insulating layer together form a corresponding gate insulating layer under the gate.
  • the manufacturing method of the thin film transistor substrate further includes:
  • Step S3 depositing an interlayer dielectric layer on the gate, active layer and buffer layer, patterning the interlayer dielectric layer, and forming on the interlayer dielectric layer correspondingly located in the The first via hole and the second via hole above both ends of the active layer;
  • Step S4 depositing a source and drain metal layer on the interlayer dielectric layer, and patterning the source and drain metal layer to obtain the active layer through the first via hole and the second via hole respectively Source and drain in contact at both ends;
  • Step S5 a passivation layer is deposited on the interlayer dielectric layer, the source electrode and the drain electrode, and the passivation layer is patterned to form a second electrode on the passivation layer correspondingly above the drain electrode.
  • the material of the deposited metal oxide semiconductor layer is indium gallium zinc oxide, indium gallium tin oxide, or indium gallium zinc tin oxide.
  • the first insulating layer is patterned by a dry etching method first, and then the remaining first insulating layer is used as a shielding layer, and the metal oxide semiconductor layer is subjected to a wet etching method.
  • the layer is patterned, and an active layer is formed from the metal oxide semiconductor layer.
  • the first insulating layer is formed by a plasma enhanced chemical vapor deposition method.
  • the present invention also provides a thin film transistor substrate including a substrate, a buffer layer provided on the substrate, an active layer provided on the buffer layer, a gate insulating layer provided on the active layer, and corresponding A gate provided on the gate insulating layer;
  • the active layer is formed by patterning a metal oxide semiconductor layer
  • the gate insulating layer is formed by patterning an insulating material film layer, and the insulating material film layer includes a first insulating layer and a second insulating layer;
  • the first insulating layer is deposited and formed on the metal oxide semiconductor layer before patterning to form the active layer;
  • the second insulating layer is deposited and formed on the first insulating layer and the buffer layer after the active layer is patterned.
  • the thin film transistor substrate further includes an interlayer dielectric layer arranged on the gate, active layer and buffer layer, source and drain electrodes arranged on the interlayer dielectric layer, and arranged on the interlayer dielectric layer.
  • the interlayer dielectric layer is provided with a first via hole and a second via hole respectively located above the two ends of the active layer;
  • the source electrode and the drain electrode are in contact with both ends of the active layer through a first via hole and a second via hole respectively;
  • the material of the active layer is indium gallium zinc oxide, indium gallium tin oxide or indium gallium zinc tin oxide.
  • FIG. 1 is a schematic flow diagram of a method for manufacturing a thin film transistor substrate of the present invention
  • Fig. 2-3 is a schematic diagram of step S1 of the method of manufacturing a thin film transistor substrate of the present invention.
  • Figure 4-5 is a schematic diagram of step S2 of the method for manufacturing a thin film transistor substrate of the present invention.
  • 6-7 are schematic diagrams of step S3 of the manufacturing method of the thin film transistor substrate of the present invention.
  • step S4 of the manufacturing method of the thin film transistor substrate of the present invention are schematic diagrams of step S4 of the manufacturing method of the thin film transistor substrate of the present invention.
  • the present invention first provides a method for manufacturing a thin film transistor substrate, including the following steps:
  • Step S1 as shown in FIG. 2-3, a substrate 10 is provided, and a buffer layer 15, a metal oxide semiconductor layer 20, and a first insulating layer 31 are sequentially deposited on the substrate 10, and the first insulating layer 31 and the metal
  • the oxide semiconductor layer 20 is patterned according to the active layer pattern, and the active layer 25 is formed from the metal oxide semiconductor layer 20.
  • the buffer layer 15 deposited on the substrate 10 may be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a stack combination of the two.
  • the material of the deposited first insulating layer 31 may be silicon oxide with a thickness of 100-2000 ⁇ , and the first insulating layer 31 is used as the protection of the metal oxide semiconductor layer 20 in the semiconductor manufacturing process.
  • the layer can prevent the upper surface of the metal oxide semiconductor layer 20 from contacting photoresist, organic solution, acid and alkali.
  • the deposited metal oxide semiconductor layer 20 may be made of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO) or indium gallium zinc tin oxide (IGZTO). And other metal oxide semiconductor materials.
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin oxide
  • IGZTO indium gallium zinc tin oxide
  • the first insulating layer 31 is patterned first by dry etching (Dry Etch), and only the first insulating layer 31 corresponding to the active layer pattern is retained, and then
  • the metal oxide semiconductor layer 20 is patterned by a wet etching method (Wet Etch), and the active layer 25 is formed from the metal oxide semiconductor layer 20.
  • the first insulating layer 31 may be deposited by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition).
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • PVD Physical Vapor Deposition
  • the deposited material of the second insulating layer 32 may be silicon oxide or silicon nitride.
  • the second insulating layer 32 is formed by PECVD, ALD, or PVD deposition.
  • Step S3 As shown in FIGS. 6-7, an interlayer dielectric layer 50 is deposited on the gate 45, the active layer 25, and the buffer layer 15, and the interlayer dielectric layer 50 is patterned.
  • the interlayer dielectric layer 50 is formed with a first via 51 and a second via 52 respectively located above the two ends of the active layer 25.
  • Step S4 As shown in FIGS. 8-9, a source and drain metal layer 60 is deposited on the interlayer dielectric layer 50, and the source and drain metal layer 60 is patterned to obtain the first via holes respectively. The source 61 and the drain 62 contacting both ends of the active layer 25 with 51 and the second via 52.
  • the material of the source and drain metal layer 60 is one or a stack combination of molybdenum, titanium, aluminum and copper.
  • Step S5. As shown in FIG. 10, a passivation layer 70 is deposited on the interlayer dielectric layer 50, the source electrode 61 and the drain electrode 62, and the passivation layer 70 is patterned. A third via hole 71 corresponding to the top of the drain electrode 62 is formed on 70, a pixel electrode 80 is formed on the passivation layer 70, and the pixel electrode 80 is in contact with the drain electrode 62 through the third via hole 71 .
  • the passivation layer 70 may be a silicon oxide layer, a silicon nitride layer or a stack combination of the two, etc.; the pixel electrode 80 may be indium tin oxide (ITO), indium zinc oxide (IZO) and other transparent conductive film layers, or non-transparent conductive film layers, such as silver (Ag), tungsten (W), copper, titanium, etc.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • non-transparent conductive film layers such as silver (Ag), tungsten (W), copper, titanium, etc.
  • the buffer layer 15, the metal oxide semiconductor layer 20, and the first insulating layer 31 are sequentially deposited on the substrate 10, and then the first insulating layer 31 and the metal oxide semiconductor layer 20 are
  • the active layer pattern is patterned, the active layer 25 is formed from the metal oxide semiconductor layer 20, and then the second insulating layer 32 and the gate metal layer 40 are sequentially deposited, and the top gate self-aligning technology is used for the gate electrode.
  • the metal layer 40, the second insulating layer 32, and the first insulating layer 31 are patterned, the gate metal layer 40 forms a gate, and the first insulating layer 31 and the second insulating layer 32 together form a gate insulating layer 35.
  • the first insulating layer 31 is used to protect the metal oxide semiconductor layer 20 to prevent the upper surface of the metal oxide semiconductor layer 20 from being in a subsequent process
  • PBTS positive bias temperature stress
  • NBTIS negative bias Temperature instability stress
  • the present invention also provides a thin film transistor substrate, including a substrate 10, a buffer layer 15 provided on the substrate 10, and a buffer layer 15 provided on the buffer layer 15
  • the active layer 25 is formed by patterning a metal oxide semiconductor layer.
  • the gate insulating layer 35 is formed by patterning an insulating material film layer.
  • the insulating material film layer includes a first insulating layer 31 and a second insulating layer 32; the first insulating layer 31 is patterned.
  • the second insulating layer 32 is deposited on the metal oxide semiconductor layer before the active layer 25 is formed; the second insulating layer 32 is deposited on the first insulating layer 31 and buffer after the active layer 25 is patterned.
  • the interlayer dielectric layer 50 is respectively provided with a first via 51 and a second via 52 located above the two ends of the active layer 25; the source 61 and the drain 62 respectively pass through the first The via 51 and the second via 52 are in contact with both ends of the active layer 25.
  • the passivation layer 70 is correspondingly provided with a third via hole 71 above the drain electrode 62; the pixel electrode 80 is in contact with the drain electrode 62 through the third via hole 71.
  • the material of the first insulating layer 31 may be silicon oxide, and the thickness of the first insulating layer 31 is 100-2000 ⁇ .
  • the material of the gate 45, the source 61 and the drain 62 may be one or a stack combination of molybdenum, titanium, aluminum and copper.
  • the interlayer dielectric layer 50 may be a silicon oxide layer, a silicon nitride layer, or a stack combination of the two.
  • the passivation layer 70 may be a silicon oxide layer, a silicon nitride layer, or a stack combination of the two;
  • the pixel electrode 80 may be a transparent conductive film layer such as indium tin oxide, indium zinc oxide, or the like, or non-transparent Conductive film layer, such as silver, tungsten, copper, titanium, etc.
  • the buffer layer, the metal oxide semiconductor layer and the first insulating layer are sequentially deposited on the substrate, and then the first insulating layer and the metal oxide semiconductor layer are The source layer pattern is patterned, the active layer is formed from the metal oxide semiconductor layer, and then the second insulating layer and the gate metal layer are sequentially deposited, and the top gate self-alignment technology is used to isolate the gate metal layer and the second insulating layer.
  • the first insulating layer and the first insulating layer are patterned, the gate metal layer is used to form the gate, and the first insulating layer and the second insulating layer are jointly formed to form the gate insulating layer.
  • the thin film transistor substrate of the present invention includes a substrate, a buffer layer, an active layer, a gate insulating layer and a gate.
  • the active layer is formed by patterning a metal oxide semiconductor layer
  • the gate insulating layer is composed of
  • the insulating material film layers of the first insulating layer and the second insulating layer are formed by patterning.
  • the first insulating layer is deposited and formed on the metal oxide semiconductor layer before patterning to form the active layer, so that the first insulating layer can be used.
  • the insulating layer protects the metal oxide semiconductor layer, so that defects in the contact surface between the active layer and the gate insulating layer are reduced, and device stability is improved.

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Abstract

本发明提供一种薄膜晶体管基板的制作方法及薄膜晶体管基板。本发明的薄膜晶体管基板的制作方法，在基板上依次沉积缓冲层、金属氧化物半导体层及第一绝缘层之后，再对该第一绝缘层及金属氧化物半导体层按照有源层图案进行图案化处理，由该金属氧化物半导体层形成有源层，然后依次沉积第二绝缘层及栅极金属层，利用顶栅极自对准技术对栅极金属层、第二绝缘层及第一绝缘层进行图案化处理，由该栅极金属层形成栅极，由该第一绝缘层和第二绝缘层共同形成栅极绝缘层，本发明在图案化处理金属氧化物半导体层之前沉积第一绝缘层，利用第一绝缘层对金属氧化物半导体层进行保护，使得有源层与栅极绝缘层的接触面缺陷减少，从而提高器件稳定性。

Description

薄膜晶体管基板的制作方法及薄膜晶体管基板 技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管基板的制作方法及薄膜晶体管基板。
 背景技术
薄膜晶体管（Thin Film Transistor，TFT）是目前液晶显示装置（Liquid Crystal Display，LCD）、有机电致发光二极管（Organic Light-Emitting Diode，OLED）显示装置及微发光二极管（Micro LED）等平板显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管有源层的材料也具有多种，其中，金属氧化物薄膜晶体管（metal oxide TFT），例如铟镓锌氧化物（IGZO）薄膜晶体管，具有场效应迁移率高（≥10cm 2/V·s）、制备工艺简单、大面积沉积均匀性好、响应速度快及可见光范围内透过率高等特点，被认为是显示器朝着大尺寸及柔性化方向发展的最有潜力的背板技术，但是为了提高金属氧化物薄膜晶体管的电性和稳定性，需要进行高温退火制程，限制了其在柔性方向的应用。
传统底栅结构的金属氧化物薄膜晶体管，由于栅极与源漏电极之间重叠面积较大，产生了较大的寄生电容，会导致信号的延迟，且其制作出来的晶体管尺寸较大，因而限制了其应用。顶栅自对准结构由于源漏电极之间与栅极之间没有重叠，因此具有更低的寄生电容和更好的延展性。
OLED及Micro LED作为电流驱动器件，需要较大的电流通过能力及较好的器件稳定性以及面内电压（Vth）均匀性。顶栅型IGZO TFT等类似的氧化物半导体薄膜晶体管具有较高的迁移率，比较适合作为电流驱动显示电路。目前已知的顶栅型 IGZO TFT在制作过程中，IGZO表面需要接触光阻以及较多的有机溶剂，使得IGZO有源层与栅极绝缘层的接触面缺陷较多，影响器件在后续操作中的稳定性。
 技术问题
本发明的目的在于提供一种薄膜晶体管基板的制作方法，通过在图案化处理金属氧化物半导体层之前沉积第一绝缘层，利用第一绝缘层对其进行保护，使得有源层与栅极绝缘层的接触面缺陷减少，从而提高器件稳定性。
本发明的目的还在于提供一种薄膜晶体管基板，通过在图案化处理金属氧化物半导体层之前沉积第一绝缘层，利用第一绝缘层对其进行保护，使得有源层与栅极绝缘层的接触面缺陷减少，从而提高器件稳定性。
 技术解决方案
为实现上述目的，本发明提供一种薄膜晶体管基板的制作方法，包括如下步骤：
步骤S1、提供一基板，在所述基板上依次沉积缓冲层、金属氧化物半导体层及第一绝缘层，对该第一绝缘层及金属氧化物半导体层按照有源层图案进行图案化处理，由所述金属氧化物半导体层形成有源层；
步骤S2、在所述第一绝缘层及缓冲层上依次沉积第二绝缘层及栅极金属层，对所述栅极金属层、第二绝缘层及第一绝缘层进行图案化处理，由所述栅极金属层形成栅极，由所述第一绝缘层和第二绝缘层共同形成对应位于所述栅极下方的栅极绝缘层。
所述的薄膜晶体管基板的制作方法，还包括：
步骤S3、在所述栅极、有源层及缓冲层上沉积层间介电层，对该层间介电层进行图案化处理，在所述层间介电层上形成分别对应位于所述有源层两端上方的第一过孔和第二过孔；
步骤S4、在所述层间介电层上沉积源漏极金属层，对所述源漏极金属层进行图案化处理，得到分别通过第一过孔和第二过孔与所述有源层两端相接触的源极和漏极；
步骤S5、在所述层间介电层、源极及漏极上沉积钝化层，对该钝化层进行图案化处理，在所述钝化层上形成对应位于所述漏极上方的第三过孔，在所述钝化层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触。
所述步骤S1中，所沉积形成的第一绝缘层的材料为氧化硅，所述第一绝缘层的厚度为100-2000Å。
所述步骤S1中，所沉积形成的金属氧化物半导体层的材料为铟镓锌氧化物、铟镓锡氧化物或铟镓锌锡氧化物。
所述步骤S1中，先采用干法蚀刻法对所述第一绝缘层进行图案化处理，然后以剩余的所述第一绝缘层为遮蔽层，采用湿法蚀刻法对所述金属氧化物半导体层进行图案化处理，由所述金属氧化物半导体层形成有源层。
所述步骤S1中，所述第一绝缘层通过等离子体增强化学气相沉积法制作形成。
本发明还提供一种薄膜晶体管基板，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的有源层、设于所述有源层上的栅极绝缘层及对应设于所述栅极绝缘层上的栅极；
所述有源层由金属氧化物半导体层经图案化处理形成；
所述栅极绝缘层由绝缘材料膜层经图案化处理形成，所述绝缘材料膜层包括第一绝缘层和第二绝缘层；
所述第一绝缘层在图案化形成所述有源层之前沉积形成于所述金属氧化物半导体层上；
所述第二绝缘层在图案化形成所述有源层之后沉积形成于所述第一绝缘层和缓冲层上。
所述的薄膜晶体管基板还包括设于所述栅极、有源层及缓冲层上的层间介电层、设于层间介电层上的源极和漏极、设于所述层间介电层、源极及漏极上的钝化层及设于所述钝化层上的像素电极；
所述层间介电层分别对应位于所述有源层两端上方设有第一过孔和第二过孔；
所述源极和漏极分别通过第一过孔和第二过孔与所述有源层两端相接触；
所述钝化层对应位于所述漏极上方设有第三过孔；
所述像素电极通过第三通孔与所述漏极相接触。
所述第一绝缘层的材料为氧化硅，所述第一绝缘层的厚度为100-2000Å。
所述有源层的材料为铟镓锌氧化物、铟镓锡氧化物或铟镓锌锡氧化物。
 有益效果
本发明的有益效果：本发明的薄膜晶体管基板的制作方法，在基板上依次沉积缓冲层、金属氧化物半导体层及第一绝缘层之后，再对该第一绝缘层及金属氧化物半导体层按照有源层图案进行图案化处理，由该金属氧化物半导体层形成有源层，然后依次沉积第二绝缘层及栅极金属层，利用顶栅极自对准技术对栅极金属层、第二绝缘层及第一绝缘层进行图案化处理，由该栅极金属层形成栅极，由该第一绝缘层和第二绝缘层共同形成栅极绝缘层，通过在图案化处理金属氧化物半导体层之前沉积第一绝缘层，利用第一绝缘层对金属氧化物半导体层进行保护，使得有源层与栅极绝缘层的接触面缺陷减少，从而提高器件稳定性。本发明的薄膜晶体管基板，包括基板、缓冲层、有源层、栅极绝缘层及栅极，所述有源层由金属氧化物半导体层经图案化处理形成，所述栅极绝缘层由包括第一绝缘层和第二绝缘层的绝缘材料膜层经图案化处理形成，该第一绝缘层在图案化形成所述有源层之前沉积形成于金属氧化物半导体层上，从而可利用第一绝缘层对金属氧化物半导体层进行保护，使得有源层与栅极绝缘层的接触面缺陷减少，提高器件稳定性。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为本发明的薄膜晶体管基板的制作方法的流程示意图；
图2-3为本发明的薄膜晶体管基板的制作方法的步骤S1的示意图；
图4-5为本发明的薄膜晶体管基板的制作方法的步骤S2的示意图；
图6-7为本发明的薄膜晶体管基板的制作方法的步骤S3的示意图；
图8-9为本发明的薄膜晶体管基板的制作方法的步骤S4的示意图；
图10为本发明的薄膜晶体管基板的制作方法的步骤S5的示意图暨本发明的薄膜晶体管基板的结构示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明首先提供一种薄膜晶体管基板的制作方法，包括如下步骤：
步骤S1、如图2-3所示，提供一基板10，在所述基板10上依次沉积缓冲层15、金属氧化物半导体层20及第一绝缘层31，对该第一绝缘层31及金属氧化物半导体层20按照有源层图案进行图案化处理，由所述金属氧化物半导体层20形成有源层25。
具体地，所述步骤S1中，在所述基板10上沉积形成的缓冲层15可为氧化硅（SiOx）层、氮化硅（SiNx）层或两者的堆栈组合等。
具体地，所述步骤S1中，所沉积形成的第一绝缘层31的材料可为氧化硅，厚度为100-2000Å，以该第一绝缘层31作为半导体制程中金属氧化物半导体层20的保护层，可避免金属氧化物半导体层20上表面接触光阻、有机溶液、酸碱等。
具体地，所述步骤S1中，所沉积形成的金属氧化物半导体层20的材料可为铟镓锌氧化物（IGZO）、铟镓锡氧化物（IGTO）或铟镓锌锡氧化物（IGZTO）等金属氧化物半导体材料。
具体地，所述步骤S1中，首先采用干法蚀刻法（Dry Etch）对所述第一绝缘层31进行图案化处理，仅保留对应于有源层图案上的第一绝缘层31，接着采用湿法蚀刻法（Wet Etch）对所述金属氧化物半导体层20进行图案化处理，由所述金属氧化物半导体层20形成有源层25。
具体地，所述步骤S1中，所述第一绝缘层31可通过等离子体增强化学气相沉积法（Plasma Enhanced Chemical Vapor Deposition，PECVD）、原子层沉积法（Atomic layer deposition，ALD）、或物理气相沉积法（Physical Vapor Deposition，PVD） 制作形成，优选采用PECVD制作形成。
步骤S2、如图4-5所示，在所述第一绝缘层31及缓冲层15上依次沉积第二绝缘层32及栅极金属层40，利用顶栅自对准技术对所述栅极金属层40、第二绝缘层32及第一绝缘层31进行图案化处理，由所述栅极金属层40形成栅极45，由所述第一绝缘层31和第二绝缘层32共同形成对应位于所述栅极45下方的栅极绝缘层35。
具体地，所述步骤S2中，所沉积形成的第二绝缘层32的材料可为氧化硅或氮化硅。
具体地，所述所步骤S2中，所述栅极金属层40的材料为钼（Mo）、钛（Ti）、铝（Al）及铜（Cu）中的一种或多种的堆栈组合。
具体地，所述所步骤S2中，所述第二绝缘层32通过PECVD、ALD、或PVD沉积形成。
步骤S3、如图6-7所示，在所述栅极45、有源层25及缓冲层15上沉积层间介电层50，对该层间介电层50进行图案化处理，在所述层间介电层50上形成分别对应位于所述有源层25两端上方的第一过孔51和第二过孔52。
具体地，所述步骤S3中，所述层间介电层50可为氧化硅层、氮化硅层或两者的堆栈组合等。
步骤S4、如图8-9所示，在所述层间介电层50上沉积源漏极金属层60，对所述源漏极金属层60进行图案化处理，得到分别通过第一过孔51和第二过孔52与所述有源层25两端相接触的源极61和漏极62。
具体地，所述所步骤S4中，所述源漏极金属层60的材料为钼、钛、铝及铜中的一种或多种的堆栈组合。
步骤S5、如图10所示，在所述层间介电层50、源极61及漏极62上沉积钝化层70，对该钝化层70进行图案化处理，在所述钝化层70上形成对应位于所述漏极62上方的第三过孔71，在所述钝化层70上形成像素电极80，所述像素电极80通过第三通孔71与所述漏极62相接触。
具体地，所述步骤S5中，所述钝化层70可为氧化硅层、氮化硅层或两者的堆栈组合等；所述像素电极80可为氧化铟锡（ITO）、氧化铟锌（IZO）等透明导电膜层，或非透明导电膜层，如银（Ag）、钨（W）、铜、钛等。
本发明的薄膜晶体管基板的制作方法，在基板10上依次沉积缓冲层15、金属氧化物半导体层20及第一绝缘层31之后，再对该第一绝缘层31及金属氧化物半导体层20按照有源层图案进行图案化处理，由该金属氧化物半导体层20形成有源层25，然后依次沉积第二绝缘层32及栅极金属层40，利用顶栅极自对准技术对该栅极金属层40、第二绝缘层32及第一绝缘层31进行图案化处理，由该栅极金属层40形成栅极，由该第一绝缘层31和第二绝缘层32共同形成栅极绝缘层35，通过在图案化处理金属氧化物半导体层20之前沉积第一绝缘层31，利用第一绝缘层31对金属氧化物半导体层20进行保护，避免金属氧化物半导体层20上表面在后续制程中接触有机溶液、酸碱等，使得有源层25与栅极绝缘层35的接触面缺陷减少，保持器件在正偏压温度不稳定性（positive bias temperature stress，PBTS）及负偏压温度不稳定性（negative bias temperature instability stress，NBTIS）测试中性能稳定，从而提高器件稳定性。
请参阅图10，基于上述的薄膜晶体管基板的制作方法，本发明还提供一种薄膜晶体管基板，包括基板10、设于所述基板10上的缓冲层15、设于所述缓冲层15上的有源层25、设于所述有源层25上的栅极绝缘层35、对应设于所述栅极绝缘层35上的栅极45、设于所述栅极45、有源层25及缓冲层15上的层间介电层50、设于层间介电层50上的源极61和漏极62、设于所述层间介电层50、源极61及漏极62上的钝化层70及设于所述钝化层70上的像素电极80。
具体地，所述有源层25由金属氧化物半导体层经图案化处理形成。
具体地，所述栅极绝缘层35由绝缘材料膜层经图案化处理形成，所述绝缘材料膜层包括第一绝缘层31和第二绝缘层32；所述第一绝缘层31在图案化形成所述有源层25之前沉积形成于所述金属氧化物半导体层上；所述第二绝缘层32在图案化形成所述有源层25之后沉积形成于所述第一绝缘层31和缓冲层15上。
具体地，所述层间介电层50分别对应位于所述有源层25两端上方设有第一过孔51和第二过孔52；所述源极61和漏极62分别通过第一过孔51和第二过孔52与所述有源层25两端相接触。
具体地，所述钝化层70对应位于所述漏极62上方设有第三过孔71；所述像素电极80通过第三通孔71与所述漏极62相接触。
具体地，所述第一绝缘层31的材料可为氧化硅，所述第一绝缘层31的厚度为100-2000Å。
具体地，所述有源层25的材料可为铟镓锌氧化物、铟镓锡氧化物或铟镓锌锡氧化物等金属氧化物半导体材料。
具体地，所述缓冲层15可为氧化硅层、氮化硅层或两者的堆栈组合等。
具体地，所述栅极45、源极61及漏极62的材料可以为钼、钛、铝及铜中的一种或多种的堆栈组合。
具体地，所述第二绝缘层32的材料可为氧化硅或氮化硅。
具体地，所述层间介电层50可为氧化硅层、氮化硅层或两者的堆栈组合等。
具体地，所述钝化层70可为氧化硅层、氮化硅层或两者的堆栈组合等；所述像素电极80可为氧化铟锡、氧化铟锌等透明导电膜层，或非透明导电膜层，如银、钨、铜、钛等。
本发明的薄膜晶体管基板，有源层25由金属氧化物半导体层经图案化处理形成，栅极绝缘层35由包括第一绝缘层31和第二绝缘层32的绝缘材料膜层经图案化处理形成，该第一绝缘层31在图案化形成所述有源层25之前沉积形成于金属氧化物半导体层上，从而可利用该第一绝缘层31对金属氧化物半导体层进行保护，使得有源层25与栅极绝缘层35的接触面缺陷减少，从而提高器件稳定性。
综上所述，本发明的薄膜晶体管基板的制作方法，在基板上依次沉积缓冲层、金属氧化物半导体层及第一绝缘层之后，再对该第一绝缘层及金属氧化物半导体层按照有源层图案进行图案化处理，由该金属氧化物半导体层形成有源层，然后依次沉积第二绝缘层及栅极金属层，利用顶栅极自对准技术对栅极金属层、第二绝缘层及第一绝缘层进行图案化处理，由该栅极金属层形成栅极，由该第一绝缘层和第二绝缘层共同形成栅极绝缘层，通过在图案化处理金属氧化物半导体层之前沉积第一绝缘层，利用第一绝缘层对金属氧化物半导体层进行保护，使得有源层与栅极绝缘层的接触面缺陷减少，从而提高器件稳定性。本发明的薄膜晶体管基板，包括基板、缓冲层、有源层、栅极绝缘层及栅极，所述有源层由金属氧化物半导体层经图案化处理形成，所述栅极绝缘层由包括第一绝缘层和第二绝缘层的绝缘材料膜层经图案化处理形成，该第一绝缘层在图案化形成所述有源层之前沉积形成于金属氧化物半导体层上，从而可利用第一绝缘层对金属氧化物半导体层进行保护，使得有源层与栅极绝缘层的接触面缺陷减少，提高器件稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种薄膜晶体管基板的制作方法，包括如下步骤：
    步骤S1、提供一基板，在所述基板上依次沉积缓冲层、金属氧化物半导体层及第一绝缘层，对该第一绝缘层及金属氧化物半导体层按照有源层图案进行图案化处理，由所述金属氧化物半导体层形成有源层；
    步骤S2、在所述第一绝缘层及缓冲层上依次沉积第二绝缘层及栅极金属层，对所述栅极金属层、第二绝缘层及第一绝缘层进行图案化处理，由所述栅极金属层形成栅极，由所述第一绝缘层和第二绝缘层共同形成对应位于所述栅极下方的栅极绝缘层。
  2. 如权利要求1所述的薄膜晶体管基板的制作方法，还包括：
    步骤S3、在所述栅极、有源层及缓冲层上沉积层间介电层，对该层间介电层进行图案化处理，在所述层间介电层上形成分别对应位于所述有源层两端上方的第一过孔和第二过孔；
    步骤S4、在所述层间介电层上沉积源漏极金属层，对所述源漏极金属层进行图案化处理，得到分别通过第一过孔和第二过孔与所述有源层两端相接触的源极和漏极；
    步骤S5、在所述层间介电层、源极及漏极上沉积钝化层，对该钝化层进行图案化处理，在所述钝化层上形成对应位于所述漏极上方的第三过孔，在所述钝化层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触。
  3. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述步骤S1中，所沉积形成的第一绝缘层的材料为氧化硅，所述第一绝缘层的厚度为100-2000Å。
  4. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述步骤S1中，所沉积形成的金属氧化物半导体层的材料为铟镓锌氧化物、铟镓锡氧化物或铟镓锌锡氧化物。
  5. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述步骤S1中，先采用干法蚀刻法对所述第一绝缘层进行图案化处理，然后以剩余的所述第一绝缘层为遮蔽层，采用湿法蚀刻法对所述金属氧化物半导体层进行图案化处理，由所述金属氧化物半导体层形成有源层。
  6. 如权利要求1所述的薄膜晶体管基板的制作方法，其中，所述步骤S1中，所述第一绝缘层通过等离子体增强化学气相沉积法制作形成。
  7. 一种薄膜晶体管基板，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的有源层、设于所述有源层上的栅极绝缘层及对应设于所述栅极绝缘层上的栅极；
    所述有源层由金属氧化物半导体层经图案化处理形成；
    所述栅极绝缘层由绝缘材料膜层经图案化处理形成，所述绝缘材料膜层包括第一绝缘层和第二绝缘层；
    所述第一绝缘层在图案化形成所述有源层之前沉积形成于所述金属氧化物半导体层上；
    所述第二绝缘层在图案化形成所述有源层之后沉积形成于所述第一绝缘层和缓冲层上。
  8. 如权利要求7所述的薄膜晶体管基板，还包括设于所述栅极、有源层及缓冲层上的层间介电层、设于层间介电层上的源极和漏极、设于所述层间介电层、源极及漏极上的钝化层及设于所述钝化层上的像素电极；
    所述层间介电层分别对应位于所述有源层两端上方设有第一过孔和第二过孔；
    所述源极和漏极分别通过第一过孔和第二过孔与所述有源层两端相接触；
    所述钝化层对应位于所述漏极上方设有第三过孔；
    所述像素电极通过第三通孔与所述漏极相接触。
  9. 如权利要求7所述的薄膜晶体管基板，其中，所述第一绝缘层的材料为氧化硅，所述第一绝缘层的厚度为100-2000Å。
  10. 如权利要求7所述的薄膜晶体管基板，其中，所述有源层的材料为铟镓锌氧化物、铟镓锡氧化物或铟镓锌锡氧化物。
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