US11374027B2 - Manufacturing method of thin film transistor substrate and thin film transistor substrate - Google Patents

Manufacturing method of thin film transistor substrate and thin film transistor substrate Download PDF

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US11374027B2
US11374027B2 US16/620,515 US201916620515A US11374027B2 US 11374027 B2 US11374027 B2 US 11374027B2 US 201916620515 A US201916620515 A US 201916620515A US 11374027 B2 US11374027 B2 US 11374027B2
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insulating layer
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oxide semiconductor
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Macai Lu
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a manufacturing method and a thin film transistor substrate of a thin film transistor substrate.
  • Thin film transistors are main driving elements in flat display devices such as liquid crystal display devices (LCDs), organic light-emitting diode (OLED) display devices, and micro light-emitting diode (Micro LED) display devices.
  • the thin film transistors are directly related to a development of high performance flat display devices.
  • the thin film transistors have a variety of structures. There are also various materials for forming an active layer of the thin film transistor of a corresponding structure, where a metal oxide TFT, such as an indium gallium zinc oxide (IGZO) thin film transistor, has high field effect mobility ( ⁇ 10 cm 2 /V ⁇ s).
  • IGZO indium gallium zinc oxide
  • the thin film transistor has a simple preparation process, good uniformity of deposition over a large area, fast response, and high transmittance in a range of visible light. Therefore, the thin film transistors are considered to be the most promising backplane technology for large size and flexible displays.
  • a high temperature annealing process is required, which limits its application in flexibility.
  • a top gate type IGZO TFT or the like has a high mobility and is suitable as a current driving display circuit.
  • a surface of the IGZO will be in contact with a photoresist and more organic solvent, so that a contact surface between the active layer of the IGZO and a gate insulating layer has more defects, which affects the stability of the device in subsequent operations.
  • An object of the present disclosure is to provide a manufacturing method of a thin film transistor substrate.
  • a first insulating layer is deposited before a metal oxide semiconductor layer is patterned, so the first insulating layer can protect it, such that defects on a contact surface between an active layer and a gate insulating layer are reduced, thereby improving the stability of a device.
  • Another object of the present disclosure is to provide a thin film transistor substrate.
  • a first insulating layer is deposited before a metal oxide semiconductor layer is patterned, so the first insulating layer can protect it, such that defects on a contact surface between an active layer and a gate insulating layer are reduced, thereby improving the stability of a device.
  • the present disclosure provides a manufacturing method of a thin film transistor substrate, including the following steps.
  • step S1 providing a substrate, and sequentially depositing a buffer layer, a metal oxide semiconductor layer, and a first insulating layer on the substrate, and patterning the first insulating layer and the metal oxide semiconductor layer according to a pattern of an active layer.
  • the metal oxide semiconductor layer forms the active layer.
  • step S2 sequentially depositing a second insulating layer and a gate metal layer on the first insulating layer and the buffer layer, and patterning the gate metal layer, the second insulating layer, and the first insulating layer.
  • the gate metal layer forms a gate
  • the first insulating layer and the second insulating layer together form a gate insulating layer below the gate.
  • the manufacturing method of the thin film transistor substrate further including:
  • step S3 depositing an interlayer dielectric layer on the gate, the active layer, and the buffer layer, and patterning the interlayer dielectric layer, and forming a first via hole and a second via hole on the interlayer dielectric layer.
  • the first via hole and the second via hole are respectively disposed above two ends of the active layer.
  • step S4 depositing a source and drain metal layer on the interlayer dielectric layer, and patterning the source and drain metal layer to obtain a source and a drain that are in contact with the both ends of the active layer through the first via hole and the second via hole, respectively.
  • step S5 depositing a passivation layer on the interlayer dielectric layer, the source, and the drain, patterning the passivation layer, forming a third via hole on the passivation layer above the drain, and forming a pixel electrode on the passivation layer.
  • the pixel electrode is in contact with the drain through the third via hole.
  • material of the first insulating layer includes silicon oxide, and a thickness of the first insulating layer ranges from 100 ⁇ to 2000 ⁇ .
  • material of the metal oxide semiconductor layer includes indium gallium zinc oxide, indium gallium tin oxide, or indium gallium zinc tin oxide.
  • the first insulating layer is patterned by a dry etching method, and then a remaining first insulating layer serves as a shielding layer.
  • the metal oxide semiconductor layer is patterned by a wet etching method, and the active layer is formed from the metal oxide semiconductor layer.
  • the first insulating layer is formed by a plasma-enhanced chemical vapor deposition process.
  • the present disclosure also provides a thin film transistor substrate, including a substrate, a buffer layer disposed on the substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, and a gate correspondingly disposed on the gate insulating layer.
  • the active layer is formed by patterning a metal oxide semiconductor layer.
  • the gate insulating layer is formed by patterning an insulating material layer, and the insulating material layer includes a first insulating layer and a second insulating layer.
  • the first insulating layer is deposited on the metal oxide semiconductor layer before the active layer is formed.
  • the second insulating layer is deposited on the first insulating layer and the buffer layer after the active layer is formed.
  • the thin film transistor substrate includes an interlayer dielectric layer, a source, a drain, a passivation layer, and a pixel electrode.
  • the interlayer dielectric layer is disposed on the gate, the active layer, and the buffer layer.
  • the source and the drain are disposed on the interlayer dielectric layer.
  • the passivation layer is disposed on the interlayer dielectric layer, the source, and the drain.
  • the pixel electrode is disposed on the passivation layer.
  • the interlayer dielectric layer is provided with a first via hole and a second via hole above two ends of the active layer.
  • the source and the drain are in contact with the two ends of the active layer through the first via hole and the second via hole, respectively.
  • the passivation layer is provided with a third via hole above the drain.
  • the pixel electrode is in contact with the drain through the third via hole.
  • Material of the first insulating layer includes silicon oxide, and a thickness of the first insulating layer ranges from 100 ⁇ to 2000 ⁇ .
  • Material of the active layer includes indium gallium zinc oxide, indium gallium tin oxide, or indium gallium zinc tin oxide.
  • the buffer layer, the metal oxide semiconductor layer, and the first insulating layer are sequentially deposited on the substrate, and then the first insulating layer and the metal oxide semiconductor layer are patterned according to the pattern of the active layer.
  • the metal oxide semiconductor layer forms the active layer.
  • the second insulating layer and the gate metal layer are then sequentially deposited.
  • the gate metal layer, the second insulating layer, and first insulating layer are patterned by a top gate self-aligned technology.
  • the gate metal layer forms the gate, and the first insulating layer and the second insulating layer together form the gate insulating layer.
  • the first insulating layer is deposited before the metal oxide semiconductor layer is patterned, so the first insulating layer can be used to protect the metal oxide semiconductor layer, such that defects on a contact surface between the active layer and the gate insulating layer are reduced, thereby improving the stability of a device.
  • the thin film transistor substrate of the present disclosure includes the substrate, the buffer layer, the active layer, the gate insulating layer, and the gate.
  • the active layer is formed by patterning the metal oxide semiconductor layer.
  • the gate insulating layer is formed by a patterned insulating material layer including the first insulating layer and the second insulating layer.
  • the first insulating layer is deposited on the metal oxide semiconductor layer before being patterned to form the active layer, so that the first insulating layer can be used to protect the metal oxide semiconductor layer. Thus, defects on a contact surface between the active layer and the gate insulating layer are reduced, and the stability of a device is increased.
  • FIG. 1 is a flowchart of a manufacturing method of a thin film transistor substrate of the present disclosure.
  • FIG. 2 and FIG. 3 are schematic diagrams showing a step S1 of the manufacturing method of the thin film transistor substrate of the present disclosure.
  • FIG. 4 and FIG. 5 are schematic diagrams showing a step S2 of the manufacturing method of the thin film transistor substrate of the present disclosure.
  • FIG. 6 and FIG. 7 are schematic diagrams showing a step S3 of the manufacturing method of the thin film transistor substrate of the present disclosure.
  • FIG. 8 and FIG. 9 are schematic diagrams showing a step S4 of the manufacturing method of the thin film transistor substrate of the present disclosure.
  • FIG. 10 is schematic diagrams showing a step S5 of the manufacturing method of the thin film transistor substrate of the present disclosure, and also showing the thin film transistor substrate of the present disclosure.
  • the present disclosure provides a manufacturing method of a thin film transistor substrate, including the following steps.
  • a substrate 10 is provided.
  • a buffer layer 15 , a metal oxide semiconductor layer 20 , and a first insulating layer 31 are sequentially deposited on the substrate 10 .
  • the first insulating layer 31 and the metal oxide semiconductor layer 20 are patterned according to a pattern of an active layer.
  • the metal oxide semiconductor layer 20 forms the active layer 25 .
  • the buffer layer 15 formed on the substrate 10 may be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a laminated combination of the two.
  • material of the first insulating layer 31 includes a silicon oxide having a thickness of 100 ⁇ to 2000 ⁇ .
  • the first insulating layer 31 serves as a protective layer of the metal oxide semiconductor layer 20 in a semiconductor process, so that an upper surface of the metal oxide semiconductor layer 20 can be prevented from being in contact with a photoresist, an organic solution, acid and alkali, and the like.
  • material of the deposited metal oxide semiconductor layer 20 may be a metal oxide semiconductor material such as indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO).
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin oxide
  • IGZTO indium gallium zinc tin oxide
  • the first insulating layer 31 is firstly patterned by using a dry etching method, and only a portion of the first insulating layer 31 corresponding to the pattern of the active layer is remained, and then the metal oxide semiconductor layer 20 is patterned by using a wet etching method.
  • the metal oxide semiconductor layer 20 forms the active layer 25 .
  • the first insulating layer 31 may be formed by being subjected to a plasma-enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) method, or a physical vapor deposition (PVD) method, preferably, the PECVD process is employed.
  • PECVD plasma-enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • a second insulating layer 32 and a gate metal layer 40 are sequentially deposited on the first insulating layer 31 and the buffer layer 15 .
  • the gate metal layer 40 , the second insulating layer 32 , and the first insulating layer 31 are patterned by a top gate self-aligned technology.
  • the gate metal layer 40 forms a gate 45
  • the first insulating layer 31 and the second insulating layer 32 together form a gate insulating layer 35 below the gate 45 .
  • material of the formed second insulating layer 32 may be silicon oxide or silicon nitride.
  • material of the gate metal layer 40 is selected from the group consisting of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • the second insulating layer 32 is formed by PECVD, ALD, or PVD deposition.
  • an interlayer dielectric layer 50 is deposited on the gate 45 , the active layer 25 , and the buffer layer 15 .
  • the interlayer dielectric layer is patterned.
  • a first via hole 51 and a second via hole 52 are formed on the interlayer dielectric layer 50 , and the first via hole 51 and the second via hole 52 are respectively disposed above two ends of the active layer 25 .
  • the interface dielectric layer 50 may be a silicon oxide layer, a silicon nitride layer, or a laminated combination of the two.
  • a source and drain metal layer 60 is deposited on the interlayer dielectric layer 50 .
  • the source and drain metal layer 60 is patterned to obtain a source 61 and a drain 62 that are in contact with the both ends of the active layer 25 through the first via hole 51 and the second via hole 52 , respectively.
  • material of the source and drain metal layer 60 is selected from the group consisting of molybdenum, titanium, aluminum, and copper.
  • a passivation layer 70 is deposited on the interlayer dielectric layer 50 , the source 61 , and the drain 62 .
  • the passivation layer 70 is patterned.
  • a third via hole 71 is formed on the passivation layer 70 above the drain 62 .
  • a pixel electrode 80 is formed on the passivation layer 70 .
  • the pixel electrode 80 is in contact with the drain 62 through the third via hole 71 .
  • the passivation layer 70 may be a silicon oxide layer, a silicon nitride layer, or a laminated combination of the two.
  • the pixel electrode 80 may be a transparent conductive film layer (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or a non-transparent conductive film layer (such as silver (Ag), tungsten (W), copper, titanium or the like).
  • the buffer layer 15 , the metal oxide semiconductor layer 20 , and the first insulating layer 31 are sequentially deposited on the substrate 10 , and then the first insulating layer 31 and the metal oxide semiconductor layer 20 are patterned according to the pattern of the active layer.
  • the metal oxide semiconductor layer 20 forms the active layer 25 .
  • the second insulating layer 32 and the gate metal layer 40 are then sequentially deposited.
  • the gate metal layer 40 , the second insulating layer 32 , and first insulating layer 31 are patterned by a top gate self-aligned technology.
  • the gate metal layer 40 forms the gate, and the first insulating layer 31 and the second insulating layer 32 together form the gate insulating layer 35 .
  • the first insulating layer 31 is deposited before the metal oxide semiconductor layer 20 is patterned, so the first insulating layer 31 can be used to protect the metal oxide semiconductor layer 20 , so that an upper surface of the metal oxide semiconductor layer 20 can be prevented from being in contact with an organic solution, acid and alkali, and the like in subsequent operations.
  • PBTS positive bias temperature stress
  • NTIS negative bias temperature instability
  • the present disclosure further provides a thin film transistor substrate.
  • the thin film transistor substrate includes a substrate 10 , a buffer layer 15 , an active layer 25 , a gate insulating layer 35 , a gate 45 , an interlayer dielectric layer 50 , a source 61 , a drain 62 , a passivation layer 70 , and a pixel electrode 80 .
  • the buffer layer 15 is disposed on the substrate 10 .
  • the active layer 25 is disposed on the buffer layer 15 .
  • the gate insulating layer 35 is disposed on the active layer 25 .
  • the gate 45 correspondingly disposed on the gate insulating layer 35 .
  • the interlayer dielectric layer 50 is disposed on the gate 45 , the active layer 25 , and the buffer layer 15 .
  • the source 61 and the drain 62 are disposed on the interlayer dielectric layer 50 .
  • the passivation layer 70 is disposed on the interlayer dielectric layer 50 , the source 61 , and the drain 62 .
  • the pixel electrode 80 is disposed on the passivation layer 70 .
  • the active layer 25 is formed by patterning a metal oxide semiconductor layer.
  • the gate insulating layer 35 is formed by patterning an insulating material layer.
  • the insulating material layer includes a first insulating layer 31 and a second insulating layer 32 .
  • the first insulating layer 31 is deposited on the metal oxide semiconductor layer.
  • the second insulating layer 32 is deposited on the first insulating layer 31 and the buffer layer 15 .
  • a first via hole 51 and a second via hole 52 are formed on the interlayer dielectric layer 50 , and the first via hole 51 and the second via hole 52 are respectively disposed above two ends of the active layer 25 .
  • the source 61 and the drain 62 are in contact with the both ends of the active layer 25 through the first via hole 51 and the second via hole 52 , respectively.
  • a third via hole 71 is formed on the passivation layer 70 above the drain 62 .
  • the pixel electrode 80 is in contact with the drain 62 through the third via hole 71 .
  • material of the first insulating layer 31 may be silicon oxide, and a thickness of the first insulating layer 31 ranges from 100 ⁇ to 2000 ⁇ .
  • material of the active layer 25 may be a metal oxide semiconductor material such as indium gallium zinc oxide, indium gallium tin oxide, or indium gallium zinc tin oxide.
  • the buffer layer 15 may be a silicon oxide layer, a silicon nitride layer, or a laminated combination of the two.
  • materials of the gate 45 , the source 61 , and the drain 62 are selected from the group consisting of molybdenum, titanium, aluminum, and copper.
  • material of the second insulating layer 32 may be silicon oxide or silicon nitride.
  • the interlayer dielectric layer 50 may be a silicon oxide layer, a silicon nitride layer, or a laminated combination of the two.
  • the passivation layer 70 may be a silicon oxide layer, a silicon nitride layer, or a laminated combination of the two.
  • the pixel electrode 80 may be a transparent conductive film layer (such as indium tin oxide or indium zinc oxide) or a non-transparent conductive film layer (such as silver, tungsten, copper, titanium or the like).
  • the active layer 25 is formed by patterning the metal oxide semiconductor layer.
  • the gate insulating layer 35 is formed by patterning an insulating material layer including the first insulating layer 31 and the second insulating layer 32 .
  • the first insulating layer 31 is deposited on the metal oxide semiconductor layer.
  • the metal oxide semiconductor layer can be protected by the first insulating layer 31 , so that defects on a contact surface between the active layer 25 and the gate insulating layer 35 are reduced, and the stability of a device is increased.
  • the buffer layer, the metal oxide semiconductor layer, and the first insulating layer are sequentially deposited on the substrate, and then the first insulating layer and the metal oxide semiconductor layer are patterned according to the pattern of the active layer.
  • the metal oxide semiconductor layer forms the active layer.
  • the second insulating layer and the gate metal layer are then sequentially deposited.
  • the gate metal layer, the second insulating layer, and first insulating layer are patterned by a top gate self-aligned technology.
  • the gate metal layer forms the gate, and the first insulating layer and the second insulating layer together form the gate insulating layer.
  • the first insulating layer is deposited before the metal oxide semiconductor layer is patterned, so the first insulating layer can be used to protect the metal oxide semiconductor layer, such that defects on a contact surface between the active layer and the gate insulating layer are reduced, thereby improving the stability of a device.
  • the thin film transistor substrate of the present disclosure includes the substrate, the buffer layer, the active layer, the gate insulating layer, and the gate.
  • the active layer is formed by patterning the metal oxide semiconductor layer.
  • the gate insulating layer is formed by a patterned insulating material layer including the first insulating layer and the second insulating layer.
  • the first insulating layer is deposited on the metal oxide semiconductor layer before being patterned to form the active layer, so that the first insulating layer can be used to protect the metal oxide semiconductor layer. Thus, defects on a contact surface between the active layer and the gate insulating layer are reduced, and the stability of a device is increased.

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PCT/CN2019/096604 WO2021003767A1 (zh) 2019-07-05 2019-07-18 薄膜晶体管基板的制作方法及薄膜晶体管基板

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CN111681960A (zh) * 2020-05-12 2020-09-18 福建华佳彩有限公司 一种tft结构的制作方法
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