WO2016000336A1 - 低温多晶硅tft阵列基板及其制备方法、显示装置 - Google Patents

低温多晶硅tft阵列基板及其制备方法、显示装置 Download PDF

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WO2016000336A1
WO2016000336A1 PCT/CN2014/087893 CN2014087893W WO2016000336A1 WO 2016000336 A1 WO2016000336 A1 WO 2016000336A1 CN 2014087893 W CN2014087893 W CN 2014087893W WO 2016000336 A1 WO2016000336 A1 WO 2016000336A1
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film
layer
polysilicon
photoresist
thin film
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PCT/CN2014/087893
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English (en)
French (fr)
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龙春平
梁逸南
刘政
王祖强
田雪雁
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京东方科技集团股份有限公司
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Priority to EP14882781.9A priority Critical patent/EP2985784B1/en
Priority to US14/769,891 priority patent/US9947697B2/en
Publication of WO2016000336A1 publication Critical patent/WO2016000336A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the technical field of preparing an active matrix organic light emitting diode display, and more particularly to a low temperature polysilicon thin film field effect transistor (TFT) array substrate and a method for fabricating the same, and the low temperature polysilicon thin film field effect transistor array substrate Display device.
  • TFT thin film field effect transistor
  • organic light emitting diode displays Compared with liquid crystal displays, organic light emitting diode displays have the advantages of fast response speed, light weight, flexibility, and wide viewing angle.
  • the Active Matrix Organic Light Emitting Diode (AMOLED) has the advantages of low drive current and low power consumption, and is suitable for high-resolution displays.
  • the active matrix organic light emitting diode architecture can be driven using amorphous silicon, polysilicon, oxide semiconductor or organic thin film transistors. Among them, the carrier mobility and the driving current of the amorphous silicon or organic thin film transistor are small, so the voltage required to drive the high-brightness organic light emitting diode is high and the device is large.
  • Low-temperature polysilicon has a mobility of up to 100cm 2 /Vs, and its high current characteristics meet the strict requirements of organic light-emitting diodes.
  • the low operating voltage and high-density driving architecture make the organic light-emitting diodes have a longer life. Different from the traditional liquid crystal display voltage driving method, the organic light emitting diode driving needs a special current driving structure, and there is a compensation circuit involved in overcoming the gray scale and panel uniformity.
  • 2 to 6 thin film transistors are often required in the same pixel, and the high-density layout characteristics of low-temperature polysilicon make the high-brightness and high-quality organic light-emitting diode panels easier to implement.
  • Most of the currently successful commercial production of AMOLEDs is the use of low temperature polysilicon thin film field effect transistor array substrates.
  • FIG. 1 is a schematic view of a conventional low temperature polysilicon thin film field effect transistor array substrate.
  • the mask process leads to a complicated preparation process.
  • the manufacturing process of the conventional low-temperature polysilicon thin film field effect transistor array substrate shown in FIG. 1 will be described below with reference to FIGS. 2A to 2G.
  • a silicon nitride (SiN) film and a silicon dioxide (SiO 2 ) film are sequentially deposited on the entire insulating substrate 1 by plasma enhanced chemical vapor deposition (PECVD) to form silicon nitride and silicon dioxide.
  • PECVD plasma enhanced chemical vapor deposition
  • the buffer layer 2 is constructed.
  • An amorphous silicon (a-Si) film is then formed on the buffer layer 2 by PECVD or other chemical or physical vapor deposition methods.
  • the a-Si crystal is made into a polysilicon film by laser annealing (ELA) or solid phase crystallization (SPC).
  • a pattern of a photoresist layer is formed on the polysilicon film by a conventional mask process, and the photoresist layer is used as an etch barrier layer, and the polysilicon film not protected by the photoresist layer is plasma-etched to form a polysilicon active layer. 4 and polysilicon storage capacitor 3.
  • the transistor channel in the polysilicon active layer 4 is doped with a low concentration ion by an ion implantation process, and a conductive channel required for the thin film transistor is formed in the polysilicon active layer 4.
  • a photoresist 5 composed of a photoresist material is formed on the polysilicon active layer 4 by a mask process to protect the polysilicon active layer 4 from ion implantation.
  • a poly-concentration ion implantation process is performed on the polysilicon storage capacitor 3 without the photoresist layer protection, and the polysilicon storage capacitor 3 is converted into a low-resistance doped polysilicon film.
  • FIG. 2C to FIG. 2G since the second plate of the capacitor composed of the gate insulating layer and the gate metal film is formed only on the polysilicon storage capacitor 3, it is not in FIGS. 2C to 2G.
  • the only subsequent photolithography process of the polysilicon storage capacitor 3 is shown, that is, the photolithography process of forming the second plate of the capacitor.
  • the photoresist 5 on the polysilicon active layer 4 is removed by a photoresist stripping process, and a SiO 2 film or a composite film of SiO 2 and SiN is deposited by PECVD, in a polysilicon storage capacitor 3, a polysilicon active layer. 4 and a gate insulating layer 6 is formed on the entire buffer layer 2.
  • One or more low-resistance metal material thin films are deposited on the gate insulating layer 6 by a physical vapor deposition method such as magnetron sputtering, and the gate electrode 7 is formed by a photolithography process.
  • the polysilicon active layer 4 is ion doped using the gate electrode 7 as an ion implantation blocking layer, and a low impedance source electrode and drain electrode contact region is formed in the polysilicon active layer region not blocked by the gate.
  • an SiO 2 film and a SiN film are sequentially deposited by PECVD to form an interlayer insulating layer 8 on the entire surface including the gate electrode 7, and the interlayer insulating layer 8 is etched by a mask and an etching process to form a source electrode.
  • drain electrodes contact holes 15 and 16.
  • the interlayer insulating layer 8 and the source and drain electrodes are contacted by magnetron sputtering.
  • One or more low-resistance metal thin films are deposited on the holes 15 and 16, and the source electrode 9 and the drain electrode 10 are formed through a mask and an etching process.
  • the source electrode 9 and the drain electrode 10 pass through the contact holes 15, 16 and the polysilicon.
  • the source layer 4 forms an ohmic contact.
  • the ions doped in the polysilicon active layer 4 are activated using rapid thermal annealing or heat treatment furnace annealing to form an effective conductive channel in the polysilicon active layer 4 under the gate 7.
  • a SiN film is deposited on the entire surface including the source electrode 9 and the drain electrode 10 by PECVD, and a passivation layer 11 including via holes 17 is formed through a mask and an etching process.
  • the hydrogenation process is performed using rapid thermal annealing or heat treatment furnace annealing to repair defects in the inside and interface of the polysilicon active layer 4.
  • an organic planarization layer 18 having the same via holes as the via holes 17 is formed over the SiN passivation layer 11 by a mask process, and the depressions filling the surface of the device form a flat surface.
  • a transparent conductive film is deposited on the organic planarization layer 18 and the via 17 by magnetron sputtering, and the transparent conductive film is etched in the via hole 17 and a portion of the organic planarization layer by a photolithography process.
  • a pixel electrode 12 of a pixel region is formed on top of 18, and then a photosensitive organic material similar to the organic planarization layer 18 is coated on the organic planarization layer 18 and the pixel electrode 12, and the pixel electrode 12 is exposed through a final mask process.
  • a partial region forms the pixel defining layer 13 shown in FIG. 1, and the pixel defining layer 13 covers the organic planarizing layer 18 and a portion of the pixel electrode 12 region.
  • At least 8 to 9 photolithography processes are required to form the low temperature polysilicon thin film field effect transistor array substrate shown in FIG. 1, including a polysilicon active layer, a storage capacitor doping, a gate, and an interlayer by a photolithography process.
  • Insulating layer contact holes, source and drain electrodes, passivation layer vias, planarization layers, pixel electrodes, and pixel definition layers result in longer process times and lower process yields, resulting in complex fabrication processes and fabrication costs Higher.
  • one of the objectives of the present disclosure is to provide a low temperature polysilicon thin film field effect transistor array substrate and a method for fabricating the same, to reduce the number of photolithography processes of a low temperature polysilicon thin film field effect transistor array substrate, thereby improving process yield and Reduce the cost of the process.
  • a method of fabricating a low temperature polysilicon thin film field effect transistor array substrate comprising the steps of:
  • the electrode layer is subjected to a patterning process to form a pattern of interlayer insulating layer via holes and pixel electrodes by one photolithography process;
  • the step a) comprises: cleaning the substrate, sequentially depositing a SiN film and a SiO 2 film on the surface of the substrate, the SiN film and the SiO 2 film forming a buffer layer; depositing a layer of amorphous silicon on the buffer layer The film, the amorphous silicon film is subjected to a dehydrogenation process, and the amorphous silicon film is subjected to a crystallization process to form a polysilicon film; the polysilicon film is cleaned, and a semi-transparent reticle is used to form a first thickness of two different thicknesses on the surface of the polysilicon film.
  • the glue forms a polysilicon active layer and a polysilicon storage capacitor lower plate simultaneously on the substrate.
  • the thickness of the SiN film constituting the buffer layer is 50 nm to 100 nm, and the thickness of the SiO 2 film is 100 nm to 400 nm; the thickness of the amorphous silicon film deposited on the buffer layer is 40 nm to 100 nm;
  • the amorphous silicon film is subjected to a dehydrogenation process to prevent hydrogen explosion during crystallization; the amorphous silicon film is crystallized by laser annealing crystallization, metal induced crystallization or solid phase crystallization; wherein the semi-transparent reticle is A halftone or gray tone reticle having a thickness of between 1 micrometer and 3 micrometers overlying a region of the polysilicon film for forming a polysilicon active layer, the second photoresist having a thickness of 0.5 micron Between 1 micron, covering the area of the polysilicon film for forming the lower plate of the polysilicon storage capacitor; etching the polysilicon film by plasma or inductively coupled plasma method;
  • a gate insulating layer is formed on the polysilicon active layer and the polysilicon storage capacitor lower plate by a plasma enhanced chemical vapor deposition (PECVD) method, the gate insulating layer being composed of a SiO 2 film and The SiN film is formed, and the SiN film is formed on the SiO 2 film, the thickness of the SiO 2 film is 30 nm to 100 nm, and the thickness of the SiN film is 20 nm to 100 nm.
  • PECVD plasma enhanced chemical vapor deposition
  • the step of forming a metal layer on the gate insulating layer comprises: depositing a metal film having a thickness of 200 nm to 500 nm on the gate insulating layer by a magnetron sputtering method, Then, the metal film in the regions other than the gate, the gate line, the source electrode, the drain electrode and the data line is removed by photolithography and etching processes to form a gate electrode and a gate line connected to the gate electrode, the source electrode, the drain electrode and the source electrode The data line connected to the drain electrode and the upper plate of the polysilicon storage capacitor are simultaneously formed.
  • the metal thin film is a single-layer metal thin film formed of a metal material of Al, Cu, Mo, Ti or AlNd, or a multilayer metal thin film formed of Mo/Al/Mo or Ti/Al/Ti;
  • the data line connected to the source electrode and the drain electrode is composed of a continuous linear metal film, and the gate line is composed of a discontinuous linear metal film, and the gate line is disconnected at the intersection with the data line
  • the step of etching the metal layer is performed by a wet etching or a dry etching process; the gate insulating layer formed on the lower plate of the polysilicon storage capacitor, the lower plate of the polysilicon storage capacitor, and the lower end of the polysilicon storage capacitor
  • the board constitutes a polysilicon storage capacitor.
  • the step d) comprises: depositing a dielectric film on the gate, the source electrode, the drain electrode, the metal gate line and the data line by PECVD to form a passivation layer, and then performing a rapid thermal annealing or a heat treatment furnace annealing process;
  • the SiN film in the passivation layer and the gate insulating layer is used to realize the hydrogenation of the polysilicon active layer and the interface between the polysilicon film and the SiO 2 film;
  • the semi-transparent reticle is used to form two different thicknesses on the surface of the passivation layer.
  • a third photoresist and a fourth photoresist wherein the thickness of the third photoresist is greater than the thickness of the fourth photoresist; and the gate insulating layer under the passivation layer and the passivation layer is performed by plasma or inductively coupled plasma method Etching to form a passivation layer via; removing the fourth photoresist while leaving the third photoresist as a lift-off layer; passivation layer via, third photoresist, passivation layer, source electrode, drain electrode And depositing a transparent conductive film on the surface of the entire substrate; and removing the third photoresist and the transparent conductive film deposited thereon by using a lift-off process, while leaving the passivation layer via and the source electrode, the drain electrode and the pixel region passivated A transparent conductive film over the layer film forms a source electrode and a pixel electrode.
  • the passivation layer is a SiN film containing hydrogen having a thickness between 200 nm and 500 nm; the semi-transparent reticle is a halftone or gray tone reticle; and the third photoresist has a thickness of 1 micron.
  • the fourth photoresist The thickness is between 0.5 micrometers and 1 micrometer, covering the drain electrode and the adjacent pixel region; when the low temperature polysilicon thin film field effect transistor array adopts a bottom emission active matrix organic light emitting diode (AMOLED), the passivation layer
  • the via, the third photoresist, the passivation layer, the source electrode, the drain electrode, and the transparent conductive film deposited on the entire substrate surface are oxide transparent conductive films, including at least indium tin oxide, indium zinc oxide or tin oxide aluminum, and have a thickness of 20 nm to 100 nm; when the low temperature polysilicon thin film field effect transistor array adopts a top emission AMOLED, the transparent deposition on the passivation layer via, the third photoresist, the passivation layer, the source electrode, the drain electrode, and the entire substrate surface Conduct
  • AMOLED active matrix organic light emitting diode
  • the passivation layer via process while performing the passivation layer via process, the conductive film deposition and the lift-off process, forming a conductive film connecting the broken gate lines at the broken gate line bridge, completing the fabrication of the entire array data line;
  • the passivation layer via process at the gate line is performed simultaneously with the passivation layer via process at the source and drain electrodes, and the deposition and lift-off process of the gate line connection conductive film and the pixel electrode deposition and lift-off process are simultaneously performed.
  • the pixel defining layer formed on the pixel electrode is made of a acryl material and has a thickness of 1 micrometer to 4 micrometers.
  • Step e) includes: after forming the pixel defining layer on the pixel electrode, further annealing the low temperature polysilicon thin film field effect transistor array substrate by using a rapid thermal annealing or heat treatment furnace to stabilize the characteristics of the low temperature polysilicon thin film transistor.
  • a low temperature polysilicon thin film field effect transistor array substrate prepared by the above method.
  • the gate, the source electrode and the drain electrode are prepared using the same layer of metal.
  • the same transparent conductive film for depositing the pixel electrodes connects the respective gate lines through the via holes.
  • the same transparent conductive film for depositing the pixel electrode also connects the drain electrode to the active layer.
  • a display device comprising the above-described low temperature polysilicon thin film field effect transistor array substrate.
  • FIG. 1 is a schematic view of a conventional low temperature polysilicon thin film field effect transistor array substrate.
  • 2A-2G are process flow diagrams of a conventional low-temperature polysilicon thin film field effect transistor array substrate shown in FIG. 1.
  • FIG. 3 is a flow chart of a method for preparing a low temperature polysilicon thin film field effect transistor array substrate provided by the present disclosure.
  • 4A-4H are process flow diagrams for preparing a low temperature polysilicon thin film field effect transistor array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a low temperature polysilicon thin film field effect transistor array substrate prepared in accordance with FIGS. 4A to 4H.
  • the present disclosure provides a method of fabricating a low temperature polysilicon thin film field effect transistor array substrate using three process technologies That is, the semi-transparent reticle mask process, the film stripping process, and the gate (gate line) and the source electrode and the drain electrode (data line) are deposited in the same layer, so that the lithography process for preparing the low-temperature polysilicon film field effect transistor array substrate The number of times dropped to 4 times.
  • a photoresist film of two different thicknesses is formed by using a semi-transparent reticle mask process, first performing polysilicon etching to form a polysilicon active layer and a polysilicon storage capacitor; and then removing the thinner a photoresist film, while retaining a thicker photoresist film as an ion implantation barrier layer of the polysilicon active layer, performing ion implantation to form a polysilicon storage capacitor, thereby doping the prior art polysilicon etching and storage capacitors
  • the lithography process is combined into one.
  • a metal thin film is deposited on the gate insulating film, and a gate/gate line, and a source electrode and a drain electrode/data line are simultaneously formed by one photolithography process, and the gate electrode and the source electrode and the drain electrode of the prior art are respectively The lithography process is reduced to one time.
  • a photoresist film of two different thicknesses is formed by using a semi-transparent reticle mask process, first etching to form a passivation layer via hole; then removing a thin pixel region a photoresist film, a transparent conductive film is deposited, and a thick photoresist film and a transparent conductive film thereon are removed by a film stripping process to form a pixel electrode, thereby passing the passivation layer of the prior art.
  • the two photolithography processes of the pixel electrode are combined into one.
  • the last photolithography process forms a pixel definition layer, and the prepared low temperature polysilicon film field effect transistor array substrate can be used for the fabrication of AMOLED.
  • FIG. 3 is a flow chart of a method for preparing a low temperature polysilicon thin film field effect transistor array substrate provided by the present disclosure, the method comprising the following steps:
  • Step 10 using a step-type photoresist process, simultaneously forming a polysilicon active layer and a polysilicon storage capacitor lower plate on the substrate by one photolithography process;
  • Step 20 forming a gate insulating layer on the polysilicon active layer and the polysilicon storage capacitor lower plate;
  • Step 30 forming a metal layer on the gate insulating layer, etching the metal layer to form a gate and a gate line connected to the gate, a source electrode, a drain electrode, and a data line connected to the source and drain electrodes;
  • Step 40 sequentially forming a passivation layer, a photoresist layer, and a pixel on the etched metal layer Electrode layer, using a step mask process and a lift-off technique, patterning the passivation layer, the photoresist layer and the pixel electrode layer, forming a pattern of interlayer insulating layer via holes and pixel electrodes by one photolithography process ;
  • Step 50 Form a pixel defining layer on the pixel electrode to complete preparation of a low temperature polysilicon thin film field effect transistor array substrate.
  • the substrate 1 is initially cleaned to remove the impurity particles on the surface of the substrate 1, and then a SiN film and a SiO 2 film are sequentially deposited on the surface of the substrate by PECVD.
  • the SiN film and the SiO 2 film form a buffer layer. 2, wherein the thickness of the SiN film is 50 nm to 100 nm, and the thickness of the SiO 2 film is 100 nm to 400 nm.
  • the SiN film has a strong diffusion barrier property and can suppress the influence of metal ions on the polysilicon film on the buffer layer 2.
  • the excellent interface between the SiO 2 film and the polysilicon film can prevent the defects of the SiN film from damaging the quality of the polysilicon film.
  • an amorphous silicon (a-Si) film having a thickness of 40 nm to 100 nm is continuously deposited on the buffer layer 2 by PECVD, and the a-Si film is subjected to a dehydrogenation process in a heat treatment furnace to prevent hydrogen during crystallization. burst. Then, the a-Si film is subjected to a crystallization process by laser annealing crystallization, metal induced crystallization or solid phase crystallization to form a polysilicon film 19 as shown in FIG. 4A. Next, the polysilicon film 19 is cleaned with diluted hydrofluoric acid to reduce the surface roughness of the polysilicon film 19.
  • a-Si amorphous silicon
  • Two different thicknesses of the first photoresist 5a and the second photoresist 5b are formed on the surface of the polysilicon film 19 by using a semi-transparent reticle, and the semi-transparent reticle may be a half-tone mask or a gray a gray-tone mask, the first photoresist 5a has a thickness of between 1 micrometer and 3 micrometers, covering a region of the polysilicon film 19 for forming the polysilicon active layer 4, and the second photoresist 5b The thickness is between 0.5 ⁇ m and 1 ⁇ m, covering the region of the polysilicon film 19 for forming the polysilicon storage capacitor lower plate 3.
  • the polysilicon film 19 is etched by a plasma or inductively coupled plasma method to form a thin film for constituting the polysilicon active layer 4 and a thin film for constituting the polysilicon storage capacitor lower plate 3.
  • the second photoresist 5b is then removed by a plasma ashing process, leaving the first photoresist 5a as an ion implantation barrier.
  • the film used to form the lower plate 3 of the polysilicon storage capacitor is ion-doped by ion implantation or ion cloud implantation, and the doping ions are generally PH 3 /H 2 or B 2 H 6 /H 2 , ion implantation dose.
  • the implantation energy is between 10 keV and 100 keV between 10 14 ions/cm 2 and 10 16 ions/cm 2 .
  • the residual first photoresist 5a is removed by a plasma etching machine or a stripper to form a polysilicon active layer 4 and a polysilicon storage capacitor lower plate 3. Then, a rapid thermal annealing process is applied to the polysilicon active layer 4 to activate the doping ions to enhance the conductive characteristics of the polysilicon active layer 4.
  • a dielectric film is formed on the polysilicon active layer 4, the polysilicon storage capacitor lower plate 3, and the exposed buffer layer 2 by PECVD to form a gate insulating layer 6, which is made of SiO 2 .
  • the film and the SiN film are formed, and the SiN film is formed on the SiO 2 film, the thickness of the SiO 2 film is 30 nm to 100 nm, and the thickness of the SiN film is 20 nm to 100 nm; wherein the film is deposited on the lower plate 3 under the polysilicon storage capacitor.
  • the gate insulating layer 6 constitutes an insulating medium of the polysilicon storage capacitor; then a metal film having a thickness of 200 nm to 500 nm is deposited on the gate insulating layer 6 by magnetron sputtering, and the metal film may be Al, Cu, Mo, Ti. Or an AlNd single-layer metal material, which may also be a multilayer metal film such as Mo/Al/Mo or Ti/Al/Ti.
  • a metal thin film of a region other than the gate, the gate line, the source electrode, the drain electrode and the data line is removed by a photolithography process and etching to form a gate electrode 7 and its associated gate line (not shown), the source electrode 9, and the drain electrode
  • the pole 10 and its connected data line (not shown), and the polysilicon storage capacitor upper plate, the polysilicon storage capacitor upper plate, the polysilicon storage capacitor insulating medium, and the polysilicon storage capacitor lower plate 3 constitute a polysilicon storage capacitor.
  • the data line is composed of a continuous linear metal film
  • the gate line is composed of a discontinuous linear metal film and is disconnected at the intersection with the data line.
  • the metal etch process can be wet etch, or dry etch, such as inductively coupled plasma etch.
  • a passivation layer 11 is formed by depositing a dielectric film on the gate 7, source electrode 9, drain electrode 10, and metal gate lines and data lines by PECVD.
  • the passivation layer 11 is generally 200 nm thick.
  • a rapid thermal annealing or a heat treatment furnace annealing process is performed, and the SiN film in the passivation layer 11 and the gate insulating layer 6 is used to realize hydrogenation at the interface between the polysilicon active layer 4 and the polysilicon film and the SiO 2 film, thereby overcoming the passivation body. Defects and interface defects improve the transistor characteristics of the polysilicon film.
  • the third photoresist 5c and the fourth photoresist 5d are formed on the surface of the passivation layer by using a semi-transparent reticle, and the semi-transparent reticle may be a half-tone mask or a gray a gray-tone mask, the thickness of the third photoresist 5c is between 1 micrometer and 3 micrometers, covering the gate electrode 7 and its connected gate lines, the source electrode 9 and its connected data lines, and
  • the fourth photoresist 5d has a thickness of between 0.5 ⁇ m and 1 ⁇ m across the passivation layer via 20 and all regions except the fourth photoresist 5d, covering the drain electrode 10 and adjacent pixel regions.
  • the SiN film is etched by plasma or an inductively coupled plasma method to form a passivation layer via 20.
  • the thinner fourth photoresist 5d is removed by a plasma ashing process while the third photoresist 5c is left as a lift-off layer.
  • a transparent conductive film 12a is deposited on the passivation layer via 20, the third photoresist 5c, the passivation layer 11, the source electrode 9, the drain electrode 10, and the entire substrate surface by magnetron sputtering.
  • the transparent conductive film 12a is generally an oxide transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or tin oxide aluminum (ZTO), and has a thickness of 20 nm to 100 nm.
  • the transparent conductive film 12a is generally a composite film of ITO/Ag/ITO, IZO/Ag, the ITO has a thickness of 10 nm to 50 nm, and the Ag metal film has a thickness of 20 nm to 100 nm.
  • the substrate on which the transparent conductive film 12a is deposited is placed in a stripper, and the residual third photoresist 5c shown in FIG. 4F is removed by using a photoresist stripping solution, and the transparent deposited on the third photoresist 5c is simultaneously removed by a lift-off process.
  • the conductive film 12a retains the passivation layer via 20 and the source electrode 9, the drain electrode 10, and the transparent conductive film 12a over the pixel region passivation layer film, forming the source electrode 9a and the pixel electrode 12 as shown in FIG. 4G.
  • the conductive film 14 connecting the interrupted gate lines 7a is formed at the intermittent gate line bridge as shown in FIG. 4H, and the entire array data line is completed. Production.
  • the passivation layer via process at the gate line 7a is performed simultaneously with the passivation layer via process at the source electrode and the drain electrode shown in FIG. 4G, and the deposition and lift-off process of the gate line connection conductive film 14 and the pixel shown in FIG. 4G The deposition and stripping process of the electrode 12 is also completed at the same time.
  • a masking process of the pixel defining layer is performed on the array substrate to form a pixel defining layer 13 as shown in FIG. 5, and the preparation of the low temperature polysilicon thin film field effect transistor array substrate is completed.
  • the pixel defining layer may be made of the same material as the planarizing layer, such as Acrylic, etc., and has a thickness of 1 ⁇ m to 4 ⁇ m.
  • the final annealing process is performed on the completed array substrate by using a rapid thermal annealing or heat treatment furnace to stabilize the characteristics of the low temperature polysilicon thin film transistor.
  • the structure of the low-temperature polysilicon thin film field effect transistor array substrate is improved, and semi-transparent is adopted.
  • Masking mask process, film stripping process and gate (gate line) and source electrode and drain electrode (data line) deposition in the same layer, the number of photolithography processes for preparing low temperature polysilicon film field effect transistor array substrate The number of lithography processes of the low-temperature polysilicon thin film field effect transistor array substrate is reduced to four times, thereby achieving the purpose of improving the process yield and reducing the process cost.
  • the step photoresist process and the lift-off technology are used to reduce the number of exposures in the preparation process of the low-temperature polysilicon thin film field effect transistor array substrate, thereby Reduced process complexity, reduced process time while reducing process costs.
  • the present disclosure also provides a low temperature polysilicon thin film field effect transistor array substrate prepared by the method shown in FIGS. 4A to 4H, wherein FIG. 5 shows the low temperature prepared according to FIGS. 4A to 4H.
  • Schematic diagram of a polysilicon thin film field effect transistor array substrate In the low-temperature polysilicon thin film field effect transistor array substrate, the gate, the source electrode and the drain electrode are prepared by using the same layer of metal, and the same transparent conductive film for depositing the pixel electrode connects the gate lines through the via holes. The same layer of transparent conductive film used to deposit the pixel electrode also connects the drain electrode to the active layer.
  • the gate (gate line) and the source electrode and the drain electrode (data line) are formed of the same metal thin film without isolation of the interlayer insulating layer,
  • the advantage is that the parasitic capacitance between the gate and the source and drain electrodes is reduced.
  • the same transparent electrode as the pixel electrode is used to form a source electrode and a drain electrode which are in contact with the polysilicon film, and the transparent conductive film and the low-resistance metal film are connected to reduce the impedance of the electrode and the wire, and the transparent conductive film is connected to the intermittent gate line.
  • the SiN film is used only or the organic planarization film is used as the passivation layer, or the organic planarization film is used as the pixel definition layer, which simplifies the array structure and the preparation process.
  • the low temperature polysilicon thin film field effect transistor array substrate prepared in accordance with an embodiment of the present disclosure can be used for the preparation of a low temperature polysilicon active matrix organic light emitting diode (LTPS-AMOLED).
  • LTPS-AMOLED low temperature polysilicon active matrix organic light emitting diode
  • the present disclosure also provides a display device including the low temperature polysilicon thin film field effect transistor array substrate prepared according to the foregoing embodiment.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the gate, the source electrode and the drain electrode are prepared by using the same layer of metal, and the gate, the source electrode and the drain electrode are not separated by the interlayer insulating layer, and the advantage is that the gate and the source and drain electrodes are lowered.
  • the same transparent conductive film for depositing the pixel electrode connects the respective gate lines through the via holes, and the same transparent conductive film for depositing the pixel electrodes also connects the drain electrode to the active layer, thereby reducing the electrodes and the wires. Impedance, while the transparent conductive film is connected to the intermittent gate line metal film, simplifying the array structure and fabrication process.

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Abstract

一种低温多晶硅TFT阵列基板及其制备方法、显示装置，该制备方法包括：利用台阶式光刻胶工艺，通过一次光刻工艺在基板（1）上同时形成多晶硅有源层（4）和多晶硅存储电容下极板（3）；在多晶硅有源层（4）和多晶硅存储电容下极板（3）上形成栅极绝缘层（6）；在栅极绝缘层（6）上形成金属层，刻蚀金属层形成栅极（7）及与其相连的栅线（7a），源电极（9）、漏电极（10）及与其相连的数据线（9b）；依次形成钝化层（11）、光刻胶层和像素电极层（12），并对其进行构图工艺处理，通过一次光刻工艺形成层间绝缘层过孔和像素电极图案；在像素电极上形成像素定义层（13）。减少了光刻工艺次数，提升了工艺良率，降低了成本。

Description

低温多晶硅TFT阵列基板及其制备方法、显示装置
本申请要求于2014年6月30日递交的、申请号为201410305758.6、发明名称为“低温多晶硅TFT阵列基板及其制备方法、显示装置”的中国专利申请的优先权，其全部内容通过引用并入本申请中。
技术领域
本公开涉及制备有源矩阵有机发光二极管显示器的技术领域，尤其涉及一种低温多晶硅薄膜场效应晶体管(Thin Film Transistor，TFT)阵列基板及其制备方法、具有该低温多晶硅薄膜场效应晶体管阵列基板的显示装置。
背景技术
相对于液晶显示器，有机发光二极管显示器具有反应速度快、重量轻、可弯曲和广视角等优点。而有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)更具有驱动电流小和功耗低的优势，适合于高解析度显示器。有源矩阵有机发光二极管架构可使用非晶硅、多晶硅、氧化物半导体或有机薄膜晶体管驱动。其中，非晶硅或有机薄膜晶体管的载流子迁移率与驱动电流小，因此驱动高亮度有机发光二极管所需的电压较高且器件也较大。而低温多晶硅具有高达100cm2/V-s的迁移率，其高电流特性正好符合有机发光二极管严格的要求，低操作电压与高密度的驱动架构使得有机发光二极管寿命较长。有别于传统液晶显示器电压驱动的方式，有机发光二极管驱动所需为特殊电流驱动架构，而且还有为了克服灰阶与面板均匀性所涉及的补偿电路。而且往往在同一像素中需要2～6个薄膜晶体管，而低温多晶硅高密度的布局特点，使得高亮度与高画质的有机发光二极管面板更容易实现。目前成功商业化生产的AMOLED绝大部分是使用低温多晶硅薄膜场效应晶体管阵列基板。
图1是现有的低温多晶硅薄膜场效应晶体管阵列基板的示意图。在传统的低温多晶硅薄膜场效应晶体管阵列基板的制备工艺中，一般需要8～9 道掩模工序，导致制备工艺比较复杂。以下参照图2A～图2G，对图1所示的现有低温多晶硅薄膜场效应晶体管阵列基板的制备工艺进行说明。
如图2A所示，通过等离子体增强化学气相沉积(PECVD)，在整个绝缘基板1上依次沉积氮化硅(SiN)薄膜和二氧化硅(SiO2)薄膜，形成氮化硅和二氧化硅构成的缓冲层2。接着利用PECVD或者其它化学或物理气相沉积方法在缓冲层2上形成非晶硅(a-Si)薄膜。通过激光退火(ELA)或者固相结晶(SPC)方法，使得a-Si结晶成为多晶硅薄膜。然后采用传统掩模工艺在多晶硅薄膜上形成光刻胶层的图案，以光刻胶层为刻蚀阻挡层，通过等离子体刻蚀没有被光刻胶层保护的多晶硅薄膜，形成多晶硅有源层4和多晶硅存储电容3。利用离子注入工艺对多晶硅有源层4中的晶体管沟道进行低浓度离子掺杂，在多晶硅有源层4中形成薄膜晶体管要求的导电沟道。
如图2B所示，通过掩模工艺在多晶硅有源层4上形成光阻材料组成的光刻胶5，以保护多晶硅有源层4不被离子注入。对没有光刻胶层保护的多晶硅存储电容3进行高浓度离子注入工艺，将多晶硅存储电容3转化为低电阻的掺杂多晶硅薄膜。在图2C～图2G所示的后续工艺过程中，由于只在多晶硅存储电容3上形成栅极绝缘层和栅极金属薄膜构成的电容的第二极板，因此在图2C～图2G中不再显示多晶硅存储电容3后续仅有的一次光刻工艺，即形成电容的第二极板的光刻工艺。
如图2C所示，通过光刻胶剥离工艺去除多晶硅有源层4上的光刻胶5，使用PECVD沉积SiO2薄膜或SiO2与SiN的复合薄膜，在多晶硅存储电容3、多晶硅有源层4以及整个缓冲层2上形成栅极绝缘层6。通过磁控溅射等物理气相沉积方法在栅极绝缘层6上沉积一种或者多种低电阻的金属材料薄膜，利用光刻工艺形成栅极7。使用栅极7作为离子注入阻挡层，对多晶硅有源层4进行离子掺杂，在未被栅极阻挡的多晶硅有源层区域形成低阻抗的源电极和漏极电极接触区。
如图2D所示，在包含栅极7的整个表面，使用PECVD依次沉积SiO2薄膜和SiN薄膜形成层间绝缘层8，通过掩模和刻蚀工艺刻蚀层间绝缘层8而形成源电极和漏电极接触孔15和16。
如图2E所示，使用磁控溅射在层间绝缘层8及源电极和漏电极接触 孔15和16之上沉积一种或多种低电阻的金属薄膜，通过掩模和刻蚀工艺形成源电极9和漏电极10，源电极9和漏电极10通过接触孔15、16与多晶硅有源层4形成欧姆接触。使用快速热退火或热处理炉退火，激活多晶硅有源层4中掺杂的离子，在栅极7之下的多晶硅有源层4中形成有效的导电沟道。
如图2F所示，使用PECVD在包含源电极9和漏电极10的整个表面沉积一层SiN薄膜，通过掩模和刻蚀工艺形成包含过孔17的钝化层11。使用快速热退火或热处理炉退火进行氢化工艺，修复多晶硅有源层4内部和界面的缺陷。再一次通过掩模工艺，在SiN钝化层11之上形成具有与过孔17相同的过孔的有机平坦化层18，填充器件表面的低凹形成平坦表面。
如图2G所示，使用磁控溅射在有机平坦化层18和过孔17之上沉积一层透明导电薄膜，通过光刻工艺刻蚀该透明导电薄膜在过孔17及部分有机平坦化层18之上形成像素区域的像素电极12，然后在有机平坦化层18及像素电极12上涂覆一层与有机平坦化层18类似的光敏有机材料，通过最后一道掩模工艺暴露出像素电极12的部分区域，形成图1中所示的像素定义层13，像素定义层13覆盖有机平坦化层18及部分的像素电极12区域。
综上所述，至少需要8～9道光刻工艺形成图1所示的低温多晶硅薄膜场效应晶体管阵列基板，包括通过光刻工艺实现多晶硅有源层、存储电容掺杂、栅极、层间绝缘层接触孔、源电极和漏电极、钝化层过孔、平坦化层、像素电极和像素定义层，结果导致较长的工艺时间和较低的工艺良率，使得制备工艺复杂，制备成本较高。
发明内容
有鉴于此，本公开的目的之一在于提供一种低温多晶硅薄膜场效应晶体管阵列基板及其制备方法，以减少低温多晶硅薄膜场效应晶体管阵列基板的光刻工艺次数，从而达到提升工艺良率和降低工艺成本的目的。
本公开的还一目的在于提供一种包括该低温多晶硅薄膜场效应晶体管阵列基板的显示装置。
根据本公开的一个方面，提供了一种制备低温多晶硅薄膜场效应晶体管阵列基板的方法，包括步骤：
a)利用台阶式光刻胶工艺，通过一次光刻工艺在基板上同时形成多晶硅有源层和多晶硅存储电容下极板；
b)在所述多晶硅有源层和多晶硅存储电容下极板上形成栅绝缘层；
c)在所述栅极绝缘层上形成金属层，刻蚀该金属层形成栅极及与栅极相连的栅线，源电极、漏电极及与源电极、漏电极相连的数据线；
d)在所述刻蚀后的金属层上依次形成钝化层、光刻胶层和像素电极层，利用台阶式掩模工艺和剥离技术，对所述钝化层、光刻胶层和像素电极层进行构图工艺处理，通过一次光刻工艺形成层间绝缘层过孔和像素电极的图案；
e)在所述像素电极上形成像素定义层，完成低温多晶硅薄膜场效应晶体管阵列基板的制备。
优选地，所述步骤a)包括：清洗基板，在基板表面依次沉积一层SiN薄膜和一层SiO2薄膜，该SiN薄膜和SiO2薄膜构成缓冲层；在缓冲层上沉积一层非晶硅薄膜，对该非晶硅薄膜进行脱氢工艺处理，并对非晶硅薄膜进行结晶工艺，形成多晶硅薄膜；清洗多晶硅薄膜，采用半透式掩模版在多晶硅薄膜表面形成两种不同厚度的第一光刻胶和第二光刻胶，且第一光刻胶的厚度大于第二光刻胶的厚度；对多晶硅薄膜进行刻蚀，形成用于构成多晶硅有源层的薄膜和用于构成多晶硅存储电容下极板的薄膜，接着去除第二光刻胶，保留第一光刻胶作为离子注入阻挡层，对用于构成多晶硅存储电容下极板的薄膜进行离子掺杂，然后去除第一光刻胶，在基板上同时形成多晶硅有源层和多晶硅存储电容下极板。
优选地，所述构成缓冲层的SiN薄膜的厚度为50nm～100nm，SiO2薄膜的厚度为100nm～400nm；所述在缓冲层上沉积的非晶硅薄膜厚度为40nm～100nm；采用热处理炉对该非晶硅薄膜进行脱氢工艺处理，用以防止结晶过程中的氢爆；采用激光退火结晶、金属诱导结晶或固相结晶方法对非晶硅薄膜进行结晶工艺；其中半透式掩模版是半色调或灰色调掩模版，第一光刻胶的厚度在1微米～3微米之间，覆盖在多晶硅薄膜的用于形成多晶硅有源层的区域上，第二光刻胶的厚度在0.5微米～1微米之间，覆盖在 多晶硅薄膜的用于形成多晶硅存储电容下极板的区域上；采用等离子体或电感耦合等离子方法对多晶硅薄膜进行刻蚀；采用等离子体灰化工艺去除第二光刻胶并且保留第一光刻胶作为离子注入阻挡层；采用离子注入或离子云注入的方法对用于构成多晶硅存储电容下极板的薄膜进行离子掺杂，掺杂离子为PH3/H2或B2H6/H2，离子注入剂量在1014ions/cm2～1016ions/cm2之间，注入能量在10KeV～100KeV之间。
优选地，在步骤b)中，采用等离子体增强化学气相沉积(PECVD)方法在所述多晶硅有源层和多晶硅存储电容下极板上形成栅绝缘层，该栅极绝缘层由SiO2薄膜和SiN薄膜构成，且SiN薄膜形成在SiO2薄膜之上，SiO2薄膜的厚度为30nm～100nm，SiN薄膜的厚度为20nm～100nm。所述在多晶硅存储电容下极板之上沉积的栅极绝缘层用以构成多晶硅存储电容的绝缘介质。
优选地，在步骤c)中，所述在所述栅极绝缘层上形成金属层的步骤包括：采用磁控溅射方法在栅极绝缘层上沉积一层厚度为200nm～500nm的金属薄膜，然后通过光刻和刻蚀工艺去除栅极、栅线、源电极、漏电极和数据线以外区域的金属薄膜，形成栅极及与栅极相连的栅线，源电极、漏电极及与源电极、漏电极相连的数据线，以及同时形成多晶硅存储电容上极板。
优选地，所述金属薄膜是由金属材料Al、Cu、Mo、Ti或AlNd形成的单层金属薄膜，或者是由Mo/Al/Mo或Ti/Al/Ti形成的多层金属薄膜；所述与源电极、漏电极相连的数据线由连续线状的金属薄膜构成，而所述栅线由不连续线状的金属薄膜构成，且所述栅线在与所述数据线的交叉处断开；所述刻蚀该金属层的步骤是采用湿法腐蚀或干法腐蚀工艺实现；所述多晶硅存储电容下极板、多晶硅存储电容下极板上形成的栅极绝缘层和多晶硅存储电容下极板构成多晶硅存储电容。
优选地，所述步骤d)包括：采用PECVD在栅极、源电极、漏电极以及金属栅线和数据线上沉积一层介质薄膜而形成钝化层，然后进行快速热退火或热处理炉退火工艺，利用钝化层和栅极绝缘层中的SiN薄膜，实现多晶硅有源层内部以及多晶硅薄膜与SiO2薄膜界面的氢化；采用半透式掩模版在钝化层表面形成两种不同厚度的第三光刻胶和第四光刻胶，第三 光刻胶的厚度大于第四光刻胶的厚度；采用等离子体或电感耦合等离子方法对钝化层及钝化层下的栅极绝缘层进行刻蚀，形成钝化层过孔；去除第四光刻胶，而保留第三光刻胶作为剥离层；在钝化层过孔、第三光刻胶、钝化层、源电极、漏电极以及整个基板表面沉积一层透明导电薄膜；以及采用剥离工艺同时去除第三光刻胶及其上沉积的透明导电薄膜，而保留钝化层过孔以及源电极、漏电极和像素区域钝化层薄膜之上的透明导电薄膜，形成源电极和像素电极。
优选地，所述钝化层是厚度在200nm～500nm之间含氢的SiN薄膜；所述半透式掩模版是半色调或灰色调掩模版；所述第三光刻胶的厚度在1微米～3微米之间，覆盖栅极及其相连的栅线、源电极及其相连的数据线、以及除钝化层过孔和第四光刻胶以外的所有区域；所述第四光刻胶的厚度在0.5微米～1微米之间，覆盖漏电极以及相邻的像素区域；当该低温多晶硅薄膜场效应晶体管阵列采用底发射有源矩阵有机发光二极管(AMOLED)时，所述在钝化层过孔、第三光刻胶、钝化层、源电极、漏电极以及整个基板表面沉积的透明导电薄膜是氧化物透明导电薄膜，至少包括氧化铟锡、氧化铟锌或氧化锡铝，厚度为20nm～100nm；当该低温多晶硅薄膜场效应晶体管阵列采用顶发射AMOLED时，所述在钝化层过孔、第三光刻胶、钝化层、源电极、漏电极以及整个基板表面沉积的透明导电薄膜是复合薄膜，至少包括ITO/Ag/ITO和IZO/Ag，其中ITO厚度为10nm～50nm，Ag金属薄膜厚度为20nm～100nm。
优选地，在进行所述钝化层过孔工艺、导电薄膜沉积和剥离工艺的同时，在断续栅线搭桥处形成连接断续栅线的导电薄膜，完成整个阵列数据线的制作；所述栅线处的钝化层过孔工艺与所述源漏电极处钝化层过孔工艺同时进行，栅线连接导电薄膜的沉积和剥离工艺与所述像素电极沉积、剥离工艺也是同时进行的。
优选地，在步骤e)中，所述在像素电极上形成的像素定义层采用的材料是亚克力材料，厚度是1微米～4微米。步骤e)包括：在像素电极上形成像素定义层后，进一步对低温多晶硅薄膜场效应晶体管阵列基板采用快速热退火或热处理炉进行退火处理，以稳定低温多晶硅薄膜晶体管的特性。
根据本公开的另一个方面，还提供了一种利用上述方法制备的低温多晶硅薄膜场效应晶体管阵列基板。
优选地，在该低温多晶硅薄膜场效应晶体管阵列基板中，栅极、源电极和漏电极是采用同一层金属制备的。
优选地，在该低温多晶硅薄膜场效应晶体管阵列基板中，用于沉积像素电极的同一层透明导电薄膜通过过孔将各条栅线连接起来。
优选地，在该低温多晶硅薄膜场效应晶体管阵列基板中，用于沉积像素电极的同一层透明导电薄膜还将漏电极与有源层连接起来。
根据本公开的再一个方面，还提供了一种显示装置，该显示装置包括上述的低温多晶硅薄膜场效应晶体管阵列基板。
附图说明
图1是现有的低温多晶硅薄膜场效应晶体管阵列基板的示意图。
图2A～图2G是现有的制备图1所示低温多晶硅薄膜场效应晶体管阵列基板的工艺流程图。
图3是本公开提供的制备低温多晶硅薄膜场效应晶体管阵列基板的方法流程图。
图4A～图4H是依照本公开实施例的制备低温多晶硅薄膜场效应晶体管阵列基板的工艺流程图。
图5是依照图4A～图4H制备的低温多晶硅薄膜场效应晶体管阵列基板的示意图。
附图标记：1、基板；2、缓冲层；3、多晶硅存储电容；4、多晶硅有源层；5、光刻胶；5a、5c、全厚度光刻胶；5b、5d、半厚度光刻胶；6、栅极绝缘层；7、栅极；7a、栅线；8、层间绝缘层；9、源电极；9a、源接触电极；9b、数据线10、漏电极；11、钝化层；12、像素电极；12a、残留像素电极薄膜(透明导电薄膜)；13、像素定义层；14、栅线线连接导电薄膜；15、源电极接触孔；16、漏电极接触孔；17、过孔；18、有机平坦化层；19、多晶硅薄膜；20、钝化层过孔。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
根据本公开的一个方面，为了减少制备低温多晶硅薄膜场效应晶体管阵列基板工艺的光刻次数，本公开提供了一种制备低温多晶硅薄膜场效应晶体管阵列基板的方法，该方法采用了三种工艺技术，即：半透式掩模版掩模工艺、薄膜剥离工艺以及栅极(栅线)和源电极、漏电极(数据线)同层沉积，使得制备低温多晶硅薄膜场效应晶体管阵列基板的光刻工艺次数下降到4次。其中，在多晶硅薄膜光刻工艺中，采用半透式掩模版掩模工艺，形成两种不同厚度的光刻胶薄膜，首先进行多晶硅刻蚀形成多晶硅有源层和多晶硅存储电容；然后去除较薄的光刻胶薄膜，而保留较厚的光刻胶薄膜作为多晶硅有源层的离子注入阻挡层，进行离子注入形成多晶硅存储电容，由此将原有技术的多晶硅刻蚀和存储电容掺杂两道光刻工艺合二为一。在栅极绝缘薄膜之上沉积一层金属薄膜，通过一次光刻工艺同时形成栅极/栅线、以及源电极和漏电极/数据线，将现有技术的栅极和源电极、漏电极两道光刻工艺减少到一次。在钝化层过孔光刻工艺中，使用半透式掩模版掩模工艺，形成两种不同厚度的光刻胶薄膜，首先进行刻蚀形成钝化层过孔；然后去除像素区域较薄的光刻胶薄膜，沉积一层透明导电薄膜，使用薄膜剥离工艺去除较厚的光刻胶薄膜及其之上的透明导电薄膜，形成像素电极，由此将原有技术的钝化层过孔和像素电极两道光刻工艺合二为一。最后一道光刻工艺形成像素定义层，制备完成的低温多晶硅薄膜场效应晶体管阵列基板可以用于AMOLED的制作。
如图3所示，图3是本公开提供的制备低温多晶硅薄膜场效应晶体管阵列基板的方法流程图，该方法包括以下步骤：
步骤10：利用台阶式光刻胶工艺，通过一次光刻工艺在基板上同时形成多晶硅有源层和多晶硅存储电容下极板；
步骤20：在所述多晶硅有源层和多晶硅存储电容下极板上形成栅极绝缘层；
步骤30：在所述栅极绝缘层上形成金属层，刻蚀该金属层形成栅极及与栅极相连的栅线，源电极、漏电极及与源漏电极相连的数据线；
步骤40：在所述刻蚀后的金属层上依次形成钝化层、光刻胶层和像素 电极层，利用台阶式掩模工艺和剥离技术，对所述钝化层、光刻胶层和像素电极层进行构图工艺处理，通过一次光刻工艺形成层间绝缘层过孔和像素电极的图案；
步骤50：在所述像素电极上形成像素定义层，完成低温多晶硅薄膜场效应晶体管阵列基板的制备。
基于图3所示的制备低温多晶硅薄膜场效应晶体管阵列基板的方法流程图，以下参照图4A～图4H详细说明依照本公开实施例的低温多晶硅薄膜场效应晶体管阵列基板的制备工艺。
如图4A所示，对基板1进行初始清洗以清除基板1表面的杂质粒子，然后采用PECVD在基板表面依次沉积一层SiN薄膜和一层SiO2薄膜，该SiN薄膜和SiO2薄膜构成缓冲层2，其中SiN薄膜的厚度为50nm～100nm，SiO2薄膜的厚度为100nm～400nm。SiN薄膜具有很强的扩散阻挡特性，可以抑制金属离子对缓冲层2上多晶硅薄膜的影响。SiO2薄膜与多晶硅薄膜之间具有优良的界面，可以防止SiN薄膜的缺陷对多晶硅薄膜质量的损害。接着采用PECVD在缓冲层2上连续沉积一层厚度在40nm～100nm的非晶硅(a-Si)薄膜，采用热处理炉对该a-Si薄膜进行脱氢工艺处理，以防止结晶过程中的氢爆。然后采用激光退火结晶、金属诱导结晶或固相结晶等方法对a-Si薄膜进行结晶工艺，形成如图4A所示的多晶硅薄膜19。接着，采用稀释的氢氟酸对多晶硅薄膜19进行清洗，降低多晶硅薄膜19的表面粗糙度。采用一种半透式掩模版在多晶硅薄膜19表面形成两种不同厚度的第一光刻胶5a和第二光刻胶5b，半透式掩模版可以是半色调(Half-tone mask)或者灰色调掩模版(Gray-tone mask)，第一光刻胶5a的厚度在1微米～3微米之间，覆盖在多晶硅薄膜19的用于形成多晶硅有源层4的区域，第二光刻胶5b的厚度在0.5微米～1微米之间，覆盖在多晶硅薄膜19的用于形成多晶硅存储电容下极板3的区域。
如图4B所示，采用等离子体或者电感耦合等离子方法对多晶硅薄膜19进行刻蚀，形成用于构成多晶硅有源层4的薄膜和用于构成多晶硅存储电容下极板3的薄膜。然后采用等离子体灰化工艺去除第二光刻胶5b，保留第一光刻胶5a作为离子注入阻挡层。采用离子注入或者离子云注入的方法，对用于构成多晶硅存储电容下极板3的薄膜进行离子掺杂，掺杂离 子一般为PH3/H2或者B2H6/H2，离子注入剂量在1014ions/cm2～1016ions/cm2之间，注入能量在10KeV～100KeV之间。
完成离子注入后，如图4C所示，采用等离子体刻蚀机或者剥离机去除残留的第一光刻胶5a，形成多晶硅有源层4和多晶硅存储电容下极板3。然后，对多晶硅有源层4采用快速热退火工艺，激活掺杂离子，增强多晶硅有源层4的导电特性。
如图4D所示，采用PECVD在多晶硅有源层4、多晶硅存储电容下极板3及暴露的缓冲层2之上沉积介质薄膜而形成栅极绝缘层6，该栅极绝缘层6由SiO2薄膜和SiN薄膜构成，且SiN薄膜形成在SiO2薄膜之上，SiO2薄膜的厚度为30nm～100nm，SiN薄膜的厚度为20nm～100nm；其中，在多晶硅存储电容下极板3之上沉积的栅极绝缘层6构成多晶硅存储电容的绝缘介质；接着采用磁控溅射在栅极绝缘层6上沉积一层厚度为200nm～500nm的金属薄膜，该金属薄膜可以是Al、Cu、Mo、Ti或AlNd单层金属材料，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。然后通过光刻工艺和刻蚀去除栅极、栅线、源电极、漏电极和数据线以外区域的金属薄膜，形成栅极7及其相连的栅线(未示出)，源电极9、漏电极10及其相连的数据线(未示出)，以及多晶硅存储电容上极板，该多晶硅存储电容上极板、多晶硅存储电容的绝缘介质和多晶硅存储电容下极板3构成多晶硅存储电容。其中数据线由连续线状的金属薄膜构成，而栅线由不连续线状的金属薄膜构成，在与数据线的交叉处断开。金属刻蚀工艺可以是湿法腐蚀，或者干法腐蚀，如电感耦合等离子体刻蚀。
如图4E所示，采用PECVD在栅极7、源电极9、漏电极10以及金属栅线和数据线上沉积一层介质薄膜而形成钝化层11，该钝化层11一般是厚度在200nm～500nm之间含氢的SiN薄膜。而后进行快速热退火或者热处理炉退火工艺，利用钝化层11和栅极绝缘层6中的SiN薄膜，实现多晶硅有源层4内部以及多晶硅薄膜与SiO2薄膜界面的氢化，从而克服钝化体缺陷和界面缺陷，提高了多晶硅薄膜的晶体管特性。采用一种半透式掩模版在钝化层表面形成两种不同厚度的第三光刻胶5c和第四光刻胶5d，半透式掩模版可以是半色调(Half-tone mask)或者灰色调掩模版(Gray-tone mask)，第三光刻胶5c的厚度在1微米～3微米之间，覆盖栅极7及其相连 的栅线、源电极9及其相连的数据线，以及除钝化层过孔20和第四光刻胶5d以外的所有区域，第四光刻胶5d的厚度在0.5微米～1微米之间，覆盖漏电极10以及相邻的像素区域。采用等离子体或者电感耦合等离子方法进行SiN薄膜的刻蚀，形成钝化层过孔20。通过等离子体灰化工艺去除较薄的第四光刻胶5d，而保留第三光刻胶5c作为剥离层。
如图4F所示，采用磁控溅射在钝化层过孔20、第三光刻胶5c、钝化层11、源电极9、漏电极10以及整个基板表面沉积一层透明导电薄膜12a。低温多晶硅薄膜场效应晶体管阵列采用底发射AMOLED时，该透明导电薄膜12a一般是是氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锡铝(ZTO)等氧化物透明导电薄膜，厚度为20nm～100nm。低温多晶硅薄膜场效应晶体管阵列采用顶发射AMOLED时，该透明导电薄膜12a一般是ITO/Ag/ITO、IZO/Ag等复合薄膜，ITO厚度为10nm～50nm，Ag金属薄膜厚度为20nm～100nm。
把沉积完透明导电薄膜12a的基板放入剥离机中，采用光刻胶剥离液去除图4F所示残留的第三光刻胶5c，通过剥离工艺同时去除第三光刻胶5c上沉积的透明导电薄膜12a，而保留钝化层过孔20以及源电极9、漏电极10和像素区域钝化层薄膜之上的透明导电薄膜12a，形成如图4G所示的源电极9a和像素电极12。
进行上述钝化层过孔工艺、导电薄膜溅射和剥离工艺的同时，在如图4H所示的断续栅线搭桥处，形成连接断续栅线7a的导电薄膜14，完成整个阵列数据线的制作。栅线7a处的钝化层过孔工艺与图4G所示的源电极、漏电极处钝化层过孔工艺同时进行，栅线连接导电薄膜14的沉积和剥离工艺与图4G所示的像素电极12沉积、剥离工艺也是同时完成的。
最后在阵列基板上进行像素定义层的掩模工艺，形成如图5所示的像素定义层13，完成低温多晶硅薄膜场效应晶体管阵列基板的制备。像素定义层可以采用和平坦化层相同的材料，如亚克力(Acrylic)等，厚度是1微米～4微米。采用快速热退火或热处理炉，对于完成的阵列基板进行最后的退火处理，以稳定低温多晶硅薄膜晶体管的特性。
在本公开提供的制备低温多晶硅薄膜场效应晶体管阵列基板的方法中，通过改进低温多晶硅薄膜场效应晶体管阵列基板的结构，并采用半透 式掩模版掩模工艺、薄膜剥离工艺以及栅极(栅线)和源电极、漏电极(数据线)同层沉积三种工艺方法，使得制备低温多晶硅薄膜场效应晶体管阵列基板的光刻工艺次数下降到4次，减少了低温多晶硅薄膜场效应晶体管阵列基板的光刻工艺次数，从而达到提升工艺良率和降低工艺成本的目的。
此外，在本公开提供的制备低温多晶硅薄膜场效应晶体管阵列基板的方法中，采用台阶式光刻胶工艺和剥离技术，减少了低温多晶硅薄膜场效应晶体管阵列基板制备工艺过程中的曝光次数，从而降低了工序复杂度，在缩短制备工艺时间的同时降低工艺成本。
根据本公开的另一个方面，本公开还提供了一种利用图4A～图4H所示方法制备的低温多晶硅薄膜场效应晶体管阵列基板，其中图5示出了依照图4A～图4H制备的低温多晶硅薄膜场效应晶体管阵列基板的示意图。在该低温多晶硅薄膜场效应晶体管阵列基板中，栅极、源电极和漏电极是采用同一层金属制备的，用于沉积像素电极的同一层透明导电薄膜通过过孔将各条栅线连接起来，用于沉积像素电极的同一层透明导电薄膜还将漏电极与有源层连接起来。
在根据上述实施例制备的低温多晶硅薄膜场效应晶体管阵列基板中，栅极(栅线)和源电极、漏电极(数据线)由同一层金属薄膜形成，而没有层间绝缘层隔离开来，其优势是降低了栅极和源电极、漏电极之间的寄生电容。使用与像素电极相同的透明导电薄膜，形成和多晶硅薄膜接触的源电极和漏电极，透明导电薄膜和低电阻的金属薄膜相连接，降低电极和导线阻抗，同时透明导电薄膜连接了断续的栅线金属薄膜。只使用SiN薄膜或者只使用有机平坦化薄膜作为钝化层，或者使用有机平坦化薄膜作为像素定义层，简化阵列结构和制备工艺。
另外，依照本公开实施例制备的低温多晶硅薄膜场效应晶体管阵列基板可以用于低温多晶硅有源矩阵有机发光二极管(LTPS-AMOLED)的制备。
根据本公开的再一个方面，本公开还提供了一种包括根据前述实施例制备的低温多晶硅薄膜场效应晶体管阵列基板的显示装置。所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在该显示装置中，栅极、源电极和漏电极是采用同一层金属制备的，栅极、源电极和漏电极没有层间绝缘层隔离开来，其优势是降低了栅极和源漏电极之间的寄生电容。而用于沉积像素电极的同一层透明导电薄膜通过过孔将各条栅线连接起来，用于沉积像素电极的同一层透明导电薄膜还将漏电极与有源层连接起来，降低了电极和导线阻抗，同时透明导电薄膜连接了断续的栅线金属薄膜，简化阵列结构和制备工艺。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (17)

  1. 一种制备低温多晶硅薄膜场效应晶体管阵列基板的方法，包括步骤：
    a)利用台阶式光刻胶工艺，通过一次光刻工艺在基板上同时形成多晶硅有源层和多晶硅存储电容下极板；
    b)在所述多晶硅有源层和多晶硅存储电容下极板上形成栅极绝缘层；
    c)在所述栅极绝缘层上形成金属层，刻蚀该金属层形成栅极及与栅极相连的栅线，源电极、漏电极及与源电极、漏电极相连的数据线；
    d)在所述刻蚀后的金属层上依次形成钝化层、光刻胶层和像素电极层，利用台阶式掩模工艺和剥离技术，对所述钝化层、光刻胶层和像素电极层进行构图工艺处理，通过一次光刻工艺形成层间绝缘层过孔和像素电极的图案；
    e)在所述像素电极上形成像素定义层，完成低温多晶硅薄膜场效应晶体管阵列基板的制备。
  2. 根据权利要求1所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，所述步骤a)包括：
    清洗基板，在基板表面依次沉积一层SiN薄膜和一层SiO2薄膜，该SiN薄膜和SiO2薄膜构成缓冲层；
    在缓冲层上沉积一层非晶硅薄膜，对该非晶硅薄膜进行脱氢工艺处理，并对非晶硅薄膜进行结晶工艺，形成多晶硅薄膜；
    清洗多晶硅薄膜，采用半透式掩模版在多晶硅薄膜表面形成两种不同厚度的第一光刻胶(5a)和第二光刻胶(5b)，且第一光刻胶(5a)的厚度大于第二光刻胶(5b)的厚度；
    对多晶硅薄膜进行刻蚀，形成用于构成多晶硅有源层的薄膜和用于构成多晶硅存储电容下极板的薄膜，接着去除第二光刻胶(5b)，保留第一光刻胶(5a)作为离子注入阻挡层，对用于构成多晶硅存储电容下极板的薄膜进行离子掺杂，然后去除第一光刻胶(5a)，在基板上同时形成多晶硅有源层和多晶硅存储电容下极板。
  3. 根据权利要求2所述的制备低温多晶硅薄膜场效应晶体管阵列基 板的方法，其中，
    所述构成缓冲层的SiN薄膜的厚度为50nm～100nm，SiO2薄膜的厚度为100nm～400nm；
    所述在缓冲层上沉积的非晶硅薄膜的厚度为40nm～100nm；其中采用热处理炉对该非晶硅薄膜进行脱氢工艺处理；采用激光退火结晶、金属诱导结晶或固相结晶方法对非晶硅薄膜进行结晶工艺；
    所述半透式掩模版是半色调或灰色调掩模版；第一光刻胶(5a)的厚度在1微米～3微米之间，覆盖在多晶硅薄膜的用于形成多晶硅有源层的区域上；以及第二光刻胶(5b)的厚度在0.5微米～1微米之间，覆盖在多晶硅薄膜的用于形成多晶硅存储电容下极板的区域上；
    采用等离子体或电感耦合等离子方法对多晶硅薄膜进行刻蚀；采用等离子体灰化工艺去除第二光刻胶(5b)并且保留第一光刻胶(5a)作为离子注入阻挡层；采用离子注入或离子云注入的方法对用于构成多晶硅存储电容下极板的薄膜进行离子掺杂，掺杂离子为PH3/H2或B2H6/H2，离子注入剂量在1014ions/cm2～1016ions/cm2之间，注入能量在10KeV～100KeV之间。
  4. 根据权利要求1所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，在步骤b)中，采用等离子体增强化学气相沉积方法在所述多晶硅有源层和多晶硅存储电容下极板上形成栅极绝缘层，该栅极绝缘层由SiO2薄膜和SiN薄膜构成，且SiN薄膜形成在SiO2薄膜之上，SiO2薄膜的厚度为30nm～100nm，SiN薄膜的厚度为20nm～100nm。
  5. 根据权利要求4所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，所述在多晶硅存储电容下极板之上沉积的栅极绝缘层用以构成多晶硅存储电容的绝缘介质。
  6. 根据权利要求1所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，在步骤c)中，所述在所述栅极绝缘层上形成金属层的步骤包括采用磁控溅射方法在栅极绝缘层上沉积一层厚度为200nm～500nm的金属薄膜，然后通过光刻和刻蚀工艺去除栅极、栅线、源电极、漏电极和数据线以外区域的金属薄膜，形成栅极及与栅极相连的栅线，源电极、漏电极及与源电极、漏电极相连的数据线，以及同时形成多晶硅存 储电容上极板。
  7. 根据权利要求6所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，
    所述金属薄膜是由Al、Cu、Mo、Ti或AlNd形成的单层金属薄膜，或者是由Mo/Al/Mo或Ti/Al/Ti形成的多层金属薄膜；
    所述与源电极、漏电极相连的数据线由连续线状的金属薄膜构成，而所述栅线由不连续线状的金属薄膜构成，且所述栅线在与所述数据线的交叉处断开；
    所述刻蚀该金属层的步骤是采用湿法腐蚀或干法腐蚀工艺实现；
    所述多晶硅存储电容下极板、多晶硅存储电容下极板上形成的栅极绝缘层和多晶硅存储电容下极板构成多晶硅存储电容。
  8. 根据权利要求1所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，所述步骤d)包括：
    采用等离子体增强化学气相沉积在栅极、源电极、漏电极以及金属栅线和数据线上沉积一层介质薄膜而形成钝化层，然后进行快速热退火或热处理炉退火工艺，利用钝化层和栅极绝缘层中的SiN薄膜，实现多晶硅有源层内部以及多晶硅薄膜与SiO2薄膜界面的氢化；
    采用半透式掩模版在钝化层表面形成两种不同厚度的第三光刻胶(5c)和第四光刻胶(5d)，第三光刻胶(5c)的厚度大于第四光刻胶(5d)的厚度；
    采用等离子体或电感耦合等离子方法对钝化层及钝化层下的栅极绝缘层进行刻蚀，形成钝化层过孔；
    去除第四光刻胶(5d)，而保留第三光刻胶(5c)作为剥离层；
    在钝化层过孔、第三光刻胶(5c)、钝化层、源电极、漏电极以及整个基板表面沉积一层透明导电薄膜；以及
    采用剥离工艺同时去除第三光刻胶(5c)及其上沉积的透明导电薄膜，而保留钝化层过孔以及源电极、漏电极和像素区域钝化层薄膜之上的透明导电薄膜，形成源电极和像素电极。
  9. 根据权利要求8所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，
    所述钝化层是厚度在200nm～500nm之间含氢的SiN薄膜；
    所述半透式掩模版是半色调或灰色调掩模版；
    所述第三光刻胶(5c)的厚度在1微米～3微米之间，覆盖栅极及其相连的栅线、源电极及其相连的数据线、以及除钝化层过孔和第四光刻胶(5d)以外的所有区域；所述第四光刻胶(5d)的厚度在0.5微米～1微米之间，覆盖漏电极以及相邻的像素区域；
    当该低温多晶硅薄膜场效应晶体管阵列采用底发射有源矩阵有机发光二极管时，所述在钝化层过孔、第三光刻胶(5c)、钝化层、源电极、漏电极以及整个基板表面沉积的透明导电薄膜是氧化物透明导电薄膜，至少包括氧化铟锡、氧化铟锌或氧化锡铝，厚度为20nm～100nm；
    当该低温多晶硅薄膜场效应晶体管阵列采用顶发射有源矩阵有机发光二极管时，所述在钝化层过孔、第三光刻胶(5c)、钝化层、源电极、漏电极以及整个基板表面沉积的透明导电薄膜是复合薄膜，至少包括ITO/Ag/ITO和IZO/Ag，其中ITO厚度为10nm～50nm，Ag金属薄膜厚度为20nm～100nm。
  10. 根据权利要求8所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，
    在进行所述钝化层过孔工艺、导电薄膜沉积和剥离工艺的同时，在断续栅线搭桥处形成连接断续栅线的导电薄膜，完成整个阵列数据线的制作；
    所述栅线处的钝化层过孔工艺与所述源漏电极处钝化层过孔工艺同时进行，栅线连接导电薄膜的沉积和剥离工艺与所述像素电极沉积、剥离工艺也是同时进行的。
  11. 根据权利要求1所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，在步骤e)中所述在像素电极上形成的像素定义层由亚克力材料形成，厚度是1微米～4微米。
  12. 根据权利要求1所述的制备低温多晶硅薄膜场效应晶体管阵列基板的方法，其中，步骤e)包括：在像素电极上形成像素定义层后，进一步对低温多晶硅薄膜场效应晶体管阵列基板采用快速热退火或热处理炉进行退火处理，以稳定低温多晶硅薄膜晶体管的特性。
  13. 一种低温多晶硅薄膜场效应晶体管阵列基板，利用权利要求1至 12中任一项所述的方法制备。
  14. 根据权利要求13所述的低温多晶硅薄膜场效应晶体管阵列基板，其中，栅极、源电极和漏电极是采用同一层金属制备的。
  15. 根据权利要求13所述的低温多晶硅薄膜场效应晶体管阵列基板，其中，用于沉积像素电极的同一层透明导电薄膜通过过孔将各条栅线连接起来。
  16. 根据权利要求15所述的低温多晶硅薄膜场效应晶体管阵列基板，其中，用于沉积像素电极的同一层透明导电薄膜还将漏电极与有源层连接起来。
  17. 一种显示装置，包括如权利要求13-16中任一项所述的低温多晶硅薄膜场效应晶体管阵列基板。
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