1330502 九、發明說明： 【發明所屬之技術領域】 一種薄膜電晶體面板的製作方法，尤指一種應用於有 . 機發光二極體顯示器，具有低溫多晶矽薄膜電晶體之有機 發光二極體面板的製作方法。 【先前技術】 φ 一般製造低溫多晶石夕薄膜電晶體（low temperature polycrystalline silicon thin film transistor，LTPS TFT)陣列 的步驟需使用多達六至九道光罩來進行黃光暨蝕刻製程 (photo-etching-process，PEP)，遠較一般非晶矽薄膜電晶體 (hydrogenated amorphous silicon thin film transistor» a -Si:H TFT)的五道光輩複雜且耗時。此外，在主動式有機發光二 極體面板（active matrix organic light-emitting diode > • AMOLED)的應用上’因為複雜的晝素電路設計架構，所以 必須利用低溫多晶矽薄膜電晶體驅動陣列來製作，然其又 因為多了一層定義晝素電極發光區域的絕緣層（pixel define layer，PDL)，更使得所需光罩數增為七至十道。 請參閱第1圖，第1圖是應用在傳統有機發光二極體 面板之薄膜電晶體（TFT )的結構示意圖。習知技術在製 作有機發光二極體面板1〇〇時，係先提供一個玻璃基板 102,再依序沈積一緩衝絕緣層1〇4和—層非晶矽薄膜（未 51330502 IX. Description of the invention: [Technical field of invention] A method for fabricating a thin film transistor panel, in particular, an organic light-emitting diode panel having a low-temperature polycrystalline germanium film transistor applied to an organic light-emitting diode display Production Method. [Prior Art] φ The general procedure for fabricating a low temperature polycrystalline silicon thin film transistor (LTPS TFT) array requires up to six to nine masks for photo-etching (photo-etching). -process, PEP), which is much more complicated and time consuming than the five atoms of the hydrogenated amorphous silicon thin film transistor» a -Si:H TFT. In addition, in the application of active matrix organic light-emitting diodes (AMOLEDs), it is necessary to use low-temperature polycrystalline germanium film transistor driving arrays because of the complicated structure design of the pixel circuit. However, because of the addition of a layer of a pixel defining layer (PDL) that defines the light-emitting area of the elemental electrode, the number of masks required is increased by seven to ten. Please refer to Fig. 1. Fig. 1 is a schematic view showing the structure of a thin film transistor (TFT) applied to a conventional organic light emitting diode panel. In the prior art, when the organic light-emitting diode panel is fabricated, a glass substrate 102 is first provided, and a buffer insulating layer 1〇4 and a layer of amorphous germanium film are sequentially deposited (not 5).
1330502 I 顯示）於玻璃基板102上，並經由準分子雷射退火（excimer laser annealing，ELA)等製程’使此作晶石夕薄膜再結晶 (recrystallize)成多晶石夕薄膜。接著利用〆第一光罩來進行 第一微影蝕刻製程（PEP) ’以於多晶矽薄膜餘刻出所需之 主動層（active layer)圖案’之後再沈積一閘極絕緣層（gate insulator) 108覆蓋於主動層和緩衝絕緣層104表面。 然後再藉著一金屬沈積製程和一使用第二光罩的第二 微影蝕刻（PEP)來蝕刻出閘極金屬11〇。隨後即可利用閘 極金屬110作為自我對準（self-alignment)遮罩，對主動層 106進行棚離子等離子佈植製程，以形灰源極(source) 103 和〉及極（drain) 105。其中，習知技術另可視電路設計之需 要，於各像素區中形成多晶矽下極板107和金屬上極板 111，並隔離以閘極絕緣層108，構成儲存電容（storage capacitance，Cst) 113。 接著沈積一層間絕緣層（inter-layer dielectric，ILD)， 並覆蓋閘極金屬110、金屬上極板111和閘極絕緣層108， 再利用第三光罩來進行第三微影蝕刻（PEP)，用以去除源 極103和汲極1〇5上方的部份層間絕緣層112和閘極絕緣 層108，以定義出介層洞（Via hole) 115。然後再進行另 一金屬沈積製程，並利用第四光罩來進行第四微影蝕刻 (PEP)，以蝕刻出訊號線、汲極金屬等之金屬層114在介 6 1330502 層洞1 1 5表而μ .四上’且分別電連接源極1〇3和汲極1〇5。接 1 '平—化之保護層（passivation layer) 116於金屬層 114和層間絕緣層112之上，並利用第五光罩來進行第五微 （PEP) ’以去除電連接没極105之金屑層114上方 日116然後再形成氧化銦錫（Indium Tin Oxide， • ⑽之相導電_(未顯示)於護層 116上，並利用第六光 罩來進行第”微影轴刻（pEp)，以定義出適當大小之透明 籲電極，1= ’ &後再進行一沈積製程並利用第七光罩來進行 第七U刻（PEp)以形成晝素電極絕緣層㈣[)n 最後再於透明電極118表面形成發光二極體（未顯示），即 完成習知技術中有機發光二極體面板雨。 在習知技術中，必須利用七道光罩才能完成前述應用 於薄膜電晶體㈣的製作’不但步驟繁續、製程複雜，而1330502 I is shown on the glass substrate 102, and the crystallized film is recrystallized into a polycrystalline film by excimer laser annealing (ELA) or the like. The first photolithography process (PEP) is then performed using the first photomask to deposit a gate insulator 108 after the polysilicon film remains engraved with the desired active layer pattern. Covering the active layer and the surface of the buffer insulating layer 104. The gate metal 11 is then etched by a metal deposition process and a second photolithography (PEP) using a second mask. The active metal layer 106 can then be subjected to a shed ion plasma implantation process using the gate metal 110 as a self-alignment mask to form a source 103 and a drain 105. Among them, the conventional technology can also form a polycrystalline lower plate 107 and a metal upper plate 111 in each pixel region, and is isolated from the gate insulating layer 108 to constitute a storage capacitance (Cst) 113. An inter-layer dielectric (ILD) is then deposited and covers the gate metal 110, the metal upper plate 111 and the gate insulating layer 108, and the third photomask is used for the third lithography (PEP). A portion of the interlayer insulating layer 112 and the gate insulating layer 108 over the source 103 and the drain 1 〇 5 are removed to define a via hole 115. Then another metal deposition process is performed, and a fourth photomask is used to perform a fourth photolithography etching (PEP) to etch the metal layer 114 of the signal line, the drain metal, etc. in the layer 6 1330502 layer 1 1 5 And μ.4" and electrically connected to the source 1〇3 and the drain 1〇5, respectively. A 1 'leveling passivation layer 116 is over the metal layer 114 and the interlayer insulating layer 112, and a fifth photomask is used to perform a fifth micro (PEP) 'to remove the gold of the electrically connected immersion 105 The upper layer 116 of the chip layer 114 then forms indium tin oxide (Indium Tin Oxide, (10) phase conduction _ (not shown) on the sheath 116, and uses the sixth mask to perform the "micro lithography" (pEp) To define a transparent electrode of appropriate size, 1 = ' & then perform a deposition process and use the seventh mask to perform the seventh U-etch (PEp) to form the halogen electrode insulation layer (4) [) n A light-emitting diode (not shown) is formed on the surface of the transparent electrode 118, that is, the organic light-emitting diode panel rain in the prior art is completed. In the prior art, it is necessary to use the seven masks to complete the foregoing application to the thin film transistor (4). Making 'not only the steps are complicated, the process is complicated, but
且夕光罩數所導致的高成本及對位誤差⑽㈣卽则〇，也 嚴重降低產能與良率。因此如何縮減製作時的光罩數，已 成為有機發光二極體顯示器開發的重要課題之一。 【發明内容】 有鑑於此本發明係提供_種主動矩陣式有機發光二極 體面板的製作方法，以解決上述問題。 依照本發明最佳實施例所述之提供-種主動矩陣式有機 7 1330502 =3=3製作方法’其中包含提供基板，形成訊號線與 衝絕缘#上\藉’於基板上形成緩衝絕緣層，形成主動層於緩 =二Γ極絕緣層覆蓋於主動層和緩衝絕緣層上’於 和躲，於閘=絕緣層表面形賴極金屬’進行離子佈植源極 和/及極_料緣層+形齡層洞，職”電極於介層 洞和閘極㈣層表面，形成畫素電極絕緣層於等透明電極 上，以及形成發光二極體於透明電極上。The high cost and alignment error caused by the number of masks (10) (4) are also severely degraded, as well as the production capacity and yield. Therefore, how to reduce the number of masks at the time of production has become one of the important topics in the development of organic light-emitting diode displays. SUMMARY OF THE INVENTION In view of the above, the present invention provides a method for fabricating an active matrix organic light emitting diode panel to solve the above problems. Provided in accordance with a preferred embodiment of the present invention, an active matrix type organic 7 1330502 = 3 = 3 fabrication method 'which includes providing a substrate, forming a signal line and punching insulation on the substrate to form a buffer insulating layer on the substrate, Forming an active layer on the active layer and the buffer insulating layer on the active layer and the buffer insulating layer, and immersing the source and/or the edge layer on the surface of the insulating layer The +-type layer hole, the "electrode" on the surface of the via hole and the gate (four) layer, forms a pixel electrode insulating layer on the transparent electrode, and forms a light-emitting diode on the transparent electrode.
本發明改變了 一般低溫多晶石夕薄膜電晶體陣列的液晶 顯示面板中金屬線的位置結構，使閘極金屬位於金屬層: 方，並省略習知技術的層間絕緣層的製作，更利用緩衝絕 緣層與閘極絕緣層作為金屬層和閘極金屬之間的絕緣層， 以避免其發生短路而且本發明更省略護層的製作，使得 光罩數目減少至六道，以達到降低成本與簡化製程的目標。The invention changes the positional structure of the metal lines in the liquid crystal display panel of the general low-temperature polycrystalline slab thin-film transistor array, so that the gate metal is located on the metal layer: and the fabrication of the interlayer insulating layer of the prior art is omitted, and the buffer is further utilized. The insulating layer and the gate insulating layer serve as an insulating layer between the metal layer and the gate metal to avoid short circuit thereof, and the invention further omits the fabrication of the protective layer, so that the number of masks is reduced to six, so as to reduce cost and simplify the process. The goal.
【實施方式】 第2圖至第8圖繪示為依照本發明實施例之主動矩陣 式有機發光二極體面板(AMOLED)的製程示意圖。如第2 圖所示’首先提供一個玻璃基板202當作下基板，再沈積 一層第一金屬薄骐（未顯示）於玻璃基板202上，接著利 用一第一光罩來對此第一金屬薄膜進行第—微影蝕刻 (PEP)，以形成訊號線、汲極金屬等之金屬層2〇4。 1330502 隨後如第3圖所示，於玻璃基板202的表面沈積一層 緩衝絕緣層206並覆蓋在金屬層204之上。接著在緩衝絕 緣層206上沈積一層非晶矽薄膜（未顯示），並藉由準分子 雷射等退火製程，使此非晶矽薄膜再結晶成多晶矽薄膜。 然後利用一第二光罩來對此多晶矽薄膜（未顯示）進行第 二微影蝕刻（PEP)，即可得到所需之主動層208的圖案， 且主動層208係位於訊號線、汲極金屬之金屬層204間的 • 緩衝絕緣層2〇6上方，如第4圖所示。 接著，參閱第5圖，在主動層208和緩衝絕緣層206 表面沈積一閘極絕緣層210。然後進行一第二金屬薄膜沈 積製程，以於閘極絕緣層210表面形成一層第二金屬薄膜 (未顯示），.並利用一第三光罩來進行第三微影蝕刻 (PEP)，以蝕刻得到閘極金屬212，如第6圖所示，隨後 即可利用閘極金屬212作為自我對準遮罩，對主動層208 進行硼離子離子佈植製程，以於主動層208中形成源極213 和沒極215。 請注意到在本發明之最後實施例中，閘極金屬212係 位於金屬層204的上方，但是，在習知技術中金屬層114 係位於閘極金屬110的上方。 請參閱第7圖，接著利用一第四光罩來進行第四微影 9 1330502 緣層 巴 以分別 蝕刻（PEP)，蝕刻部份之閘極絕緣層210和緩^^ 2〇6 ’直至源極213、汲極215與金屬層204表面， 於金屬層204和汲極215與源極213上方形成複數 〜 洞217。然後形成一透明導電薄膜（未顯示）例如：^ 丨層 氣化鋼紐 (ITO)或氧化銦辞（indium zinc oxide, IZO)，並覆蓋 ’ 屬212、金屬層204源極213、汲極215和閘極〇1 金 z 1 〇上方 之後再利用一第五光罩對透明導電薄膜進行第玉 ’ ±·,|[Embodiment] FIG. 2 to FIG. 8 are schematic diagrams showing a process of an active matrix organic light emitting diode panel (AMOLED) according to an embodiment of the invention. As shown in FIG. 2, a glass substrate 202 is first provided as a lower substrate, and a first metal thin crucible (not shown) is deposited on the glass substrate 202, and then a first photomask is used to coat the first metal thin film. The first photolithography (PEP) is performed to form a metal layer 2〇4 of a signal line, a drain metal, or the like. 1330502 Subsequently, as shown in FIG. 3, a buffer insulating layer 206 is deposited on the surface of the glass substrate 202 and overlying the metal layer 204. Next, an amorphous germanium film (not shown) is deposited on the buffer insulating layer 206, and the amorphous germanium film is recrystallized into a polycrystalline germanium film by an annealing process such as excimer laser. Then, a second photomask is used to perform a second lithography (PEP) on the polysilicon film (not shown) to obtain a desired pattern of the active layer 208, and the active layer 208 is located on the signal line and the drain metal. Between the metal layers 204 and the buffer insulation layer 2〇6, as shown in Fig. 4. Next, referring to FIG. 5, a gate insulating layer 210 is deposited on the surface of the active layer 208 and the buffer insulating layer 206. Then, a second metal film deposition process is performed to form a second metal film (not shown) on the surface of the gate insulating layer 210, and a third photomask is used to perform a third photolithography (PEP) etching. The gate metal 212 is obtained. As shown in FIG. 6, the gate metal 212 can be used as a self-aligned mask, and the active layer 208 is subjected to a boron ion implantation process to form a source 213 in the active layer 208. And no 215. It is noted that in the final embodiment of the invention, the gate metal 212 is over the metal layer 204, however, the metal layer 114 is above the gate metal 110 in the prior art. Referring to FIG. 7, a fourth reticle is used to perform a fourth lithography 9 1330502 edge layer to be separately etched (PEP), and a portion of the gate insulating layer 210 and the buffer 2 〇 6 ′ are etched to the source. 213, the surface of the drain 215 and the metal layer 204, forming a plurality of holes 217 above the metal layer 204 and the drain 215 and the source 213. Then, a transparent conductive film (not shown) is formed, for example: ITO or indium zinc oxide (IZO), and covers 'genus 212, metal layer 204 source 213, and drain 215 And after the gate 〇1 gold z 1 〇 above, the fifth transparent mask is used to perform the first conductive transparent film on the first jade '±·,|
(PEP)，以定義出適當大小之透明電極214，xJ 電極214來電性連接金屬層204與源極213，η Ώ 透明 Μ及電性、查 接當作汲極金屬之金屬層204和汲極215。 雙 然後請參閱第8圖，利用旋轉塗佈製程將〜爲^ 玻璃（spin 〇n glass，SOG)材料，例如是二氧化疋式 ^吵或感(PEP), to define a transparent electrode 214 of appropriate size, the xJ electrode 214 electrically connects the metal layer 204 and the source 213, η Μ transparent Μ and electrical, and is connected to the metal layer 204 and the drain of the metal as a drain metal 215. Double Then, please refer to Figure 8, using a spin coating process to make a glass material (Spin 〇n glass, SOG), such as cerium oxide type
性的絕緣材料均勻塗佈於透明電極214、閘極絕緣層、 和閘極金屬212之上，以形成一平坦化之畫素電極絕緣層° 216,並且利用一第六光罩來進行第六微影蝕刻（pEp)，以 蝕刻部分之畫素電極絕緣層216並曝露出電連接汲極215 之透明電極214。最後再於曝露出之透明電極214表面形 成一有機發光二極體218，即完成本發明中之有機發光二 極體面板800。其中，值得注意的是’本實施例之透明電 極214的覆蓋範圍係大於電連接汲極215之金屬層2〇4， 所以有機發光二極體218的光線可以同時由上、下兩方向 發政’因此可形成一個底部發光(bottom emission)二極體面 I33〇5〇2 • 板或上、下發光之有機發光二極體面板。 相較於習知技術’由於本發明改變了一般低溫多晶石夕 . 薄祺電晶體(LTPS TFT)陣列的液晶顯示面板中金屬線的位 置結構，使閘極金屬位於金屬層上方，並省略習知技術的 層間絕緣層的製作，更利用緩衝絕緣層與閘極絕緣層作為 金屬層和閘極金屬之間的絕緣層，以避免其發生短路。再 ♦者’本發明之畫素電極絕緣層係利用旋轉式玻璃材料，例 如二氧化矽以旋轉塗佈方法完成，其平坦化結構更有利於 、後續製程，而且本發明更省略護層的製作，使得光罩數目 減J至六道，以達到降低成本與簡化製程的目標。此外， 本發明之技術可應用於一般低溫多晶矽薄膜電晶體（ππ TFT)陣列的液晶顯示面板的製程中，不但僅需六道光罩即 可製備完成，而且更可利用電連接汲極之金屬層與透明電 •極相對位置的不同，而分別製作反射式、穿透式以及半穿 半反的液晶顯示面板。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖是習知技術中發光二極體面板的結構示意圖。 第2圖至第8圖是本發明之發光二極體面板的製程示音圖。 1330502 【主要元件符號說明】 100、800發光二極體面板 102、 202玻璃基板 103、 213 源極 104、 206緩衝絕緣層 105、 215 汲極 106、 208主動層 107多晶矽下極板 108、210閘極絕緣層 110、212閘極金屬 111金屬上極板 112層間絕緣層 113儲存電容 114、204金屬層 115介層洞 116護層 118、214透明電極 120、216晝素電極絕緣層 217介層洞 218發光二極體 12The insulating material is uniformly coated on the transparent electrode 214, the gate insulating layer, and the gate metal 212 to form a planarized pixel insulating layer 216, and a sixth mask is used for the sixth Photolithography (pEp) is performed to etch a portion of the pixel electrode insulating layer 216 and expose the transparent electrode 214 electrically connected to the drain 215. Finally, an organic light-emitting diode 218 is formed on the surface of the exposed transparent electrode 214, that is, the organic light-emitting diode panel 800 of the present invention is completed. It should be noted that the coverage of the transparent electrode 214 of the present embodiment is greater than the metal layer 2〇4 of the electrical connection diode 215, so the light of the organic light-emitting diode 218 can be simultaneously administered by both the upper and lower directions. 'Therefore, a bottom emission diode surface I33〇5〇2 • a plate or an upper and lower illuminating organic light-emitting diode panel can be formed. Compared with the prior art, the present invention changes the positional structure of the metal lines in the liquid crystal display panel of the general low temperature polycrystalline lithium transistor (LTPS TFT) array, so that the gate metal is located above the metal layer and is omitted. The fabrication of the interlayer insulating layer of the prior art further utilizes a buffer insulating layer and a gate insulating layer as an insulating layer between the metal layer and the gate metal to prevent short-circuiting thereof. Further, the pixel insulating layer of the present invention is completed by a spin coating method using a rotary glass material, such as cerium oxide, and the flattening structure is more advantageous and subsequent processes, and the invention further omits the production of the protective layer. The number of masks is reduced by J to six to achieve the goal of reducing costs and simplifying the process. In addition, the technology of the present invention can be applied to the process of a liquid crystal display panel of a general low-temperature polycrystalline germanium thin film transistor (ππ TFT) array, which can be prepared not only by six reticle but also by electrically connecting the metal layer of the drain. Reflective, transmissive, and transflective liquid crystal display panels are fabricated separately from the relative positions of the transparent electrodes. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a light-emitting diode panel in the prior art. 2 to 8 are process diagrams of the LED panel of the present invention. 1330502 [Description of main component symbols] 100, 800 LED panel 102, 202 glass substrate 103, 213 source 104, 206 buffer insulation layer 105, 215 drain 106, 208 active layer 107 polysilicon lower plate 108, 210 gate Polar insulating layer 110, 212 gate metal 111 metal upper plate 112 interlayer insulating layer 113 storage capacitor 114, 204 metal layer 115 via hole 116 protective layer 118, 214 transparent electrode 120, 216 elemental electrode insulating layer 217 via hole 218 light emitting diode 12