CN104282769B - 薄膜晶体管的制备方法、阵列基板的制备方法 - Google Patents

薄膜晶体管的制备方法、阵列基板的制备方法 Download PDF

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CN104282769B
CN104282769B CN201410473273.8A CN201410473273A CN104282769B CN 104282769 B CN104282769 B CN 104282769B CN 201410473273 A CN201410473273 A CN 201410473273A CN 104282769 B CN104282769 B CN 104282769B
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electrode
layer
thickness
photoresist
connecting line
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CN104282769A (zh
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龙春平
王祖强
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to PCT/CN2015/070327 priority patent/WO2016041304A1/zh
Priority to US14/768,009 priority patent/US9748280B2/en
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Abstract

本发明提供一种薄膜晶体管及其制造方法、阵列基板及其制备方法、显示装置，属于显示技术领域，其可解决现有的低温多晶硅阵列基板制备工艺较为复杂的问题。本发明的薄膜晶体管包括栅极、源极、漏极、栅极绝缘层、有源层、钝化层；其中，栅极、源极、漏极同层设置，且材料相同；栅极绝缘层设于栅极上方，有源层设置于栅极绝缘层上方，且栅极绝缘层、栅极、有源层三者图案相同；钝化层覆盖所述源极、漏极、有源层，钝化层中设有与源极位置对应的第一过孔、与漏极位置对应的第二过孔，与有源层位置所对应的第三过孔和第四过孔；第一电极连接线通过第一过孔和第三过孔将源极与所述有源层连接，第二电极连接线通过第二过孔和第四过孔将漏极与有源层连接。

Description

薄膜晶体管的制备方法、阵列基板的制备方法
技术领域
本发明属于显示技术领域，具体涉及一种低温多晶硅薄膜晶体管及其制备方法、阵列基板及其制备方法、显示装置。
背景技术
相对于液晶显示器，有机发光二极管显示器具有反应速度快、重量轻、可弯曲和广视角等优点。而有源矩阵有机发光二极管(AMOLED)更具有驱动电流小和功耗低的优势，适合于高解析度显示器。有源矩阵有机发光二极管架构可使用非晶硅、多晶硅、氧化物半导体或有机薄膜晶体管驱动，由于非晶硅或有机薄膜晶体管的载流子迁移率与驱动电流小，驱动高亮度有机发光二极管所需的电压较高且器件也较大。然而低温多晶硅具有高达100cm2/V-s的迁移率，其高电流特性正好符合有机发光二极管严格的要求，低操作电压与高密度的驱动架构使得有机发光二极管寿命较长。有别于传统液晶显示器电压驱动的方式，有机发光二极管驱动所需为特殊电流驱动架构，还有为了克服灰阶与面板均匀性所涉及的补偿电路，往往在同一像素中需要2～6个薄膜晶体管，而低温多晶硅薄膜晶体管高密度的布局特点，使得高亮度与高画质的有机发光二极管面板更容易实现。目前成功商业化生产的AMOLED绝大部分使用低温多晶硅的阵列基板。
在传统的低温多晶硅阵列基板制造工艺过程中，一般需要8～9道曝光。对图1所示现有技术的低温多晶硅阵列制造工艺进行说明。
通过等离子体增强化学气相沉积(PECVD)，在整个基底1上形成二氧化硅(SiO2)和氮化硅(SiN)薄膜的缓冲层2。其后利用PECVD或者其它化学(或物理)气相沉积方法在缓冲层2 上形成非晶硅薄膜(a-Si)。通过激光退火(ELA)或者固相结晶(SPC)方法，使得a-Si结晶成为多晶硅薄膜。而后使用传统曝光工艺刻蚀形成多晶硅有源层3。利用离子注入工艺进行低浓度离子掺杂，在多晶硅有源层3中形成薄膜晶体管要求的半导体沟道。
通过PECVD沉积SiO2或SiO2和SiN薄膜，在形成有源层3的基底1上形成栅极绝缘层4。通过磁控溅射等物理气相沉积方法在栅极绝缘层4上沉积一种或者多种低电阻的金属材料薄膜，利用光刻工艺形成栅极5。
在形成栅极5的基底1上，通过PECVD沉积SiO2和SiN薄膜，通过曝光和刻蚀工艺形成钝化层6，以及用于源极7和漏极8与有源层3连接的过孔。
使用磁控溅射沉积一种或多种低电阻的金属薄膜，通过曝光和刻蚀工艺形成源极7和漏极8，通过相应的过孔与多晶硅有源层3形成欧姆接触。
在完成上述步骤的基底1上，通过PECVD形成平坦化层。
在完成上述步骤的基底1上，通过磁控溅射沉积一层透明导电薄膜，通过光刻工艺形成像素区域的像素电极10。
在完成上述步骤的基底1上，形成平坦化层9，并通过构图工艺形成包括像素限定层11的图形。
综上所述，至少需要6～7道光刻工艺形成图1所示的低温多晶硅阵列结构，导致较长的工艺时间和较低的工艺良率，使得阵列成本较高。而且，发明人还发现现有技术中由于结晶过程中多余硅原子都迁移到晶粒之间，多晶硅薄膜在晶界区域形成凸起，造成多晶硅薄膜上表面较高的粗糙度，造成多晶硅有源层3和栅极绝缘层4的界面粗糙，降低了薄膜晶体管的特性，以及造成工艺不良。
发明内容
本发明所要解决的技术问题包括，针对现有的低温多晶硅阵列基板制备工艺成本较高的问题，提供一种制备工艺简单、成本 较低的低温多晶硅薄膜晶体管及其制备方法、阵列基板及其制备方法、显示装置。
解决本发明技术问题所采用的技术方案是一种低温多晶硅薄膜晶体管，包括：栅极、源极、漏极、栅极绝缘层、有源层、钝化层、第一电极连接线、第二电极连接线；其中，所述栅极、源极、漏极同层设置，且材料相同；所述栅极绝缘层设于所述栅极上方，所述有源层设置于栅极绝缘层上方，且所述栅极绝缘层、栅极、有源层三者图案相同；所述钝化层覆盖所述源极、漏极、有源层，所述钝化层中设有与所述源极位置对应的第一过孔、与所述漏极位置对应的第二过孔，与所述有源层位置所对应的第三过孔和第四过孔；所述第一电极连接线通过所述第一过孔和第三过孔将所述源极与所述有源层连接，所述第二电极连接线通过所述第二过孔和第四过孔将所述漏极与所述有源层连接。
本发明的低温多晶硅薄膜晶体管的栅极、源极、漏极、有源层、栅极绝缘层可以通过依次构图工艺制备，第一电极连接线、第二电极连接线与第一过孔、第二过孔、第三过孔、第四过孔通过依次构图工艺制备，故本发明的薄膜晶体管仅采用两次构图工艺，故其工艺简单，成本较低。
优选的是，所述栅极、源极、漏极的材料为钼、钼铌合金、铝、铝钕合金、钛和铜中的任意一种或它们中的多种。
优选的是，所述栅极绝缘层的材料为硅的氧化物、硅的氮化物、铪的氧化物、硅的氮氧化物、铝的氧化物中的任意一种或它们中的多种。
解决本发明技术问题所采用的技术方案是一种低温多晶硅薄膜晶体管的制备方法，包括如下步骤：
在基底上通过一次构图工艺形成包括薄膜晶体管栅极、源极、漏极、栅极绝缘层、有源层的图形，其中，所述栅极、源极、漏极同层设置，所述栅极绝缘层设于所述栅极上方，所述有源层设于所述栅极绝缘层上方，且所述栅极、栅极绝缘层、有源层三者图案相同；
在完成上述步骤的基底上形成钝化层，并通过构图工艺在钝化层中形成与所述源极位置对应的第一过孔、与所述漏极位置对应的第二过孔、与所述有源层位置所对应的第三过孔和第四过孔，以及用于通过所述第一过孔和第三过孔将所述源极与所述有源层连接的第一电极连接线和通过所述第二过孔和第四过孔将所述漏极与所述有源层连接的第二电极连接线的图形。
优选地，所述在基底上通过一次构图工艺形成包括薄膜晶体管栅极、源极、漏极、栅极绝缘层、有源层的图形的步骤具体包括：
在基底上依次沉积金属薄膜、栅极绝缘层薄膜、有源层薄膜，并在有源层薄膜上涂覆第一刻胶光层；
对第一光刻胶层进行曝光、显影，其中与源极和漏极位置相对应的剩余光刻胶的厚度为第一厚度，与栅极位置相对应的剩余的光刻胶的厚度为第二厚度，第一厚度小于第二厚度；
去除裸露的有源层薄膜；
去除裸露的栅极绝缘层薄膜；
去除裸露的金属薄膜；
去除第一厚度的光刻胶；
去除裸露的有源层薄膜；
去除裸露的栅极绝缘层薄膜；
去除剩余的光刻胶。
优选的是，所述形成第一过孔、第二过孔、第三过孔、第四过孔、第一电极连接线、第二电极连接线的步骤具体包括：
在形成有钝化层的基底上涂覆第二光刻胶层，并对第二光刻胶层进行曝光、显影，其中与所述第一电极连接线、第二电极连接线位置所对应的光刻胶的厚度为第三厚度，除与所述第一过孔、第二过孔、第三过孔、第四过孔位置所对应的其他区域的光刻胶厚度为第四厚度，第三厚度小于第四厚度；
去除裸露的钝化层，形成第一过孔、第二过孔、第三过孔、第四过孔；
去除第三厚度的光刻胶；
形成导电薄膜；
剥离去除剩余的光刻胶，同时去除光刻胶上方的导电薄膜，形成第一电极连接线和第二电极连接线。
本发明的阵列基板的制备方法工艺简单、成本较低。
解决本发明技术问题所采用的技术方案是一种阵列基板，其包括上述的低温多晶硅薄膜晶体管。
优选的是，所述阵列基板还包括像素电极和像素限定层，
所述像素电极与所述第一电极连接线连接，且所述像素电极与第一所述电极连接线同层设置，材料相同；
所述像素限定层设于所述像素电极上方。
进一步优选的是，所述阵列基板还包括交叉且绝缘设置的多条栅线和多条数据线，
每条所述栅线包括多个栅线条，以及通过贯穿所述钝化层的第五过孔将该条栅线中两相邻所述栅线条连接的第三电极连接线；其中，
所述栅线条和所述数据线与所述栅极、源极、漏极同层设置且材料相同；
所述第三电极连接线的材料与所述像素电极材料相同。
进一步优选的是，所述阵列基板还包括交叉且绝缘设置的多条栅线和多条数据线，
每条所述数据线包括多个数据线条，以及通过贯穿所述钝化层的第六过孔将该条数据线中两相邻所述数据线条连接的第四电极连接线；其中，
所述数据线条和所述栅线与所述栅极、源极、漏极同层设置且材料相同；
所述第四电极连接线的材料与所述像素电极材料相同。
由于本发明的阵列基板包括上述低温多晶硅薄膜晶体管，故其生产成本较低，且改善了栅极绝缘层与有源层的接触界面，故该阵列基板的性能较好。
解决本发明技术问题所采用的技术方案是一种阵列基板的制备方法，其包括：上述低温多晶硅薄膜晶体管的制备方法。
优选的是，所述通过构图工艺形成第一过孔、第二过孔、第三过孔、第四过孔、第一电极连接线、第二电极连接线的同时还包括形成像素电极图形，其中，所述像素电极与所述第二电极连接线连接；
在形成有像素电极的基底上，通过构图工艺形成包括像素限定层的图形。
优选的是，所述形成第一过孔、第二过孔、第三过孔、第四过孔、第一电极连接线、第二电极连接线，以及像素电极的步骤具体包括：
在形成有钝化层的基底上涂覆第二光刻胶层，并对第二光刻胶层进行曝光、显影，其中与所述第一电极连接线、第二电极连接线、像素电极位置所对应的光刻胶的厚度为第三厚度，除与所述第一过孔、第二过孔、第三过孔、第四过孔位置所对应的其他区域的光刻胶厚度为第四厚度，第三厚度小于第四厚度；
去除裸露的钝化层，形成第一过孔、第二过孔、第三过孔、第四过孔；
去除第三厚度的光刻胶；
形成导电薄膜；
剥离去除剩余的光刻胶，同时去除光刻胶上方的导电薄膜，形成第一电极连接线、第二电极连接线，以及像素电极。
优选的是，所述在基底上通过一次构图工艺形成包括薄膜晶体管栅极、源极、漏极、栅极绝缘层、有源层的图形的步骤同时还包括形成栅线条、数据线的图形，其中，所述栅线条与所述数据线相互绝缘，且所述栅线条和所述数据线与所述栅极、源极、漏极同层设置，材料相同；
所述通过构图工艺在钝化层中形成所述第一过孔、第二过孔、第三过孔、第四过孔的同时还包括形成用于将每条所述栅线两相邻栅极条连接的第五过孔；
所述形成像素电极的同时还包括形成通过所述第五过孔将每条所述栅线中两相邻所述栅极条连接的第三电极连接线的图形。
优选的是，所述在基底上通过一次构图工艺形成包括薄膜晶体管栅极、源极、漏极、栅极绝缘层、有源层的图形的步骤同时还包括形成数据线条、栅线的图形，其中，所述数据线条与所述栅线相互绝缘，且所述数据线条和所述栅线与所述栅极、源极、漏极同层设置，材料相同；
所述通过构图工艺在钝化层中形成所述第一过孔、第二过孔、第三过孔、第四过孔的同时还包括形成将每条所述数据线中两相邻所述数据线条连接的第六过孔；
所述形成像素电极的同时还包括形成通过所述第六过孔将每条所述数据线中两相邻所述数据线条连接的第四电极连接线的图形。
本发明的阵列基板优选地可以通过3次构图工艺制备，故降低了阵列基板的生产成本。
解决本发明技术问题所采用的技术方案是一种显示装置，其包括上述阵列基板。
由于本发明的显示装置包括上述阵列基板，故其成本较低。
附图说明
图1为现有的低温多晶硅阵列基板的结构示意图；
图2a至图2d为本发明的实施例1和2的低温多晶硅薄膜晶体管及阵列基板的制备方法中的第一次光刻工艺的示意图；
图2e至图2i为本发明的实施例1和2的低温多晶硅薄膜晶体管及阵列基板的制备方法中的第二次光刻工艺的示意图；
图2j为本发明的实施例2的阵列基板的第三次光刻工艺的示意图；
图3为本发明的实施例2的阵列基板的平面示意图；
图4为图3的A-A'的剖面图。
其中附图标记为：1、基底；2、缓冲层；3a、有源层薄膜；3、有源层；4a、栅极绝缘层薄膜；4、栅极绝缘层；5a、金属薄膜；5、栅极；6、钝化层；7、源极、8、漏极；9、平坦化层；10a、导电薄膜；10、像素电极；11、像素限定层；12a、第一厚度；12b、第二厚度；12c、剩余的第一光刻胶层的厚度；13a、第三厚度；13b、第四厚度；13c、剩余的第二光刻胶层的厚度；14a、第一过孔；14b、第一过孔；14c、第二过孔；14d、第三过孔；14e、第四过孔；15a、第一电极连接线；15b、第二电极连接线；15c、第三电极连接线；16a、栅线条；17、数据线。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
结合图2a至2i，本实施例提供一种低温多晶硅薄膜晶体管及其制备方法，该薄膜晶体管包括：包括：栅极5、源极7、漏极8、栅极绝缘层4、有源层3、钝化层6、第一电极连接线15a、第二电极连接线15b；其中，所述栅极5、源极7、漏极8同层设置，且材料相同；所述栅极绝缘层4设于所述栅极5上方，所述有源层3设置于栅极绝缘层4上方，且所述栅极绝缘层4、栅极5、有源层3三者图案相同；所述钝化层6覆盖所述源极7、漏极8、有源层3，所述钝化层6中设有与所述源极7位置对应的第一过孔14a、与所述漏极8位置对应的第二过孔14b，与所述有源层3位置所对应的第三过孔14c和第四过孔14d；所述第一电极连接线15a通过所述第一过孔14a和第三过孔14c将所述源极7与所述有源层3连接，第二电极连接线15b通过所述第二过孔14b和第四过孔14d将所述漏极8与所述有源层3连接。
由于本实施例的阵列基板具有上述特点，故其可以通过2次构图工艺制备，从而提高生产效率，节约成本。具体的如下述方 法：
如图1所示，对基底1进行初始清洗以清除基底1表面的杂质粒子，然后通过化学气相沉积(PECVD)在基底1上形成缓冲层2。
其中，该缓冲层2优选为氮化硅(SiN)薄膜和二氧化硅(SiO2)薄膜的复合膜结构，氮化硅薄膜的厚度为50～100nm，二氧化硅薄膜的厚度为100～400nm。其中，氮化硅薄膜具有很强的扩散阻挡特性，可以抑制金属离子对于多晶硅薄膜的影响；二氧化硅薄膜与多晶硅薄膜具有优良的界面，可以防止氮化硅薄膜缺陷对多晶硅薄膜质量的损害。
在完成上述步骤的基底1上，通过磁控溅射的方式沉积一层厚度为200～500nm的金属薄膜5a；其中，该金属薄膜5a的材料可以是钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层，优选为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
通过化学气相沉积的方式在金属薄膜5a上沉积形成栅极绝缘层薄膜4a，其材料可以为硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)等中的一种或它们中多种材料组成的多层复合膜，一般进一步优选为厚度在30～100nm的SiO2和厚度在20～100nm的SiN两层薄膜，其中SiO2薄膜为顶层，SiN薄膜为底层；
通过化学气相沉积的方式在栅极绝缘层薄膜4a上连续沉积一层厚度在40～100nm的a-Si(非晶硅)薄膜，使用热处理炉对a-Si薄膜进行脱氢工艺处理，以防止结晶过程中的氢爆，然后进行a-Si结晶工艺，可以使用激光退火结晶、金属诱导结晶、固相结晶等方法，形成如图所示的多晶硅薄膜，并使用稀释的氢氟酸对多晶硅薄膜进行清洗，降低多晶硅薄膜的表面粗糙度，可以减少薄膜晶体管的缺陷。使用离子注入或者离子云注入的方法，对多晶硅薄膜进行薄膜晶体管沟道掺杂，掺杂离子一般为PH3/H2或者 B2H6/H2，离子注入剂量在10^11～10^13ions/cm2之间，注入能量在10～100KeV之间。沟道掺杂可以有效调整薄膜晶体管的阈值电压，改善薄膜晶体管的开关特性；
在多晶硅薄膜上形成第一光刻胶层，并采用半透式掩模板对光刻胶层进行曝光、显影，其中与源极7和漏极8位置相对应的剩余光刻胶的厚度为第一厚度12a，与栅极5位置相对应的剩余的光刻胶的厚度为第二厚度12b，第一厚度12a小于第二厚度12b，得到如图1所示的结构；该半透式掩模板优选为半色调(Half-tone mask)或者灰色调掩模板(Gray-tone mask)。
如图2所示，使用CF4/O2、CHF3/O2或者SF6/O2等混合气体，通过等离子体或者电感耦合等离子方法去除裸露的有源层薄膜3a；
使用CF4、CF4/O2、或者CHF3/O2等气体，通过等离子体或者电感耦合等离子方法，刻蚀去除裸露的栅极绝缘薄膜，其中，刻蚀气体的流量略微不同于多晶硅薄膜刻蚀的气体流量，特别是不需要O2或者较低的O2流量；
然后刻蚀去除暴露的金属薄膜5a，金属刻蚀工艺可以是湿法腐蚀，或者干法腐蚀；
如图2c所示，使用等离子体灰化工艺去除第一厚度12a的光刻胶层，有源层3上剩余的光刻胶，其厚度为12c；
如图2d所示，采用前述方法依次去除裸露的有源层薄膜3a；去除裸露的栅极绝缘层薄膜4a；灰化去除剩余的光刻胶，形成包括栅极5、源极7、漏极8、栅极绝缘层4、有源层3的图形。
如图2e所示，在完成上述步骤的基底1上形成钝化层6，并钝化层6上方涂覆第二光刻胶层，对该光刻胶层曝光、显影，其中与所述第一电极连接线15a、第二电极连接线15b位置所对应的光刻胶的厚度为第三厚度13a，除与所述第一过孔14a、第二过孔14b、第三过孔14c、第四过孔14d位置所对应的其他区域的光刻胶厚度为第四厚度13b，第三厚度13a小于第四厚度13b；
如图2f所示，使用SF6/O2/He气体，通过等离子体或者电感 耦合等离子方法去除裸露的钝化层6，形成第一过孔14a、第二过孔14b、第三过孔14c、第四过孔14d；
如图2g所示，使用等离子体灰化工艺去除第三厚度13a的光刻胶，保留光刻胶覆盖有源层3上方第三过孔14c与第四过孔14d之间的位置，其厚度为12c；
如图2h所示，通过磁控溅射的方法在完成上述步骤的基底1上形成导电薄膜10a；将该薄膜晶体管应用于低温多晶硅阵列使用在底发射AMOLED时，该导电薄膜10a为透明氧化物薄膜，一般是氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锡铝(ZTO)等，厚度是20～100nm。低温多晶硅阵列使用在顶发射AMOLED时，该导电薄膜10a一般是ITO/Ag/ITO、IZO/Ag等复合薄膜，ITO厚度为10～50nm，Ag金属薄膜5a厚度为20～100nm。当然作为一般的薄膜晶体管，该导电薄膜10a为导电性能较好的金属，例如：钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层，优选为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
如图2i所示，把沉积完导电薄膜10a的基板放入剥离机台里，使用光刻胶剥离液去除残留的光刻胶，通过剥离工艺同时去除光刻胶上沉积的导电薄膜10a，形成第一电极连接线15a和第二电极连接线15b。
通过上述的低温多晶硅薄膜晶体管及其制备方法可以看出，该薄膜晶体管的制备仅仅采用两次光刻工艺，进而大大降低了生产成本。同时该薄膜晶体管为底栅结构的薄膜晶体管，从而使得多晶硅薄膜粗糙上表面与钝化层6接触，而多晶硅薄膜平滑下表面构成接触栅极绝缘层4的界面，使得薄膜晶体管具有更低的界面缺陷和更好的晶体管特性。
实施例2：
结合图2a至2j，以及图3和图4所示，本实施例提供了一种 阵列基板及其制备方法，该阵列基板包括实施例1所述的薄膜晶体管，故本实施例的阵列基板的制造成本较低。
优选地，本实施例的阵列基板还包括像素电极10和像素限定层11，其中，像素电极10与所述第一电极连接线15a、第二电极连接线15b同层设置且材料相同，故本实施例的像素电极10与第一电极连接线15a、第二电极连接线15b可以通过一次构图工艺形成，因而节约生产成本。
结合图3和图4所示，作为本实施例的一种情况，所述阵列基板还包括交叉且绝缘设置的多条栅线和多条数据线17，每条所述栅线包括多个栅线条16a，以及通过贯穿所述钝化层6的第五过孔14e将该条栅线中两相邻所述栅线条16a连接的第三电极连接线15c；其中，所述栅线条16a和所述数据线17与所述栅极5、源极7、漏极8同层设置且材料相同；所述第三电极连接线15c的材料与所述像素电极10材料相同。故本实施例的栅线条16a、数据线17可以与栅极5、源极7、漏极8通过一次构图以形成，第五过孔14e、第三电极连接线15c可以与所述第一过孔14a、第二过孔14b、第三过孔14c、第四过孔14d，以及第一电极连接线15a、第二电极连接线15b、像素电极10通过依次构图工艺形成，因为可以大大降低生产成本。
需要说明的是，形成栅线条16a而不是完整的栅线为了避免同层设置的栅线和数据线17由于交叠造成短路。
作为本实施例的另一种情况，该阵列基板包括所述阵列基板还包括交叉且绝缘设置的多条栅线和多条数据线17，每条所述数据线17包括多个数据线条，以及通过贯穿所述钝化层6的第六过孔将该条数据线17中两相邻所述数据线条连接的第四电极连接线；其中，所述数据线条和所述栅线与所述栅极5、源极7、漏极8同层设置且材料相同；所述第四电极连接线的材料与所述像素电极10材料相同。故本实施例的数据线条、栅线可以与栅极5、源极7、漏极8通过一次构图以形成，第六过孔、第四电极连接线可以与所述第一过孔14a、第二过孔14b、第三过孔14c、第四过孔 14d，以及第一电极连接线15a、第二电极连接线15b、像素电极10通过依次构图工艺形成，因为可以大大降低生产成本。
需要说明的是，与上述情况相似，形成数据线条而不是完整的数据线17为了避免同层设置的栅线和数据线17由于交叠造成短路。
相应的本实施例提供了一种阵列基板的制备方法，其包括实施例1中的薄膜晶体管的制备方法，具体包括：
如图2a所示，对基底1进行初始清洗以清除基底1表面的杂质粒子，然后通过化学气相沉积(PECVD)在基底1上形成缓冲层2。
其中，该缓冲层2优选为氮化硅(SiN)薄膜和二氧化硅(SiO2)薄膜的复合膜结构，氮化硅薄膜的厚度为50～100nm，二氧化硅薄膜的厚度为100～400nm。其中，氮化硅薄膜具有很强的扩散阻挡特性，可以抑制金属离子对于多晶硅薄膜的影响；二氧化硅薄膜与多晶硅薄膜具有优良的界面，可以防止氮化硅薄膜缺陷对多晶硅薄膜质量的损害。
在完成上述步骤的基底1上，通过磁控溅射的方式沉积一层厚度为200～500nm的金属薄膜5a，该金属薄膜5a的材料优选为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层，优选为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。Al、Cu、Mo、Ti、AlNd金属材料。
通过化学气相沉积的方式在金属薄膜5a上沉积形成栅极绝缘层薄膜4a，，其材料可以为硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)等中的一种或它们中多种材料组成的多层复合膜，一般进一步优选为厚度在30～100nm的SiO2和厚度在20～100nm的SiN两层薄膜，其中SiO2薄膜为顶层，SiN薄膜为底层。
通过化学气相沉积的方式在栅极绝缘层薄膜4a上连续沉积一 层厚度在40～100nm的a-Si(非晶硅)薄膜，使用热处理炉对a-Si薄膜进行脱氢工艺处理，以防止结晶过程中的氢爆，然后进行a-Si结晶工艺，可以使用激光退火结晶、金属诱导结晶、固相结晶等方法，形成如图所示的多晶硅薄膜，并使用稀释的氢氟酸对多晶硅薄膜进行清洗，降低多晶硅薄膜的表面粗糙度，可以减少薄膜晶体管的缺陷。使用离子注入或者离子云注入的方法，对多晶硅薄膜进行薄膜晶体管沟道掺杂，掺杂离子一般为PH3/H2或者B2H6/H2，离子注入剂量在10^11～10^13ions/cm2之间，注入能量在10～100KeV之间。沟道掺杂可以有效调整薄膜晶体管的阈值电压，改善薄膜晶体管的开关特性。
在多晶硅薄膜上形成第一光刻胶层，并采用半透式掩模板对光刻胶层进行曝光、显影，其中与源极7、漏极8、数据线17、栅线条16a位置相对应的剩余光刻胶的厚度为第一厚度12a，与栅极5位置相对应的剩余的光刻胶的厚度为第二厚度12b，第一厚度12a小于第二厚度12b，的到如图2a所示的结构；该半透式掩模板优选为半色调(Half-tone mask)或者灰色调掩模板(Gray-tone mask)。
如图2b所示，使用CF4/O2、CHF3/O2或者SF6/O2等混合气体，通过等离子体或者电感耦合等离子方法去除裸露的有源层薄膜3a。
使用CF4、CF4/O2、或者CHF3/O2等气体，通过等离子体或者电感耦合等离子方法，刻蚀去除裸露的栅极绝缘薄膜，其中，刻蚀气体的流量略微不同于多晶硅薄膜刻蚀的气体流量，特别是不需要O2或者较低的O2流量。
然后刻蚀去除暴露的金属薄膜5a，金属刻蚀工艺可以是湿法刻蚀，或者干法刻蚀。
如图2c所示，使用等离子体灰化工艺去除第一厚度12a的光刻胶层，剩余有源层3上方的光刻胶，其厚度为12c。
如图2d所示，采用前述方法依次去除裸露的有源层薄膜3a；去除裸露的栅极绝缘层薄膜4a；灰化去除剩余的光刻胶，形成包括栅极5、源极7、漏极8、数据线17、栅线条16a、栅极绝缘层 4、有源层3的图形。
如图2e所示，在完成上述步骤的基底1上形成钝化层6，并钝化层6上方涂覆第二光刻胶层，对该光刻胶层曝光、显影，其中与所述第一电极连接线15a、第二电极连接线15b、第三电极连接线15c、像素电极10位置所对应的光刻胶的厚度为第三厚度13a，除与所述第一过孔14a、第二过孔14b、第三过孔14c、第四过孔14d位置所对应的其他区域的光刻胶厚度为第四厚度13b，第三厚度13a小于第四厚度13b。
如图2f所示，使用SF6/O2/He气体，通过等离子体或者电感耦合等离子方法去除裸露的钝化层6，形成第一过孔14a、第二过孔14b、第三过孔14c、第四过孔14d、第五过孔14e。
如图2g所示，使用等离子体灰化工艺去除第三厚度13a的光刻胶，保留光刻胶覆盖有源层3上方第三过孔14c与第四过孔14d之间的位置(也就是有源层3的导电沟道区域)，其厚度为13c；
如图2h所示，通过磁控溅射的方法在完成上述步骤的基底1上形成导电薄膜10a；将该薄膜晶体管应用于低温多晶硅阵列使用在底发射AMOLED时，该导电薄膜10a为透明氧化物薄膜，一般是氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锡铝(ZTO)等，厚度是20～100nm。低温多晶硅阵列使用在顶发射AMOLED时，该导电薄膜10a一般是ITO/Ag/ITO、IZO/Ag等复合薄膜，ITO厚度为10～50nm，Ag金属薄膜5a厚度为20～100nm。
如图2i所示，把沉积完导电薄膜10a的基板放入剥离机台里，使用光刻胶剥离液去除残留的光刻胶，通过剥离工艺同时去除光刻胶上沉积的导电薄膜10a，形成第一电极连接线15a、第二电极连接线15b、第三电极连接线15c、像素电极10。
如图2j所示，在完成上述步骤的基底1上，通过构图工艺形成包括像素限定层11的图形。其中，像素限定层的材料可以为亚克力(Acrylic)、聚酰亚胺(PI)等，厚度在1～4um之间。
需要说明的是，上述步骤中是以形成栅线条16a为例进行说明的，当然形成数据线条，以及完整的栅线也是可行，具体的在 通过构图工艺在钝化层6中形成所述第一过孔14a、第二过孔14b、第三过孔14c、第四过孔14d的同时形成将每条所述数据线17中两相邻所述数据线条连接的第六过孔。
在形成像素电极10的同时形成通过所述第六过孔将每条所述数据线17中两相邻所述数据线条连接的第四电极连接线的图形。
实施例3：
本实施例提供一种显示装置，其包括实施例2中的阵列基板，故本实施例的显示装置的成本较低。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本实施例的显示装置中还可以包括其他常规结构，如显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (8)

1.一种低温多晶硅薄膜晶体管的制备方法，其特征在于，包括如下步骤：
在基底上通过一次构图工艺形成包括薄膜晶体管栅极、源极、漏极、栅极绝缘层、有源层的图形，其中，所述栅极、源极、漏极同层设置，所述栅极绝缘层设于所述栅极上方，所述有源层设于所述栅极绝缘层上方，且所述栅极、栅极绝缘层、有源层三者图案相同；
在完成上述步骤的基底上形成钝化层，并通过构图工艺在钝化层中形成与所述源极位置对应的第一过孔、与所述漏极位置对应的第二过孔、与所述有源层位置所对应的第三过孔和第四过孔，以及用于通过所述第一过孔和第三过孔将所述源极与所述有源层连接的第一电极连接线和通过所述第二过孔和第四过孔将所述漏极与所述有源层连接的第二电极连接线的图形。
2.根据权利要求1所述的低温多晶硅薄膜晶体管的制备方法，其特征在于，所述在基底上通过一次构图工艺形成包括薄膜晶体管栅极、源极、漏极、栅极绝缘层、有源层的图形的步骤具体包括：
在基底上依次沉积金属薄膜、栅极绝缘层薄膜、有源层薄膜，并在有源层薄膜上涂覆第一光刻胶层；
对第一光刻胶层进行曝光、显影，其中与源极和漏极位置相对应的剩余光刻胶的厚度为第一厚度，与栅极位置相对应的剩余的光刻胶的厚度为第二厚度，第一厚度小于第二厚度；
去除裸露的有源层薄膜；
去除裸露的栅极绝缘层薄膜；
去除裸露的金属薄膜；
去除第一厚度的光刻胶；
去除裸露的有源层薄膜；
去除裸露的栅极绝缘层薄膜；
去除剩余的光刻胶。
3.根据权利要求1或2所述的低温多晶硅薄膜晶体管的制备方法，其特征在于，所述形成第一过孔、第二过孔、第三过孔、第四过孔、第一电极连接线、第二电极连接线的步骤具体包括：
在形成有钝化层的基底上涂覆第二光刻胶层，并对第二光刻胶层进行曝光、显影，其中与所述第一电极连接线、第二电极连接线位置所对应的光刻胶的厚度为第三厚度，除与所述第一过孔、第二过孔、第三过孔、第四过孔位置所对应的其他区域的光刻胶厚度为第四厚度，第三厚度小于第四厚度；
去除裸露的钝化层，形成第一过孔、第二过孔、第三过孔、第四过孔；
去除第三厚度的光刻胶；
形成导电薄膜；
剥离去除剩余的光刻胶，同时去除光刻胶上方的导电薄膜，形成第一电极连接线和第二电极连接线。
4.一种阵列基板的制备方法，其特征在于，包括权利要求1至3中任意一项所述低温多晶硅薄膜晶体管的制备方法。
5.根据权利要求4所述的阵列基板的制备方法，其特征在于，所述通过构图工艺形成第一过孔、第二过孔、第三过孔、第四过孔、第一电极连接线、第二电极连接线的同时还包括形成像素电极图形，其中，所述像素电极与所述第二电极连接线连接；
在形成有像素电极的基底上，通过构图工艺形成包括像素限定层的图形。
6.根据权利要求5所述的阵列基板的制备方法，其特征在于，所述形成第一过孔、第二过孔、第三过孔、第四过孔、第一电极连接线、第二电极连接线，以及像素电极的步骤具体包括：
在形成有钝化层的基底上涂覆第二光刻胶层，并对第二光刻胶层进行曝光、显影，其中与所述第一电极连接线、第二电极连接线、像素电极位置所对应的光刻胶的厚度为第三厚度，除与所述第一过孔、第二过孔、第三过孔、第四过孔位置所对应的其他区域的光刻胶厚度为第四厚度，第三厚度小于第四厚度；
去除裸露的钝化层，形成第一过孔、第二过孔、第三过孔、第四过孔；
去除第三厚度的光刻胶；
形成导电薄膜；
剥离去除剩余的光刻胶，同时去除光刻胶上方的导电薄膜，形成第一电极连接线、第二电极连接线，以及像素电极。
7.根据权利要求4至6中任意一项所述阵列基板的制备方法，其特征在于，所述在基底上通过一次构图工艺形成包括薄膜晶体管栅极、源极、漏极、栅极绝缘层、有源层的图形的步骤同时还包括形成栅线条、数据线的图形，其中，所述栅线条与所述数据线相互绝缘，且所述栅线条和所述数据线与所述栅极、源极、漏极同层设置，材料相同；
所述通过构图工艺在钝化层中形成所述第一过孔、第二过孔、第三过孔、第四过孔的同时还包括形成用于将每条所述栅线两相邻栅极条连接的第五过孔；
所述形成像素电极的同时还包括形成通过所述第五过孔将每条所述栅线中两相邻所述栅极条连接的第三电极连接线的图形。
8.根据权利要求4至6中任意一项所述阵列基板的制备方法，其特征在于，所述在基底上通过一次构图工艺形成包括薄膜晶体管栅极、源极、漏极、栅极绝缘层、有源层的图形的步骤同时还包括形成数据线条、栅线的图形，其中，所述数据线条与所述栅线相互绝缘，且所述数据线条和所述栅线与所述栅极、源极、漏极同层设置，材料相同；
所述通过构图工艺在钝化层中形成所述第一过孔、第二过孔、第三过孔、第四过孔的同时还包括形成将每条所述数据线中两相邻所述数据线条连接的第六过孔；
所述形成像素电极的同时还包括形成通过所述第六过孔将每条所述数据线中两相邻所述数据线条连接的第四电极连接线的图形。
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