WO2013127206A1 - 一种像素驱动电路及其制备方法、阵列基板 - Google Patents

一种像素驱动电路及其制备方法、阵列基板 Download PDF

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Publication number
WO2013127206A1
WO2013127206A1 PCT/CN2012/085169 CN2012085169W WO2013127206A1 WO 2013127206 A1 WO2013127206 A1 WO 2013127206A1 CN 2012085169 W CN2012085169 W CN 2012085169W WO 2013127206 A1 WO2013127206 A1 WO 2013127206A1
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layer
tft
gate
driving
driving tft
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PCT/CN2012/085169
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French (fr)
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姜春生
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京东方科技集团股份有限公司
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Priority to US14/124,763 priority Critical patent/US9099497B2/en
Publication of WO2013127206A1 publication Critical patent/WO2013127206A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel driving circuit and a method for fabricating the same, and an array substrate including the pixel driving circuit. Background technique
  • the pixel driving circuit of the AMOLED (Active Matrix/Organic Light Emitting Diode) display is usually a TFT (Thin Film Transistor), and the TFT is used as a driving OLED (Organic Light-Emitting).
  • Diode, organic light emitting diode), PLED (olymer light-emitting diode) panel which has ten times the carrier concentration of amorphous silicon compared with amorphous silicon.
  • the TFT can be prepared by a sputtering method, so that it is not necessary to significantly change the existing liquid crystal panel production line at the time of introduction. At the same time, due to the limitations of equipment such as ion implantation and laser crystallization, it is more conducive to the production of large-area glass backsheets than polysilicon technology.
  • the switching layer connection technique of the switching TFT and the driving TFT is a key technology. At present, the following two methods are mainly used:
  • a gate TFT and a gate metal 101 for driving the TFT are deposited on the glass substrate and etched, and a gate insulating (GI) layer 102 is deposited to form a cross-sectional pattern as shown in FIG.
  • GI gate insulating
  • An indium gallium oxide (IGZO) layer 103 is deposited on the GI layer 102 at the position of the switching TFT, and the IGZO layer 103 is etched by wet etching, followed by deposition of an ESL (etch barrier layer) layer 104. Etching, forming a cross-sectional pattern as shown in Figure 1-2;
  • the GI layer 102 on the Gate metal 101 of the driving TFT is opened to form a cross-sectional pattern as shown in FIGS. 1-3, and the source/drain (S/D) metal 105 and the driving TFT of the switching TFT are deposited.
  • S/D (not shown) forms a cross-sectional pattern as shown in Figures 1-4;
  • a protective layer (PVX layer) 106 is deposited to form a cross-sectional pattern as shown in FIG. 1-5; a Via hole etching is performed to expose the drain of the switching TFT and the gate of the driving TFT, as shown in FIG. 1-6. A cross-sectional pattern is shown; an ITO (Indium Tin Oxide) layer 107 is deposited to form a cross-sectional pattern as shown in FIG. 7, thereby achieving a jumper connection of the switching TFT and the driving TFT.
  • PVX layer PVX layer
  • Method 2 depositing a switch TFT and a gate metal 101 driving the TFT on the glass substrate and etching, depositing the GI layer 102 to form a cross-sectional pattern as shown in FIG. 1-1;
  • the etching ratio of the drain environment (such as molybdenum Mo metal) and the GI layer (nano-silica SiOx) and the protective layer (silicon nitride SiNx) in the atmosphere environment using the dry etching process is guaranteed.
  • the GI layer on the gate metal of the driving TFT is etched and a via hole is formed to form a cross-sectional pattern as shown in FIG. 2-2; then the ITO layer 107 is deposited to form
  • the cross-sectional diagram shown in Figure 2-3 implements the layer jump connection between the switching TFT and the driving TFT.
  • the present invention provides a pixel driving circuit, a method of fabricating the same, and an array substrate for efficiently implementing a germanium layer connection between a switching TFT and a driving TFT.
  • the present invention provides a method for fabricating a pixel driving circuit, wherein the pixel driving circuit includes a switching thin film field effect transistor TFT and a driving TFT including: a) sequentially forming a gate of the switching TFT and the driving TFT, a gate insulating GI layer, an oxide semiconductor layer, and an etch barrier ESL layer on the substrate;
  • the present invention provides a pixel driving circuit including a switching thin film field effect transistor TFT and a driving TFT, the switching TFT and the driving TFT each including a gate, a gate insulating GI layer, an oxide semiconductor layer, and an etch barrier
  • the ESL layer, the source/drain, the drain of the switching TFT is connected to the gate of the driving TFT via an indium tin oxide ITO layer, and the pixel driving circuit is prepared by the above pixel driving circuit preparation method.
  • the present invention provides an array substrate comprising a pixel driving circuit prepared by the above method of preparing a pixel driving circuit.
  • the pixel driving circuit, the manufacturing method thereof and the array substrate provided by the invention have the following beneficial effects:
  • FIG. 1-1 to FIG. 1-7 are cross-sectional views obtained in the process of preparing a pixel driving circuit in the prior art
  • FIG. 2-1 to FIG. 2-3 are cross-sectional views obtained in the process of preparing a pixel driving circuit in the prior art
  • FIG. 3 is a flow chart of a method for preparing a pixel driving circuit according to an embodiment of the present invention
  • 4 to 4 to 4 are schematic cross-sectional views showing a method of fabricating a pixel driving circuit according to an embodiment of the present invention
  • FIG. 5 is a top plan view of a pixel driving circuit prepared according to an embodiment of the present invention. detailed description
  • the pixel driving circuit includes a switching thin film field effect transistor TFT and a driving TFT, as shown in FIG. 3, and includes:
  • the deposited gate insulating layer 202 covers the entire surface of the glass substrate.
  • a GI layer is formed using silicon nitride SiNx or silicon oxide SiOx.
  • the oxide semiconductor layer 203 may be indium gallium oxide as IGZO, or gallium oxide may be used as IZO or the like.
  • the IGZO layer is deposited and etched by wet etching, the etched IGZO layer is over the gates of the switching TFT and the driving TFT, and the upper portion of the gate of the driving TFT is not covered with the IGZO layer, so as to facilitate The switching TFT is connected to the jump layer of the driving TFT.
  • FIG. 4-1 shows a cutaway view of the portion of the upper portion of the gate electrode of the driving TFT which is not covered with the IGZO layer.
  • the etched ESL layer is over the gates of the switching TFT and the driving TFT, since the ESL layer is deposited on the IGZO layer, and the upper portion of the gate of the driving TFT is not covered by the IGZO Therefore, the upper portion of the gate of the driving TFT is also not covered by the ESL layer to facilitate the jump layer connection between the switching TFT and the driving TFT, and the ESL layer specifically uses the silicon oxide SiOx to form the ESL layer.
  • the S/D metal by using a sputtering technique and etch it. After etching, the drain metal 205 of the switching TFT is covered on the gate metal of the driving TFT, as shown in FIG. 4-1.
  • the cross-sectional pattern shown, preferably, the S/D metal ruthenium metal Mo or the ruthenium Mo/Al/Mo, the specific etching technique can be etched by the existing method, and will not be described in detail herein.
  • the IGZO layer is deposited and etched by wet etching, the etched IGZO layer is over the gates of the switching TFT and the driving TFT, and the upper portion G of the gate of the driving TFT is not covered with the IGZO layer, It is convenient to connect the switching TFT to the jump layer of the driving TFT.
  • the etched ESL layer is over the gates of the switching TFT and the driving TFT, since the ESL layer is deposited on the IGZO layer, and the upper portion of the gate of the driving TFT is not covered by the IGZO layer, thus driving the gate of the TFT
  • the upper portion of the pole is also not covered by the ESL layer to facilitate the jumper connection between the switching TFT and the driving TFT, and the ESL layer is specifically made of silicon oxide SiOx to form the ESL layer.
  • Fig. 4-1 shows a cutaway view of the portion of the upper portion of the gate of the driving TFT which is not covered by the ESL layer.
  • the S/D metal by using a sputtering technique and etch it. After etching, the drain metal 205 of the switching TFT is covered on the gate metal of the driving TFT, as shown in FIG. 4-1.
  • the cross-sectional pattern shown, preferably, the S/D metal ruthenium metal Mo or the ruthenium Mo/Al/Mo, the specific etching technique can be etched by the existing method, and will not be described in detail herein.
  • the wet etching process and the dry etching process mentioned in the embodiments of the present invention can be specifically implemented by using the existing process flow, and the etching process will not be described in detail herein.
  • the embodiment of the invention further provides an array substrate, wherein the array substrate comprises a pixel driving circuit obtained by the pixel driving circuit preparation method provided by the embodiment of the invention.
  • the present invention cover the modifications and variations of the inventions

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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
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Abstract

本发明公开了一种像素驱动电路及其制备方法及阵列基板，像素驱动电路包括开关TFT和驱动TFT该方法包括：a）在基板上依次同时制作开关TFT 和驱动TFT的栅极、栅绝缘GI层、氧化物半导体层、ESL层；b）同时开关TFT和驱动TFT的源极/漏极金属，经刻蚀所述开关TFT的漏极金属延伸覆盖在驱动TFT的栅极上方的GI层上；c）沉积保护层；d）利用过孔工艺将过孔处的保护层、开关TFT的漏极金属及GI层刻蚀掉，露出驱动TFT的栅极； e）在过孔处沉积连接开关TFT的漏极及驱动 TFT的栅极的氧化铟锡ITO层。本发明增加了背板的开口率且降低了干刻刻蚀比的开发及工艺的复杂性。

Description

一种像素驱动电路及其制备方法、 阵列基板 技术领域
本发明涉及显示技术领域， 尤其涉及一种像素驱动电路及其制备方法、 以及包括所述像素驱动电路的阵列基板。 背景技术
AMOLED ( Active Matrix/Organic Light Emitting Diode, 有源矩阵 /有机 发光二极体面板）显示器的像素驱动电路通常釆用 TFT( Thin Film Transistor, 薄膜场效应晶体管） ， TFT作为驱动 OLED ( Organic Light-Emitting Diode, 有机发光二极管）、 PLED ( olymer light-emitting diode, 高分子发光二极管） 面板， 与非晶硅相比， 其载流子浓度是非晶硅的十倍。 另外， TFT可通过溅 射（Sputter )的方法制备， 因此导入时无需大幅改变现有的液晶面板生产线。 同时， 由于没有离子注入及激光晶化等设备的限制， 相对于多晶硅技术， 更 有利于大面积的玻璃背板的生产。
像素驱动电路包含两个 TFT和一个存储电容器， 其中一个为开关 TFT ( Switching TFT ) , 另一个为驱动 TFT ( Driving TFT ) 。 在扫描线开启时， 开关 TFT的栅极上施加一定电压，电流从栅极流向漏极，并通过 ITO( Indium Tin Oxides, 纳米铟锡金属氧化物 )层传输到驱动 TFT, 使驱动 TFT导通， 电流从栅极流向漏极， 驱动 TFT与存储电容器连接， 从而为电容器充电， 当 扫描线关闭时， 存储于电容器中的电压仍能保持驱动 TFT在导通状态， 故能 在一个画面内维持 OLED的固定电流。
开关 TFT和驱动 TFT由于处于不同层， 因此开关 TFT和驱动 TFT的 跳层连接技术是关键技术。 目前主要釆用以下两种方式：
方式 1: 如图 1-1〜图 1-7所示， 主要包括以下过程：
在玻璃基板上沉积开关 TFT和驱动 TFT的栅极（ Gate )金属 101并刻蚀， 沉积栅绝缘（GI )层 102, 形成图 1-1所示的截面图形；
在 GI层 102上开关 TFT的位置沉积氧化铟镓辞 ( IGZO )层 103 , 利用 湿法刻蚀对 IGZO层 103进行刻蚀， 随后沉积 ESL (刻蚀阻挡层）层 104并 刻蚀， 形成如图 1-2所示截面图形；
利用干刻技术， 在驱动 TFT的 Gate金属 101上的 GI层 102开口， 形成 如图 1-3所示截面图形， 并沉积开关 TFT的源极 /漏极 ( S/D )金属 105和驱 动 TFT的 S/D (图中未示出） ， 形成如图 1-4所示截面图形；
然后沉积保护层（PVX层） 106, 形成如图 1-5所示截面图形； 进行过 孔 ( Via Hole )刻蚀， 露出开关 TFT的漏极和驱动 TFT的栅极，形成如图 1-6 所示的截面图形； 沉积 ITO ( Indium Tin Oxide, 氧化铟锡）层 107, 形成如 图 7所示的截面图形， 从而实现开关 TFT和驱动 TFT的跳层连接。
此方法虽然可以实现开关 TFT和驱动 TFT的跳层的可靠连接， 但在驱 动 TFT 的 Gate金属的 GI层上开口时， 是需要在图 1-2上添加一张掩膜 MASK, 釆用掩膜工艺进行开口， 不利于节约成本且降低了制备效率。
方式 2: 在玻璃基板上沉积开关 TFT和驱动 TFT的 Gate金属 101并刻 蚀， 沉积 GI层 102, 形成图 1-1所示的截面图形；
在 GI层 102上开关 TFT的位置沉积 IGZO层 103 ,利用湿法刻蚀对 IGZO 层 103进行刻蚀， 沉积 ESL层 104并刻蚀， 形成如图 1 -2所示截面图形； 沉积开关 TFT的源极 /漏极（ S/D )金属 105和驱动 TFT的 S/D (图中未 示出） ， 随后沉积保护层 106, 形成如图 2-1所示截面图形； 进行过孔刻蚀， 利用干刻工艺釆用的气氛环境对漏极（Drain )金属（如钼 Mo金属）及 GI 层（纳米二氧化硅 SiOx ) 、 保护层（氮化硅 SiNx ) 的不同的刻蚀比， 在保 证漏极金属未被刻蚀掉的前提下， 将驱动 TFT的栅极金属上的 GI层刻蚀干 净并形成过孔， 形成如图 2-2所示截面图形； 随后沉积 ITO层 107, 形成如 图 2-3所示截面图形， 实现开关 TFT和驱动 TFT的跳层连接。
虽然釆用此方法可以减少一张 MASK, 但需要调节干刻工艺， 提高干刻 气氛对 Mo金属及 SiOx、 SiNx的不同的刻蚀比， 增加了工艺的复杂性。 发明内容
本发明提供一种像素驱动电路及其制备方法及阵列基板， 用以高效率地 实现开关 TFT和驱动 TFT的 ϋ层连接。
本发明提供一种像素驱动电路的制备方法， 所述像素驱动电路包括开关 薄膜场效应晶体管 TFT和驱动 TFT包括： a)在基板上依次同时制作开关 TFT和驱动 TFT的栅极、 栅绝缘 GI层、 氧化物半导体层、 刻蚀阻挡 ESL层；
b) 同时沉积开关 TFT和驱动 TFT 的源极 /漏极金属， 经刻蚀所述开关 TFT的漏极金属延伸覆盖在驱动 TFT的栅极上方的 GI层上；
c)沉积保护层；
d) 利用过孔工艺将过孔处的保护层、开关 TFT的漏极金属及 GI层刻蚀 掉， 露出驱动 TFT的栅极； 和
e)在过孔处沉积连接开关 TFT 的漏极及驱动 TFT 的栅极的氧化铟锡 ITO层。
本发明提供一种像素驱动电路， 所述像素驱动电路包括开关薄膜场效应 晶体管 TFT和驱动 TFT, 所述开关 TFT和驱动 TFT均包括栅极、 栅绝缘 GI 层、 氧化物半导体层、 刻蚀阻挡 ESL层、 源极 /漏极， 所述开关 TFT的漏极 经氧化铟锡 ITO层与所述驱动 TFT的栅极连接在一起，所述像素驱动电路釆 用上述像素驱动电路制备方法制备得到。
本发明提供一种阵列基板， 所述阵列基板包括釆用上述像素驱动电路制 备方法制备得到的像素驱动电路。
利用本发明所提供的像素驱动电路及其制备方法及阵列基板， 具有以下 有益效果：
1 ) 由于仅在驱动 TFT的栅极上方开口， 增加了背板的开口率；
2 ) 由于仅在驱动 TFT的栅极上方开口， 刻蚀时不需要考虑对不同处刻 蚀时的刻蚀比， 减少 SiOx及 Mo金属的干刻刻蚀比的开发及工艺的复杂性； 3 )在增加背板开口率和减少工艺复杂性的条件下，保证一个像素内， 开 关 TFT和驱动 TFT的跳层连接。 附图说明
图 1-1〜图 1-7为现有技术中釆用方式 1制备像素驱动电路过程中得到的 截面图；
图 2-1〜图 2-3为现有技术中釆用方式 2制备像素驱动电路过程中得到的 截面图；
图 3为本发明实施例像素驱动电路制备方法流程图； 图 4_i〜图 4_4为本发明实施例像素驱动电路制备方法过程中得到的截面 图；
图 5为本发明实施例制备的像素驱动电路的俯视图。 具体实施方式
下面结合附图和实施例对本发明提供的像素驱动电路及其制备方法及阵 列基板进行详细地说明。
本发明实施例提供的像素驱动电路的制备方法， 所述像素驱动电路包括 开关薄膜场效应晶体管 TFT和驱动 TFT, 如图 3所示， 包括：
步骤 301 , 在基板上依次同时制作开关 TFT和驱动 TFT的栅极、栅绝缘
GI层、 氧化物半导体层、 刻蚀阻挡 ESL层；
显示器的每个像素内具有一个像素驱动电路， 像素驱动电路包括开关
TFT和驱动 TFT,开关 TFT和驱动 TFT釆用相同的结构 ,不同的是开关 TFT 与数据扫描线连接， 驱动 TFT与存储电容器连接。
步骤 302, 同时沉积开关 TFT和驱动 TFT的源极 /漏极金属， 经刻蚀所 述开关 TFT的漏极金属延伸覆盖在驱动 TFT的栅极上方的 GI层上；
在 ESL上沉积开关 TFT和驱动 TFT的源极 /漏极 ( S/D )金属， 这样， 在开关 TFT/驱动 TFT的栅极上施加一定电压时， 电流从开关 TFT/驱动 TFT 的源极流向漏极。
步骤 303, 沉积保护层；
具体地， 沉积的保护层覆盖整个阵列基板表面。
步骤 304, 利用过孔工艺将过孔处的保护层、 开关 TFT 的漏极金属及 GI层刻蚀掉， 露出驱动 TFT的栅极；
步骤 305,在过孔处沉积连接开关 TFT的漏极及驱动 TFT的栅极的氧化 铟锡 ITO层。
本发明实施例提供的像素驱动电路制备方法， 在开关 TFT和驱动 TFT 的制作过程中， 釆用延长开关 TFT的漏极金属并覆盖在驱动 TFT的栅极金 属上， 利用刻蚀技术在此位置上方开口， 将保护层、 S/D层及 GI层刻蚀掉， 形成过孔， 使得栅极金属露于背板表面， 然后沉积 ITO, 实现开关 TFT和驱 动 TFT的跳层连接， 可见， 由于本发明实施例可以优化以下问题： 1 ) 由于仅在驱动 TFT的栅极上方开口， 增加了背板的开口率；
2 ) 由于仅在驱动 TFT上方开口， 刻蚀时不需要考虑对不同处刻蚀时的 刻蚀比， 减少 SiOx及 Mo金属的干刻刻蚀比的开发及工艺的复杂性；
3 )在增加背板开口率和减少工艺复杂性的条件下，保证一个像素内， 开 关 TFT和驱动 TFT的跳层连接。
实施例 1
下面结合图 4-1〜图 4-4详细说明本发明实施例提供的像素电路的制备方 法， 详细过程 ^下：
1 )在玻璃基板上沉积栅极金属并刻蚀， 制作出开关 TFT和驱动 TFT的 栅极 201 ;
具体地， 这里的栅极 201 包括开关 TFT的栅极和驱动 TFT的栅极， 具 体的刻蚀过程可以釆用现有方法， 这里不再详述。
优选地，具体釆用金属钼 Mo,或者釆用钼 Mo/铝 A1/钼 Mo制作开关 TFT 和驱动 TFT的栅极， 其中 Mo/Al/Mo是三层金属， 分别是 Mo金属层、 A1 层及 Mo金属层， 两层 Mo金属起保护作用， 而 A1层起导电作用。
2 )沉积开关 TFT和驱动 TFT的栅绝缘（ GI )层 202;
优选地， 沉积的栅绝缘层 202覆盖整个玻璃基板表面。
具体釆用氮化硅 SiNx或氧化硅 SiOx制作 GI层。
3 )在 GI层上沉积开关 TFT和驱动 TFT的氧化物半导体层 203并进行 刻蚀；
优选地， 氧化物半导体层 203可以釆用氧化铟镓辞 IGZO, 也可釆用氧 化镓辞 IZO等。
优选地， 沉积 IGZO层并利用湿法刻蚀进行刻蚀， 刻蚀后的 IGZO层在 开关 TFT和驱动 TFT的栅极上方， 且驱动 TFT的栅极上方部分区域未被覆 盖 IGZO层， 以方便开关 TFT与驱动 TFT的跳层连接。
本实施例为了清楚地表示开关 TFT和驱动 TFT的跳层连接，图 4-1给出 的是驱动 TFT的栅极上方部分区域未被覆盖 IGZO层的切面图。 优选地， 刻蚀后的 ESL层在开关 TFT和驱动 TFT的栅极上方， 由于是 在 IGZO层上沉积 ESL层， 而驱动 TFT的栅极上方部分区域未被覆盖 IGZO 层，因此驱动 TFT的栅极上方部分区域也未被覆盖 ESL层，以方便开关 TFT 与驱动 TFT的跳层连接， ESL层具体釆用氧化硅 SiOx制作 ESL层。
5 )沉积开关 TFT和驱动 TFT的源极 S/漏极 D金属， 经刻蚀所述开关 TFT的漏极金属 205延伸覆盖在驱动 TFT的栅极上方的 GI层上；
本发明实施例中，优选釆用溅射技术沉积 S/D金属并刻蚀，经过刻蚀后， 保证开关 TFT的漏极金属 205覆盖在驱动 TFT的栅极金属上， 得到如图 4-1 所示的截面图形， 优选地， S/D金属釆用金属 Mo或釆用 Mo/Al/Mo, 具体的 刻蚀技术釆用现有方法刻蚀过程即可， 这里不再详述。
6 )沉积保护层（ PVX层） 206;
如图 4-2所示， 本实施例中沉积的保护层 206覆盖整个玻璃基板表面， 优选地， 具体釆用氮化硅 SiNx或氧化硅 SiOx制作保护层。
7 )釆用干刻工艺在驱动 TFT的栅极上方进行过孔刻蚀， 将过孔处的保 护层、 开关 TFT的漏极金属及 GI层刻蚀掉， 形成过孔， 露出驱动 TFT的栅 极， 得到如图 4-3所示的截面图形。
8 )在过孔处沉积氧化铟锡 ITO 207, 实现开关 TFT和驱动 TFT的跳层 连接， 得到如图 4-4所示的截面图形。
至此， 制作出像素驱动电路的驱动 TFT和驱动 TFT并实现了跳层连接， 进一步地， 该像素驱动电路还包括存储电容器， 将驱动 TFT与存储电容器连 接， 从而能够实现像素驱动电路的功能， 如图 5所示一个像素内像素驱动电 路的俯视图， 开关 TFT的漏极 205通过过孔与驱动 TFT的栅极连接。
实施例 2
1 )在玻璃基板上沉积栅极金属并刻蚀， 制作出开关 TFT和驱动 TFT的 栅极 201 ;
具体地， 这里的栅极 201 包括开关 TFT的栅极和驱动 TFT的栅极， 具 体的刻蚀过程可以釆用现有方法， 这里不再详述。
优选地，具体釆用金属钼 Mo,或者釆用钼 Mo/铝 A1/钼 Mo制作开关 TFT 和驱动 TFT的栅极。
2 )沉积开关 TFT和驱动 TFT的栅绝缘（ GI )层 202;
优选地， 沉积的栅绝缘层 202覆盖整个玻璃基板表面。
具体釆用氮化硅 SiNx或氧化硅 SiOx制作 GI层。 3 )在 GI层上沉积开关 TFT和驱动 TFT的氧化物半导体层 203并进行 刻独；
优选地， 沉积 IGZO层并利用湿法刻蚀进行刻蚀， 刻蚀后的 IGZO层在 开关 TFT和驱动 TFT的栅极上方， 且驱动 TFT的栅极上方部分区域 G未被 覆盖 IGZO层， 以方便开关 TFT与驱动 TFT的跳层连接。 优选地， 刻蚀后的 ESL层在开关 TFT和驱动 TFT的栅极上方， 由于是 在 IGZO层上沉积 ESL层， 而驱动 TFT的栅极上方部分区域未被覆盖 IGZO 层，因此驱动 TFT的栅极上方部分区域也未被覆盖 ESL层，以方便开关 TFT 与驱动 TFT的跳层连接， ESL层具体釆用氧化硅 SiOx制作 ESL层。
本实施例为了清楚地表示开关 TFT和驱动 TFT的跳层连接，图 4-1给出 的是驱动 TFT的栅极上方部分区域未被覆盖 ESL层的切面图。
5 )沉积开关 TFT和驱动 TFT的源极 S/漏极 D金属， 经刻蚀所述开关 TFT的漏极金属 205延伸覆盖在驱动 TFT的栅极上方的 GI层上；
本发明实施例中，优选釆用溅射技术沉积 S/D金属并刻蚀 ,经过刻蚀后 , 保证开关 TFT的漏极金属 205覆盖在驱动 TFT的栅极金属上， 得到如图 4-1 所示的截面图形， 优选地， S/D金属釆用金属 Mo或釆用 Mo/Al/Mo, 具体的 刻蚀技术釆用现有方法刻蚀过程即可， 这里不再详述。
6 )沉积保护层 206;
如图 4-2所示， 本实施例中沉积的保护层 206覆盖整个玻璃基板表面， 优选地， 具体釆用氮化硅 SiNx或氧化硅 SiOx制作保护层。
7 )在驱动 TFT的栅极上方进行过孔刻蚀， 釆用干刻工艺将过孔处的保 护层刻蚀掉， 然后利用湿刻工艺将过孔处的开关 TFT 的漏极金属完全刻蚀 掉， 最后利用干刻工艺将过孔处的 GI层刻蚀掉， 形成过孔， 露出驱动 TFT 的栅极， 得到如图 4-3所示的截面图形。
8 )在过孔处沉积氧化铟锡 ITO 207, 实现开关 TFT和驱动 TFT的跳层 连接， 得到如图 4-4所示的截面图形。
本发明实施例提及的湿刻工艺和干刻工艺具体可以釆用现有工艺流程实 现， 这里不再详述刻蚀过程。
本发明实施例中还提供一种像素驱动电路， 所述像素驱动电路包括开关 薄膜场效应晶体管 TFT和驱动 TFT,所述开关 TFT和驱动 TFT均包括栅极、 栅绝缘 GI层、氧化物半导体层、刻蚀阻挡 ESL层、源极 /漏极，所述开关 TFT 的漏极经氧化铟锡 ITO层与所述驱动 TFT的栅极连接在一起，所述像素驱动 电路釆用本发明实施例所提供的像素驱动电路制备方法制备得到， 开关 TFT 和驱动 TFT共用一个过孔实现跳层连接， 由于仅使用一个过孔， 因此增加了 背板的开口率。
本发明实施例还提供了一种阵列基板， 所述阵列基板包括釆用本发明实 施例所提供的像素驱动电路制备方法得到的像素驱动电路。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权利要求书
1、一种像素驱动电路的制备方法，所述像素驱动电路包括开关薄膜场效 应晶体管 TFT和驱动 TFT, 包括：
a)在基板上依次同时制作开关 TFT和驱动 TFT的栅极、 栅绝缘 GI层、 氧化物半导体层、 刻蚀阻挡 ESL层；
b) 同时沉积开关 TFT和驱动 TFT 的源极 /漏极金属， 经刻蚀所述开关 TFT的漏极金属延伸覆盖在驱动 TFT的栅极上方的 GI层上；
c)沉积保护层；
d) 利用过孔工艺将过孔处的保护层、开关 TFT的漏极金属及 GI层刻蚀 掉， 露出驱动 TFT的栅极；
e)在过孔处沉积连接开关 TFT 的漏极及驱动 TFT 的栅极的氧化铟锡 ITO层。
2、 如权利要求 1所述的方法， 其中， 步骤 d )中利用过孔工艺将过孔处 的保护层、 开关 TFT的漏极金属及 GI层刻蚀掉进一步包括：
釆用干刻工艺在驱动 TFT的栅极上方进行过孔刻蚀，将过孔处的保护层 层、 开关 TFT的漏极金属及 GI层刻蚀掉， 露出驱动 TFT的栅极。
3、 如权利要求 1所述的方法， 其中， 步骤 d )中利用过孔工艺将过孔处 的保护层、 开关 TFT的漏极金属及 GI层刻蚀掉进一步包括：
在驱动 TFT的栅极上方进行过孔刻蚀，釆用干刻工艺将过孔处的保护层 刻蚀掉， 然后利用湿刻工艺将过孔处的开关 TFT的漏极金属刻蚀掉， 最后利 用干刻工艺将过孔处的 GI层刻蚀掉， 露出驱动 TFT的栅极。
4、 如权利要求 1所述的方法， 其中， 步骤 a )中制作氧化物半导体层进 一步包括：
在 GI层上沉积氧化物半导体层并利用湿法刻蚀进行刻蚀， 刻蚀后的氧 化物半导体层在开关 TFT和驱动 TFT的栅极上方， 且驱动 TFT的栅极上方 部分区域未被覆盖氧化物半导体层。
5、如权利要求 4所述的方法，其中，步骤 a )中制作 ESL层进一步包括： 在氧化物半导体层上沉积 ESL层并进行刻蚀， 刻蚀后的 ESL层在开关 TFT的栅极和驱动 TFT的栅极上方。
6、 如权利要求 1所述的方法， 其中， 具体釆用金属钼 Mo, 或者釆用钼 Mo/铝 A1/钼 Mo制作开关 TFT的栅极及驱动 TFT的栅极。
7、如权利要求 1所述的方法，其中，具体釆用氮化硅 SiNx或氧化硅 SiOx 制作 GI层。
8、如权利要求 1所述的方法，其中，具体釆用氧化硅 SiOx制作 ESL层。
9、如权利要求 1所述的方法，其中，具体釆用氮化硅 SiNx或氧化硅 SiOx 制作保护层。
10、 如权利要求 1所述的方法， 其中， 所述像素驱动电路还包括存储电 容器， 所述方法还包括：
f) 将所述驱动 TFT与存储电容器连接。
11、 一种像素驱动电路， 所述像素驱动电路包括开关薄膜场效应晶体管 TFT和驱动 TFT, 所述开关 TFT和驱动 TFT均包括栅极、 栅绝缘 GI层、 氧 化物半导体层、 刻蚀阻挡 ESL层、 源极 /漏极， 所述开关 TFT的漏极经氧化 铟锡 ITO层与所述驱动 TFT的栅极连接在一起。
12、 一种阵列基板， 其中， 所述阵列基板包括权 11所述像素驱动电路。
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