WO2015100897A1 - 阵列基板及其制备方法、显示装置 - Google Patents
阵列基板及其制备方法、显示装置 Download PDFInfo
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- WO2015100897A1 WO2015100897A1 PCT/CN2014/076621 CN2014076621W WO2015100897A1 WO 2015100897 A1 WO2015100897 A1 WO 2015100897A1 CN 2014076621 W CN2014076621 W CN 2014076621W WO 2015100897 A1 WO2015100897 A1 WO 2015100897A1
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- Prior art keywords
- thin film
- film transistor
- gate
- forming
- array substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 238000002360 preparation method Methods 0.000 title abstract description 14
- 239000010409 thin film Substances 0.000 claims abstract description 116
- 238000000034 method Methods 0.000 claims abstract description 38
- 238000000059 patterning Methods 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 17
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract 1
- 229920001621 AMOLED Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
Definitions
- the invention belongs to the technical field of display device preparation, and particularly relates to an array substrate, a preparation method thereof and a display device. Background technique
- the oxide semiconductor indium gallium zinc oxide (InGaZn0 4 ; IGZO ) is used as a material for the active layer of the thin film transistor because of its high mobility, uniformity and preparation at room temperature.
- the thin film transistor structure is a bottom gate type structure.
- FIG. 1 it is a basic 2T1C pixel structure including: 2 thin film transistors (ie, a first thin film transistor M1 and a second thin film transistor M2), and a storage capacitor C1, a first thin film transistor M1.
- the source is connected to the gate of the second thin film transistor M2.
- the source and drain electrodes 106 of the first and second thin film transistors M1 and M2 and their respective active regions 103 are connected through the second contact vias 105.
- the gate electrode 102 of the second thin film transistor (drive transistor) M2 and the source 106 of the first thin film transistor (switching transistor) M1 are connected through the first contact via 104; by adjusting the gate voltage of the second thin film transistor M2 (ie, The source voltage of the first thin film transistor M1 can control the magnitude of the current flowing through the second thin film transistor M2, thereby controlling the amount of light emitted by the corresponding organic light emitting layer of each pixel unit.
- the technician found that the AMOLED backplane (array substrate) often has leakage phenomenon, which seriously affects the yield of the product.
- the first thin film transistor M1 is used as a switching transistor
- the second thin film transistor M2 is used as a driving tube
- the source and driving of the switching transistor are used.
- Gate of the tube Electrical connections must be made through contact vias.
- two contact via patterns are often formed on the photoresist by the same step exposure development (Mask-Photo) process, and then through the same channel.
- Two contact vias are prepared by dry etching.
- the long-time dry etching at the second contact via 105 causes the material of the active region 103 and the gate insulating layer disposed between the active region 103 and the gate 102 to be further etched and broken.
- the source drain 106 deposited in the subsequent process is connected to the bottom gate 102, thereby causing serious leakage of the backplane, so that the backplane is finally scrapped and the yield is reduced.
- the technical problem to be solved by the present invention includes providing a method for fabricating an array substrate for preventing leakage of a thin film transistor, an array substrate, and a display device in view of the above-described deficiencies of the conventional array substrate.
- the technical solution adopted to solve the technical problem of the present invention is a method for preparing an array substrate, comprising the following steps:
- an active region is formed first, and then a gate is formed, so that the gate is located above the active region, so that the gate metal is etched as a carrier when the second contact via is formed.
- the resistance of the gate metal to the etch is greater than the resistance of the active region material to the etch, so that it can prevent the etch time from being contacted for the second contact when the first contact via and the second contact via are simultaneously formed.
- the hole is relatively long and the gate metal disposed under the second contact via is etched through, thereby causing a problem of leakage of the array substrate.
- the method further includes:
- a buffer layer is formed on the substrate.
- the buffer layer is made of silicon oxide or silicon nitride and has a thickness of between 5 and 500 nm.
- the materials of the source, the drain and the connection of all the thin film transistors are made of any one of molybdenum, copper and aluminum, and the thickness is between l and 500 nm.
- the material of the active region of all the thin film transistors is any one of indium gallium zinc oxide, indium zinc oxide, indium tin oxide, indium gallium tin oxide, amorphous silicon, and polycrystalline silicon, and the thickness thereof is 5 to 200 nm. between.
- the gate material of all of the thin film transistors is any one of molybdenum, copper, and aluminum.
- the technical solution adopted to solve the technical problem of the present invention is an array substrate, It is prepared by any of the above preparation methods.
- the array substrate is an OLED array substrate
- the first thin film transistor is a switching tube
- the second thin film transistor is a driving tube.
- the technical solution adopted to solve the technical problem of the present invention is a display device including the above array substrate.
- 1 is a circuit diagram of a conventional 2T1C pixel structure
- FIG. 2 is a schematic structural view of one side of a conventional array substrate
- FIG. 3 is a schematic structural view of another side of a conventional array substrate
- FIG. 4 is a structural view showing one side of an array substrate prepared by the method for preparing an array substrate according to Embodiment 1 of the present invention
- FIG. 5 is a structural view showing another side of an array substrate prepared by the method for fabricating an array substrate according to Embodiment 1 of the present invention.
- Fig. 6 is a schematic view showing the process of the method of fabricating the array substrate of the embodiment 1 of the present invention.
- the reference numerals are: 101, substrate; 102, gate; 103, active region; 104, first contact via; 105, second contact via; 106, source/drain; 107, buffer layer 108, a gate insulating layer; 109, a connection line; 110, a planarization layer; 111, a deuterated layer; a first thin film transistor M1; and a second thin film transistor M2.
- the method for preparing the array substrate provided in this embodiment will be described with reference to FIGS. 4, 5, and 6.
- the preparation method specifically includes the following steps:
- Step 1 Depositing a buffer layer 107 on the substrate 101 by sputtering.
- the material of the buffer layer 107 may be silicon oxide, silicon nitride or an organic insulating material; Its thickness is preferably between 5 and 500 nm.
- Step 2 On the substrate on which the buffer layer 107 is formed, a pattern including the first thin film transistor and the second thin film transistor active region 103 is formed by a patterning process.
- the buffer layer 107 film may be deposited by magnetron sputtering, and then annealed at 300 ° C for 1 hour in an air atmosphere, and further, a patterned pattern of the active region 103 is formed by a patterning process.
- the material of the active layer may be selected from any one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium tin oxide (InGaSnO), amorphous silicon, polycrystalline silicon, etc., of course. It may be other semiconductor materials; its thickness is preferably between 5 and 200 nm.
- Step 3 On the substrate on which the first thin film transistor and the second thin film transistor active region 103 are formed, a gate insulating layer 108 is formed, and the gate insulating layer 108 covers the thin film transistor active region 103.
- the material of the gate insulating layer 108 is silicon oxide, silicon nitride, and an insulating material such as an organic insulating material; the thickness thereof is preferably between l and 300 nm.
- Step 4 On the substrate on which the gate insulating layer 108 is formed, a pattern including the first thin film transistor and the second thin film transistor gate 102 is formed by a patterning process.
- the material of the gate electrode 102 may be any one of molybdenum (Mo), copper (Cu), and aluminum (A1). Of course, it may be a metal material, an alloy material, or a composite conductive material; the thickness thereof is preferably from 1 to 300 nm. between.
- a planarization layer 110 (electrical insulation) is formed on the substrate on which the first thin film transistor and the second thin film transistor gate 102 are formed.
- the material of the planarization layer 110 may be silicon oxide or silicon nitride, and of course other insulating materials; the thickness is preferably between 5 and 500 mils.
- Step 6 forming a second contact via 105 for electrically connecting the source and drain 106 of the first thin film transistor, the source and drain 106 of the second thin film transistor and the respective active layers 103 thereof by one patterning process, and
- the first contact via 104 is electrically connected to the gate 102 of the second thin film transistor and the source 106 of the first thin film transistor.
- Step 7 forming a pattern of the corresponding source and drain electrodes 106 on the contact vias 105 above the active regions 103 of the first and second thin film transistors by a patterning process, while above the gates 102 of the second thin film transistors Contact via 104 A metal connection line 109 for connecting the gate electrode 102 of the second thin film transistor and the source 106 of the first thin film transistor is formed.
- the material of the source and drain electrodes 106 and the connection line 109 of the two thin film transistors may be any one of molybdenum (Mo), copper (Cu), and aluminum (A1), and may be metal materials, alloy materials, and composites. Conductive material; its thickness is between l ⁇ 500nm.
- the etching time of the first contact via 104 is relatively long.
- the carrier etched by the first contact via 104 is the gate 102, and the metal material of the gate 102 is relatively thick, and the ability to withstand etching is much higher than that of the active region 103. The ability to etch. Therefore, when the first contact via 104 and the second contact via 105 are simultaneously formed, the gate insulating layer 108 under the gate 102 and the gate can be prevented from being etched under the same etching time, thereby causing the gate. 102 is electrically connected to the active layer and even the source and drain electrodes 106, thereby causing leakage of the array substrate, thereby improving the yield of the product.
- Step 8 Form a deuterated layer 111 on the substrate 101 that completes the above steps.
- the material of the deuterated layer 111 may be silicon oxide or silicon nitride; and the thickness thereof is between 5 and 500 nm.
- the gate is disposed between the active layer and the source and drain, so that when the first contact via 104 and the second contact via 105 are formed, the gate 102 metal is used as a long time.
- the etched carrier, and thus the array substrate prepared, has greatly improved leakage resistance.
- this embodiment only describes the preparation of two thin film transistors on the array substrate, and the pixel structure of the array substrate may be 2T1C type.
- the present embodiment is also applicable to a 6T2C type pixel circuit, a timing control circuit, a scan driving circuit, a data driving circuit, a backplane testing circuit, an electrostatic prevention circuit, and a method of preparing a thin film transistor in other functional circuits of a TFT backplane.
- the preparation principle is the same as the above method, and it is not described here that as long as the first contact via 104 and the second contact via 105 of the thin film transistor prepared by the above method are in the protection scope of the present invention. in.
- the source and the drain of the thin film transistor are identical in structure. Therefore, the source and drain are also functionally interchangeable.
- the drain is used as the signal input terminal and the source is used as the signal output terminal; however, the protection range of the present invention is not limited thereto, and the source is used as the signal input end of the TFT and the drain is used as the signal output terminal. It also falls within the scope of protection of the present invention.
- Example 2
- the embodiment provides an array substrate including a plurality of pixel units, each of the pixel units including a first thin film transistor and a second thin film transistor, and a gate electrode 102 and a first thin film of the second thin film transistor.
- the transistor source 106 is connected through a first contact via 104 which is prepared by the preparation method described in Example 1.
- the array substrate includes: an active region 103 of the first thin film transistor and the second thin film transistor formed over the buffer layer 107; a gate of the first thin film transistor and the second thin film transistor formed over the active region 103 An insulating layer 108; a gate electrode 102 of the first thin film transistor and the second thin film transistor formed over the gate insulating layer 108 and corresponding to the respective active regions 103, respectively; a planarization layer 110 formed over the gate electrode 102; Connecting to the source and drain electrodes 106 of the first and second thin film transistors of the respective active regions 103 through the planarization layer 110 and the gate insulating layer 108; and connecting to the first film through the planarization layer 110 The gate 102 of the transistor, and extending over the planarization layer 110, is coupled to the connection line 109 of the source 106 of the second thin film transistor.
- the array substrate is an OLED array substrate
- the first thin film transistor is a switching transistor
- the second thin film transistor is a driving tube
- the source 106 of the switching transistor is connected to the gate 102 of the driving tube.
- the yield of the array substrate is greatly improved.
- the source of the TFT may be used as a signal input terminal of the TFT, and the drain may be used as a signal output terminal.
- the source of the switch will be connected to the data line.
- the image data signal is accessed, and the drain of the switch is connected to the gate of the drive tube for controlling the current through the drive tube.
- the embodiment provides a display device, which includes the array substrate described in Embodiment 2, and the display device may be: OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigation device, etc. A product or part that displays functionality.
- the display device of this embodiment has the array substrate of the first embodiment, so that the yield is greatly improved.
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Abstract
Description
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US14/422,818 US9443875B2 (en) | 2013-12-30 | 2014-04-30 | Manufacturing method for an array substrate that can avoid electrical leakage of thin film transistors |
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CN201310745581.7 | 2013-12-30 | ||
CN201310745581.7A CN103700629B (zh) | 2013-12-30 | 2013-12-30 | 一种阵列基板及其制备方法、显示装置 |
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WO2015100897A1 true WO2015100897A1 (zh) | 2015-07-09 |
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US10277227B2 (en) * | 2016-05-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device layout |
WO2018111247A1 (en) * | 2016-12-13 | 2018-06-21 | Intel Corporation | Passivation dielectrics for oxide semiconductor thin film transistors |
CN107146855A (zh) * | 2017-05-16 | 2017-09-08 | 京东方科技集团股份有限公司 | Oled基板及其制备方法、显示装置 |
KR102432344B1 (ko) * | 2017-09-22 | 2022-08-12 | 삼성디스플레이 주식회사 | 표시 장치 및 이의 제조 방법 |
US11616057B2 (en) | 2019-03-27 | 2023-03-28 | Intel Corporation | IC including back-end-of-line (BEOL) transistors with crystalline channel material |
CN110444602A (zh) * | 2019-08-05 | 2019-11-12 | 深圳市华星光电半导体显示技术有限公司 | 一种氧化物薄膜晶体管的制备方法及阵列基板 |
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US20160035755A1 (en) | 2016-02-04 |
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