CN103700629A - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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CN103700629A
CN103700629A CN201310745581.7A CN201310745581A CN103700629A CN 103700629 A CN103700629 A CN 103700629A CN 201310745581 A CN201310745581 A CN 201310745581A CN 103700629 A CN103700629 A CN 103700629A
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CN103700629B (zh
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李延钊
王刚
陈海晶
沈武林
方金钢
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BOE Technology Group Co Ltd
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Abstract

本发明提供一种阵列基板及其制备方法、显示装置，属于显示装置制造技术领域，本发明的阵列基板的制备方法，包括：在基底上通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管的有源区的图形；在完成上述步骤的基底上形成栅极绝缘层；在完成上述步骤的基底上，通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管栅极的图形；在完成上述步骤的基底上形成隔离层；在完成上述步骤的基底上，形成用于第一薄膜晶体管、第二薄膜晶体管的源漏极与其各自有源区电连接的第二接触过孔，以及用于第一薄膜晶体管的栅极与第二薄膜晶管的源极电连接的第一接触过孔。

Description

一种阵列基板及其制备方法、显示装置
技术领域
本发明属于显示装置制备技术领域，具体涉及一种阵列基板及其制备方法、显示装置。
背景技术
在AMOLED阵列基板制备工艺中，氧化物半导体铟镓锌氧化物（InGaZnO4；IGZO）因其迁移率高、均匀性好以及可在室温下制备，被用作薄膜晶体管有源层的材料，通常该薄膜晶体管结构为底栅型结构。
如图1所示，是最基本的2T1C的像素结构，其包括：2个薄膜晶体管（即，第一薄膜晶体管M1和第二薄膜晶体管M2），以及1个存储电容C1，第一薄膜晶体管M1的栅极与第二薄膜晶体管M2的源极连接。
如图2、3所示，在制作2T1C结构的AMOLED阵列基板时，第一薄膜晶体管M1与第二薄膜晶体管M2的源漏极106金属和其各自有源区103通过第二接触过孔105连接，第二薄膜晶体管（驱动管）M2的栅极102和第一薄膜晶体管（开关管）M1的源极106通过第一接触过孔104连接；通过调整第二薄膜晶体管M2的栅极电压（即第一薄膜晶体管M1的源极电压）即可控制流过第二薄膜晶体管M2的电流大小，进而控制每个像素单元对应的有机发光层的发光量。但是，在上述AMOLED器件的制作过程中，技术人员发现AMOLED背板（阵列基板）上经常出现漏电现象，严重影响产品的良品率，而且该问题一直无法得到解决。
发明内容
本发明所要解决的技术问题包括，针对现有的阵列基板存在的上述不足，提供一种防止薄膜晶体管漏电的阵列基板的制备方法、阵列基板以及显示装置。
解决本发明技术问题所采用的技术方案是一种阵列基板的制备方法，包括如下步骤：
在基底上通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管的有源区的图形；
在完成上述步骤的基底上形成栅极绝缘层；
在完成上述步骤的基底上，通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管栅极的图形；
在完成上述步骤的基底上形成隔离层；
在完成上述步骤的基底上，形成用于第一薄膜晶体管、第二薄膜晶体管的源漏极与其各自有源区电连接的第二接触过孔，以及用于第二薄膜晶体管的栅极与第一薄膜晶管的源极电连接的第一接触过孔。
本发明的阵列基板的制备方法中，先形成有源区，再形成栅极，故栅极位于有源区上方，这样在形成第二接触过孔时以栅极金属为刻蚀的承载体，栅极金属对刻蚀的承受能力大于有源区材料对刻蚀的承受能力，故其可以防止与第一接触过孔同时形成时由于刻蚀时间相对较长，造成设于第二接触过孔下方栅极金属被刻蚀穿，造成阵列基板漏电。
优选的是，在基底上通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管的有源区的图形的步骤之前，还包括：
在基底上形成缓冲层。
进一步优选的是，所述缓冲层的材料为氧化硅或氮化硅，其厚度在5～500nm之间。
优选的是，形成第一接触过孔和第二接触过孔的步骤之后，还包括：
通过构图工艺在第一薄膜晶体管和第二薄膜晶体管的有源区上方的接触过孔上形成相应的源、漏极的图形，同时在第二薄膜晶体管的栅极的接触过孔上方，形成用于连接第二薄膜晶体管的栅极和第一薄膜晶体管的源极的连接线。
进一步优选的是，所有所述薄膜晶体管的源极、漏极以及连接线的材料均采用钼、铜、铝中任意一种，且厚度均在1～500nm之间。
优选的是，所有所述薄膜晶体管的有源区的材料为氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡、非晶硅、多晶硅中任意一种，其厚度在5～200nm之间。
优选的是，所有所述薄膜晶体管的栅极材料为钼、铜、铝中任意一种。
解决本发明技术问题所采用的技术方案是一种阵列基板，其是由上述任意一种制备方法制备的。
优选的是，所述阵列基板为OLED阵列基板，所述第一薄膜晶体管为开关管，所述第二薄膜晶体管为驱动管。
解决本发明技术问题所采用的技术方案是一种显示装置，其包括上述阵列基板。
附图说明
图1为现有的2T1C像素结构的电路示意图；
图2为现有阵列基板的一个侧面的结构示意图；
图3为现有阵列基板的另一个侧面的结构示意图；
图4为本发明的实施例1提供的阵列基板的制备方法制备的阵列基板的一个侧面的结构图；
图5为本发明的实施例1提供的阵列基板的制备方法制备的阵列基板的另一个侧面的结构图；以及，
图6为本发明的实施例1的阵列基板的制备方法的流程图。
其中附图标记为：101、基底；102、栅极；103、有源区；104、第一接触过孔；105、第二接触过孔；106、源极/漏极；107、缓冲层；108、栅极绝缘层；109、连接线；110、平坦化层；111、钝化层；第一薄膜晶体管M1；第二薄膜晶体管M2。
具体实施方式
在采用底栅型TFT的AMOLED显示装置中，以采用2T1C为例，在同一个像素单元中，第一薄膜晶体管M1作为开关管，第二薄膜晶体管M2作为驱动管，开关管的源极与驱动管的栅极需通过接触过孔进行电连接。针对现有AMOLED显示装置中AMOLED背板（阵列基板）出现漏电的问题，本发明的发明人发现：
在第一接触过孔104和第二接触过孔105的制备过程中，往往采用同一步曝光显影（Mask-Photo）工艺在光刻胶上制备出两接触过孔的图形，再通过同一道干刻工艺刻蚀制备出两接触过孔。但是在刻蚀过程中，由于第一接触过孔104所需的刻蚀深度远大于第二接触过孔105的刻蚀深度，因而相对于第二接触过孔105而言，整体的刻蚀时间过长；第二接触过孔105处的长时间干法过刻，造成此处的有源区103的材料和设于有源区103与栅极102间的栅极绝缘层被击穿断裂，导致后续工艺所沉积的源漏极106与底部的栅极102相连，从而造成背板的严重漏电，以致背板最终报废，良品率降低。
当然，也可以采用将第一接触过孔104和第二接触过孔105通过两次单独的构图工艺形成，但是该方式工艺复杂、生产效率低。
为了解决上述问题，本发明提供一种阵列基板及其制备方法、显示装置。为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
结合图4、5、6所示，本实施例提供一种阵列基板的制备方法，具体包括如下步骤：
步骤一、采用溅射的方法在基底101上沉积形成缓冲层107，该缓冲层107材料可以为氧化硅、氮化硅或者为有机绝缘材料，其厚度优选在5～500nm之间。
步骤二、在形成有缓冲层107的基底上，通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管有源区103的图形，其具体可以采用磁控溅射的方法沉积缓冲层107薄膜，之后在空气氛围下300℃退火1h，并进而光刻、刻蚀出所需的有源区103的图形，有源层的材料可以选择氧化铟镓锌（IGZO）、氧化铟锌（IZO）、氧化铟锡（ITO）、氧化铟镓锡（InGaSnO）、非晶硅、多晶硅等中任意一种，当然也可以为其他半导体材料，其厚度优选在5～200nm之间。
步骤三、在形成有第一薄膜晶体管和第二薄膜晶体管有源区103的基底上，形成栅极绝缘层108，该栅极绝缘层108覆盖薄膜晶体管有源区103，优选栅极绝缘层108的材料为Mo、Au、Cr等金属材料或者合金材料及其他复合导电材料，或者为氧化硅、氮化硅，以及有机绝缘材料等绝缘材料均可，其厚度优选在1～300nm之间。
步骤四、在形成栅极绝缘层108的基底上，通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管栅极102的图形，栅极102的材料可以为钼（Mo）、铜(Cu)、铝(Al)中任意一种，当然也可以为金属材料、合金材料以及复合导电材料均可，其厚度优选在1～300nm之间。
步骤五、在形成第一薄膜晶体管和第二薄膜晶体管栅极102的基底上，形成平坦化层110（电学绝缘），平坦化层110的材料可以为氧化硅或氮化硅，当然也可以是其他绝缘材料，其厚度优选在5～500nm之间。
步骤六、通过一次构图工艺形成用于第一薄膜晶体管、第二薄膜晶体管的源、漏极106与其各自有源层103电连接的第二接触过孔105，以及用于第二薄膜晶体管的栅极102与第一薄膜晶管的源极106电连接的第一接触过孔104。
步骤七、通过构图工艺在第一薄膜晶体管和第二薄膜晶体管的有源区103上方的接触过孔上形成相应的源、漏极106的图形，同时在第二薄膜晶体管的栅极102的接触过孔上方，形成用于连接第二薄膜晶体管的栅极102和第一薄膜晶体管的源极106连接的金属连接线109。其中，两个薄膜晶体管的源漏极106以及连接线109的材料均采用钼（Mo）、铜(Cu)、铝(Al)中任意一种，当然也可以为金属材料、合金材料以及复合导电材料均可，其厚度均为1～500nm之间。
其中，由于第一接触过孔104的深度小于第二接触过孔105的深度，相对而言第一接触过孔104的刻蚀时间过长，但是第一接触过孔104刻蚀的承载体为栅极102，栅极102采用的金属材料厚度相对较厚，其可承受刻蚀的能力远高于有源区103的材料的可承受刻蚀的能力，所以在同时形成第一接触过孔104和第二接触过孔105时，就可以避免在相同的刻蚀时间下造成栅极102以及栅极下方的栅极绝缘层108被刻穿，从而导致栅极102与有源层甚至源、漏极106导通，进而造成阵列基板漏电的情况，同时可以大大提高了产品的良品率。
步骤八、在完成上述步骤的基底101上形成钝化层111，钝化层111的材料可以为氧化硅或氮化硅，其厚度为5～500nm之间。最终得到如图4、5所示的阵列基板结构。
上述步骤制备薄膜晶体管为顶栅型薄膜晶体管，在形成第一接触过孔104可第二接触过孔105时，采用栅极102金属作为长时间刻蚀的承载体，所制备的阵列基板的抗漏电性能大大提高了。
当然本实施例只是对阵列基板上中两个薄膜晶体管的制备进行了具体描述，该阵列基板的像素结构可以为2T1C型，同样也适用于6T2C的像素电路、时序控制电路、扫描驱动电路、数据驱动电路、背板测试电路、静电防止电路、以及TFT背板的其他功能电路中薄膜晶体管的制备方法，其制备原理与上述方法相同，在此就不一一阐述了，只要是采用上述方法制备的薄膜晶体管的第一接触过孔104和第二接触过孔105的阵列基板均在本发明的保护范围里。
在本实施例中，薄膜晶体管的源极和漏极在结构上是一样的，因此源极和漏极在功能上也可以互换。在实施例1的描述中，是以漏极作为信号输入端，源极作为信号输出端；但本发明的保护范围不限于此，以源极作为TFT的信号输入端，漏极作为信号输出端的方案也属于本发明的保护范围。
实施例2：
如图3所示，本实施例提供一种阵列基板，其包括第一薄膜晶体管和第二薄膜晶体管，且第二薄膜晶体管的栅极102与第一薄膜晶管源极106通过第一接触过孔104连接，所述阵列基板是由实施例1所述的制备方法制备的。
优选地，该阵列基板为OLED阵列基板，第一薄膜晶体管为开关管，第二薄膜晶体管为驱动管，开关管的源极106与驱动管的栅极102连接。
当然，在阵列基板中还应具有数据线、扫描线等其他的已知结构，在此不再详细描述。
由于本实施例的阵列基板具有实施例1的方法制备的，故其制作的阵列基板的良品率得到大大提高。
在本实施例中，也可以将TFT的源极作为TFT的信号输入端，漏极作为信号输出端；这样，开关管的源极将与数据线相连，用来接入图像数据信号，而开关管的漏极则与驱动管的栅极连接，用以控制通过驱动管的电流大小。
实施例3：
本实施例提供一种显示装置，其包括实施例2所述的阵列基板，该显示装置可以为：OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置中具有实施例1中的阵列基板，故其具的良品率大大提高。
当然，本实施例的显示装置中还可以包括其他常规结构，如电源单元、显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种阵列基板的制备方法，其特征在于，包括如下步骤：
在基底上通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管的有源区的图形；
在完成上述步骤的基底上形成栅极绝缘层；
在完成上述步骤的基底上，通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管栅极的图形；
在完成上述步骤的基底上形成隔离层；
在完成上述步骤的基底上，形成用于第一薄膜晶体管、第二薄膜晶体管的源漏极与其各自有源区电连接的第二接触过孔，以及用于第一薄膜晶体管的栅极与第二薄膜晶管的源极电连接的第一接触过孔。
2.根据权利要求1所述的阵列基板的制备方法，其特征在于，在基底上通过构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管的有源区的图形的步骤之前，还包括：
在基底上形成缓冲层。
3.根据权利要求2所述的阵列基板的制备方法，其特征在于，所述缓冲层的材料为氧化硅或氮化硅，其厚度在5～500nm之间。
4.根据权利要求1所述的阵列基板的制备方法，其特征在于，形成第一接触过孔和第二接触过孔的步骤之后，还包括：
通过构图工艺在第一薄膜晶体管和第二薄膜晶体管的有源区上方的第二接触过孔上形成相应的源、漏极的图形，同时在第二薄膜晶体管的栅极的第一接触过孔上方，形成用于连接第二薄膜晶体管的栅极和第一薄膜晶体管的源极的连接线。
5.根据权利要求4所述的阵列基板的制备方法，其特征在于，所有所述薄膜晶体管的源极、漏极以及连接线的材料均采用钼、铜、铝中任意一种，且厚度均在1～500nm之间。
6.根据权利要求1所述的阵列基板的制备方法，其特征在于，所有所述薄膜晶体管的有源区的材料为氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡、非晶硅、多晶硅中任意一种，其厚度在5～200nm之间。
7.根据权利要求1所述的阵列基板的制备方法，其特征在于，所有所述薄膜晶体管的栅极材料为钼、铜、铝中任意一种。
8.一种阵列基板，其特征在于，其是由权利要求1～7中任意一项所述的阵列基板的制备方法制备的。
9.根据权利要求8所述的阵列基板，其特征在于，所述阵列基板为OLED阵列基板，所述第一薄膜晶体管为开关管，所述第二薄膜晶体管为驱动管。
10.一种显示装置，其特征在于，包括权利要求8或9所述的阵列基板。
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