CN203983289U - 薄膜晶体管、阵列基板及显示装置 - Google Patents

薄膜晶体管、阵列基板及显示装置 Download PDF

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CN203983289U
CN203983289U CN201420323542.8U CN201420323542U CN203983289U CN 203983289 U CN203983289 U CN 203983289U CN 201420323542 U CN201420323542 U CN 201420323542U CN 203983289 U CN203983289 U CN 203983289U
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film transistor
thin
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active layer
drain electrode
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程鸿飞
乔勇
先建波
李文波
李盼
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BOE Technology Group Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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Abstract

本实用新型提供一种薄膜晶体管、阵列基板及显示装置,属于显示技术领域,其可以提高现有的薄膜晶体管的导电性能。本实用新型的薄膜晶体管,包括有源层、源极、漏极,所述有源层包括分别用于连接源极和漏极的源极接触区和漏极接接触区,以及设于所述源极接触区和漏极接触区之间的半导体沟道区,其中,在所述有源层的半导体沟道区上设置有金属导电层,所述金属导电层与所述源极和所述漏极间隔设置。

Description

薄膜晶体管、阵列基板及显示装置
技术领域
本实用新型属于显示技术领域,具体涉及一种薄膜晶体管、阵列基板及显示装置。
背景技术
显示技术广泛应用于电视、手机以及公共信息显示,目前液晶显示面板和有机电致发光显示面板(OLED)使用最为广泛。
液晶面板和OLED面板均包括阵列基板以及形成在阵列基板上的显示单元。其中,阵列基板包括多个薄膜晶体管,在液晶像素电路中,薄膜晶体管起到开关的作用。而在OLED的驱动中,薄膜晶体管既有开关作用也有驱动作用,发明人发现现有技术中薄膜晶体管作为驱动晶体管时,其驱动能力的大小是与薄膜晶体管有源层的导电能力正相关的,但是有源层的材料为半导体材料,故其导电能力相对导体材料而言较弱,所以如何增强有源层的导电能力显然很重要。
实用新型内容
本实用新型所要解决的技术问题包括,针对现有的薄膜晶体管的有源层导电能力较弱的问题,提供一种导电能力提高的薄膜晶体管、阵列基板及显示装置。
解决本实用新型技术问题所采用的技术方案是一种薄膜晶体管,其包括形成在基底上的栅极、有源层、源极、漏极,所述有源层包括分别用于连接源极和漏极的源极接触区和漏极接接触区,以及设于所述源极接触区和漏极接触区之间的半导体沟道区,其中,在所述有源层的半导体沟道区上设置有金属导电层,所述金属导电层与所述源极和所述漏极间隔设置。
由于本实用新型的薄膜晶体管的有源层的半导体沟道区上设置有金属导电层,故当给栅极加电时,该金属导电层在靠近栅极的一侧上将感应出与栅极电荷极性相反的电荷,因而在栅极与金属导电层之间将形成电场,从而增强有源层中的电场,加强半导体沟道区的导电能力,进而使得薄膜晶体管的导电性能更好。
优选的是,所述薄膜晶体管有源层的材料为非晶硅、多晶硅、微晶硅、氧化物半导体中的任意一种。
进一步优选的是,所述有源层材料为非晶硅、多晶硅、微晶硅中的任意一种,所述薄膜晶体管有源层包括:半导体层和设于半导体层上的欧姆接触层,所述欧姆接触层与所述源极、所述漏极、所述金属导电层接触且与所述源极、所述漏极、所述金属导电层图案相同。
优选的是,所述源极、所述漏极、所述金属导电层同层设置,且材料相同。
进一步优选的是,所述源极、所述漏极、所述金属导电层的材料为钼、钼铌合金、铝、铝钕合金、钛、铜中的任意一种。
优选的是,所述有源层的半导体沟道区为长方形或U型结构。
优选的是,所述金属导电层包括一个金属岛,或者包括多个同层且间隔设置的金属岛。
优选的是,所述薄膜晶体管还包括栅极,所述栅极设于所述有源层下方并通过栅极绝缘层隔开。
优选的是,所述薄膜晶体管还包括栅极,所述栅极设于所述有源层上方并通过栅极绝缘层隔开。
解决本实用新型技术问题所采用的技术方案是一种阵列基板,其包括上述薄膜晶体管。
由于本实用新型的阵列基板包括上述薄膜晶体管,故其性能更好。
解决本实用新型技术问题所采用的技术方案是一种显示装置,其包括上述阵列基板,故其性能更好。
附图说明
图1为本实用新型的实施例1、2的薄膜晶体管和阵列基板的一种结构示意图;
图2为图1的A1-A2的剖面图;
图3为本实用新型的实施例1、2的薄膜晶体管和阵列基板的另一种结构示意图;
图4为本实用新型的实施例1、2的薄膜晶体管和阵列基板的再一种结构示意图;
图5为图4的B1-B2的剖面图;
图6为本实用新型的实施例1、2的薄膜晶体管和阵列基板的又一种结构示意图。
其中附图标记为:1、基底;10、栅线;20、数据线;30、钝化层;11、栅极;12、栅极绝缘层;13、有源层;131、半导体层;132、欧姆接触层;21、源极;22、漏极;25、金属导电层;251、252、金属岛;31、过孔;32、像素电极。
具体实施方式
为使本领域技术人员更好地理解本实用新型的技术方案,下面结合附图和具体实施方式对本实用新型作进一步详细描述。
实施例1:
结合图1至6所示,本实施例提供一种薄膜晶体管,其包括形成在基底1上的栅极11、有源层13、源极21、漏极22,所述有源层13包括分别用于连接源极21和漏极22的源极21接触区和漏极22接接触区,以及设于所述源极21接触区和漏极22接触区之间的半导体沟道区,其中,在所述有源层13的半导体沟道区上设置有金属导电层25,所述金属导电层25与所述源极21和所述漏极22间隔设置。
由于本实施例的薄膜晶体管的有源层13的半导体沟道区上设置有金属导电层25,故当给栅极11加电时,该金属导电层25在靠近栅极11的一侧上将感应出与栅极11电荷极性相反的电荷,因而在栅极11与金属导电层25之间将形成电场,从而增强有源层13中的电场,加强半导体沟道区的导电能力,进而使得薄膜晶体管的导电性能更好。
优选地,薄膜晶体管有源层13的材料为非晶硅、多晶硅、微晶硅、氧化物半导体中的任意一种。
如图3所示,进一步优选地,该薄膜晶体管有源层13的材料为非晶硅、多晶硅、微晶硅中的任意一种,所述薄膜晶体管有源层13包括:半导体层131和设于半导体层131上的欧姆接触层(n+a-si)132,所述欧姆接触层132与所述源极21、所述漏极22、所述金属导电层25接触且与所述源极21、所述漏极22、所述金属导电层25图案相同。在本实施例中,欧姆接触层132有助于半导体层131与源极21和漏极22更好的接触,同时由于欧姆接触层132与所述源极21、所述漏极22、所述金属导电层25接触且与所述源极21、所述漏极22、所述金属导电层25图案相同,故欧姆接触层132与源极21、漏极22、金属导电层25可以通过一次构图工艺形成,因而不增加额外的工艺步骤。
优选地,本实施例中薄膜晶体管的源极21、漏极22、金属导电层25同层设置,且材料相同,故不增加薄膜晶体管的制备工艺步骤和成本。当然源极21和漏极22与金属导电层25分别制备也是可以的。
进一步优选地,本实施例中薄膜晶体管的源极21、漏极22、金属导电层25的材料可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成的。
优选地,本实施例的薄膜晶体管的有源层13的半导体沟道区为长方形或U型结构。具体的如图1和6所示,半导体沟道区为U型结构;如图4所示,半导体沟道区为长方形。需要说明的是,半导体沟道区的图案不局限于U型结构和长方形结构,其他形状也是可行的。
优选地,本实施例中金属导电层25包括一个金属岛(如图1至5所示),或者包括多个同层且间隔设置的金属岛(如图6所示)。具体的,如图4、5所示,有源层13的半导体沟道区上设置有金属岛,该金属岛位于薄膜晶体管的源极21和漏极22之间。其中,金属岛靠近源极21的侧边与源极21顶端边缘平行;金属岛靠近漏极22的侧边与漏极22顶端边缘平行。如图6所示,薄膜晶体管具有U型有源层13的半导体沟道区,有源层13的半导体沟道区上设置有金属导电层25,该金属导电层25包括金属岛251和金属岛252,金属岛251位于漏极22顶端与源极21底端之间,用于加强漏极22顶端与源极21底端之间半导体沟道区的导电能力;金属岛252位于有源层13的左上角,且位于漏极22和源极21之间,以加强有源层13左上角的半导体沟道区的导电能力。本实用新型实施例不对金属岛25的个数进行限定,本实用新型实施例也不对金属岛25的形状进行限定,金属岛25的个数和形状可以根据需要设置。
优选地,本实施例的薄膜晶体管可以为顶栅型薄膜晶体管也可以是底栅型薄膜晶体管。当该薄膜晶体管为顶栅型薄膜晶体管时,栅极11设于所述有源层13上方并通过栅极绝缘层12隔开;当该薄膜晶体管为底栅型薄膜晶体管时,栅极11设于所述有源层13下方并通过栅极绝缘层12隔开。其中,栅极11的材料可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层,优选为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。栅极绝缘层12的材料为:为硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)等中的一种或它们中多种材料组成的多层复合膜。当有源层13的材料为氧化物半导体时,其材料包含In(铟)、Ga(镓)、Zn(锌)、O(氧)、Sn(锡)等元素的薄膜通过溅射形成,其中薄膜中必须包含氧元素和其他两种或两种以上的元素,如氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化铟锡(InSnO)、氧化铟镓锡(InGaSnO)等。
实施例2:
结合图1至6所示,在本实施例提供一种阵列基板,其包括上述的薄膜晶体管,薄膜晶体管上方设置有钝化层30,当然还包括像素电极32,数据线20、栅线10等其他结构。其中,像素电极32通过贯穿薄膜晶体管上方钝化层30的过孔31与薄膜晶体管的漏极22连接,数据线20与源极21连接,栅线10与栅极11连接。
由于本实施例的阵列基板包括上述薄膜晶体管,故其性能更好。
实施例3:
本实施例提供一种显示装置,其包括上述阵列基板,该显示装置可以为:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置中具有实施例2中的阵列基板,故其性能更好。
当然,本实施例的显示装置中还可以包括其他常规结构,如电源单元、显示驱动单元等。
可以理解的是,以上实施方式仅仅是为了说明本实用新型的原理而采用的示例性实施方式,然而本实用新型并不局限于此。对于本领域内的普通技术人员而言,在不脱离本实用新型的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本实用新型的保护范围。

Claims (11)

1.一种薄膜晶体管,包括有源层、源极、漏极,所述有源层包括分别用于连接源极和漏极的源极接触区和漏极接接触区,以及设于所述源极接触区和漏极接触区之间的半导体沟道区,其特征在于,在所述有源层的半导体沟道区上设置有金属导电层,所述金属导电层与所述源极和所述漏极间隔设置。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述薄膜晶体管有源层的材料为非晶硅、多晶硅、微晶硅、氧化物半导体中的任意一种。
3.根据权利要求2所述的薄膜晶体管,其特征在于,所述有源层材料为非晶硅、多晶硅、微晶硅中的任意一种,所述薄膜晶体管有源层包括:半导体层和设于半导体层上的欧姆接触层,所述欧姆接触层与所述源极、所述漏极、所述金属导电层接触且与所述源极、所述漏极、所述金属导电层图案相同。
4.根据权利要求1至3中任意一项所述的薄膜晶体管,其特征在于,所述源极、所述漏极、所述金属导电层同层设置,且材料相同。
5.根据权利要求4所述的薄膜晶体管,其特征在于,所述源极、所述漏极、所述金属导电层的材料为钼、钼铌合金、铝、铝钕合金、钛、铜中的任意一种。
6.根据权利要求1至3中任意一项所述的薄膜晶体管,其特征在于,所述有源层的半导体沟道区为长方形或U型结构。
7.根据权利要求1至3中任意一项所述的薄膜晶体管,其特征在于,所述金属导电层包括一个金属岛,或者包括多个同层且间隔设置的金属岛。
8.根据权利要求1至3中任意一项所述的薄膜晶体管,其特征在于,所述薄膜晶体管还包括栅极,所述栅极设于所述有源层下方并通过栅极绝缘层隔开。
9.根据权利要求1至3中任意一项所述的薄膜晶体管,其特征在于,所述薄膜晶体管还包括栅极,所述栅极设于所述有源层上方并通过栅极绝缘层隔开。
10.一种阵列基板,其特征在于,包括权利要求1至9中任意一项所述的薄膜晶体管。
11.一种显示装置,其特征在于,包括权利要求10所述的阵列基板。
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