CN102945807B - 一种薄膜晶体管的制备方法及薄膜晶体管 - Google Patents

一种薄膜晶体管的制备方法及薄膜晶体管 Download PDF

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CN102945807B
CN102945807B CN201210460335.2A CN201210460335A CN102945807B CN 102945807 B CN102945807 B CN 102945807B CN 201210460335 A CN201210460335 A CN 201210460335A CN 102945807 B CN102945807 B CN 102945807B
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CN102945807A (zh
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何宗泽
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Abstract

本发明提供一种薄膜晶体管的制备方法及薄膜晶体管，涉及液晶显示领域。其中薄膜晶体管包括：一衬底基板；形成在所述衬底基板上的立体结构的栅电极；覆盖所述栅电极的栅绝缘层；形成在所述栅绝缘层上的半导体层；形成在所述半导体层上的缓冲层；形成在所述缓冲层上的源漏电极，所述薄膜晶体管形成的沟道为立体结构。本发明的方案可以降低驱动电压减少驱动电路功耗，减少TFT占用面积增加通光率。

Description

一种薄膜晶体管的制备方法及薄膜晶体管
技术领域
本发明涉及液晶显示领域，特别是一种薄膜晶体管的制备方法及薄膜晶体管。
背景技术
在显示领域中，高PPI（Pixelsperinch，每英寸所拥有的像素）值的平板显示器是各家竞争的焦点。然而如果面板在具有较高的PPI值时，会给面板时带来一系列诸如功耗，通光率等问题。由此在TFT(ThinFilmTransistor薄膜晶体管)阵列基板不透光面积减小的条件下增大沟道宽度以增加饱和电流保证一定的充电率就成为了技术难题。
现有技术中的TFT阵列基板，其导电沟道和栅电极层为薄膜的平面结构，无法充分合理的利用空间体积来提升饱和电流。
发明内容
本发明要解决的技术问题是提供一种薄膜晶体管的制备方法及薄膜晶体管，可以在一定程度上降低驱动电压减少驱动电路功耗，减少薄膜晶体管（TFT）占用面积增加通光率。
为解决上述技术问题，本发明的实施例提供一种薄膜晶体管的制备方法，包括：
提供一衬底基板；
在所述衬底基板上形成立体结构的栅电极；
在形成有所述栅电极的衬底基板上形成覆盖所述栅电极的栅绝缘层；
在形成有所述栅绝缘层的衬底基板上形成半导体层；
形成有所述半导体层的衬底基板上形成缓冲层；
在形成有所述缓冲层的衬底基板上形成金属层，通过构图工艺对所述金属层进行处理，形成源漏电极，所述薄膜晶体管形成的沟道为立体结构。
其中，所述立体结构为长方体。
其中，在所述衬底基板上形成立体结构的栅电极的步骤包括：
在所述衬底基板上，沉积第一金属层；
通过构图工艺，对所述第一金属层进行处理，形成立体结构的栅电极。
其中，在形成有所述栅电极的衬底基板上形成覆盖所述栅电极的栅绝缘层的步骤包括：
在形成有所述长方体结构的栅电极的衬底基板上，沉积一层绝缘材料；
通过构图工艺，对所述绝缘材料进行处理，在所述栅电极的顶面以及两个侧面上形成栅绝缘层。
其中，在形成有所述栅绝缘层的衬底基板上形成半导体层的步骤包括：
在形成有所述栅绝缘层的衬底基板上，沉积一层半导体材料；
通过构图工艺，对所述半导体材料进行处理，在所述栅绝缘层上形成半导体层。
其中，形成有所述半导体层的衬底基板上形成缓冲层的步骤包括：
在形成有所述半导体层的衬底基板上，沉积一层N+非晶硅材料；
通过构图工艺，对所述N+非晶硅材料进行处理，在所述半导体层上形成缓冲层。
其中，在形成有所述缓冲层的衬底基板上形成金属层，通过构图工艺对所述金属层进行处理，形成源漏电极的步骤包括：
在形成有所述缓冲层的衬底基板上，沉积第二金属层；
通过构图工艺，对所述第二金属层进行处理，在所述缓冲层上形成源漏电极。
本发明的实施例还提供一种薄膜晶体管，包括，
一衬底基板；
形成在所述衬底基板上的立体结构的栅电极；
覆盖所述栅电极的栅绝缘层；
形成在所述栅绝缘层上的半导体层；
形成在所述半导体层上的缓冲层；
形成在所述缓冲层上的源漏电极，所述薄膜晶体管形成的沟道为立体结构。
其中，所述立体结构为长方体形。
其中，所述薄膜晶体管的沟道至少包括三电子门。
本发明的上述技术方案的有益效果如下：
上述方案中，通过使用三维立体结构的薄膜晶体管（TFT）结构，使得相应电子门的数量增加，即在相同的栅电压，薄膜晶体管占用面积相同的情况下，饱和电流比传统的平面薄膜晶体管要大，这样可以在一定程度上降低驱动电压减少驱动电路功耗，减少薄膜晶体管占用面积增加通光率。
附图说明
图1为本发明的薄膜晶体管的结构示意图；
图2-图10为本发明的薄膜晶体管的制备方法的过程示意图。
具体实施方式
实施例1
如图2-图10所示，提供一种薄膜晶体管的制备方法，包括：
步骤1，提供一衬底基板11；
步骤2，在所述衬底基板11上形成立体结构的栅电极；
步骤3，在形成有所述栅电极的衬底基板上形成覆盖所述栅电极的栅绝缘层；
步骤4，在形成有所述栅绝缘层的衬底基板上形成半导体层；
步骤5，形成有所述半导体层的衬底基板上形成缓冲层；
步骤6，在形成有所述缓冲层的衬底基板上形成金属层，通过构图工艺对所述金属层进行处理，形成源漏电极，所述薄膜晶体管形成的沟道为立体结构。
本发明的该方法实施例通过在所述衬底基板上形成立体结构的薄膜晶体管结构，使得相应电子门的数量增加，即在相同的栅电压，薄膜晶体管占用面积相同的情况下，饱和电流比传统的平面薄膜晶体管要大，这样可以在一定程度上降低驱动电压减少驱动电路功耗，减少薄膜晶体管占用面积增加通光率。
如图2和图3所示，上述实施例中的步骤2包括：
步骤21，在所述衬底基板上沉积第一金属层1’；
步骤22，通过构图工艺，对所述第一金属层1’进行处理，形成立体结构的栅电极1，其中，该立体结构为长方体形。
其中，所述第一金属层1’采用的材料可以包括：氧化铟锡ITO，或者Cr、Mo、AL、Nd、Mo、W、Ti、Ta和Cu材料中的一种或者其中至少两种金属的合金；
现有技术中栅电极为薄膜结构，其厚度非常小，而本发明中的栅电极1为立体结构，其厚度大于一层薄膜的厚度，优选的，该栅电极1为长方体形。由此可见，在长方体的栅电极1基础上进一步设置其他结构，可以使整个薄膜晶体管具有长方体形的结构；需要指出的是，长方体只作为薄膜晶体管立体结构中的一种优选方式，以便于生产和加工；本发明的实施例还可以包括：如正方体形或者其它立体结构的薄膜晶体管结构，只要能相比于一层薄膜的平面结构而言，在相同的栅电压，薄膜晶体管占用面积相同的情况下，饱和电流比传统的平面薄膜晶体管大的结构均可。
如图4和图5所示，上述步骤3包括：
步骤31，在形成有所述长方体结构的栅电极1的衬底基板11上，沉积一层绝缘材料2’（如图4所示）；
步骤32，通过构图工艺，对所述绝缘材料2’进行处理，在所述栅电极1的顶面以及两个侧面上形成栅绝缘层2（如图5所示）；其中，所述栅绝缘层2采用的材料包括：氧化物、氮化物或者氮氧化物，如SiNx。
如图6和图7所示，上述步骤4包括：
步骤41，在形成有所述栅绝缘层2的衬底基板上11，沉积一层导电材料3’（如图6所示）；
步骤42，通过构图工艺，对所述导电材料3’进行处理，在所述栅绝缘层2上形成半导体层3（如图7所示）；其中，所述半导体层3采用的材料包括：非晶硅，如a-si。
如图8和图9所示，上述步骤5包括：
步骤51，在形成有所述半导体层3的衬底基板上11，沉积一层N+非晶硅材料4’（如图8所示）；
步骤52，通过构图工艺，对所述N+非晶硅材料4’（如N+a-si）进行处理，在所述半层体层上形成缓冲层4（如图9所示）；其中，该缓冲层4可以是掺杂半导体层，也可以不是掺杂半导体层。
如图10所示，上述步骤6包括：
步骤61，在形成有所述缓冲层4的衬底基板上11，沉积第二金属层；
步骤62，通过构图工艺，对所述第二金属层进行处理，最终在所述缓冲层4上形成源漏电极5（如图10所示）；其中，所述第二金属层为Cr、Mo、AL、Nd、Mo、W、Ti、Ta和Cu材料中的一种或者其中至少两种金属的合金。
其中，图1为通过以上步骤最终形成的立体结构的薄膜晶体管结构的立体示意图。
由图7所示，本发明的实施例中，半导体层3的有效导电沟道宽度为：W=W1+W2+W3，相比于现有技术中平面结构的导电沟道（宽度应该是如W2），很明显，W大于W2，因此，本发明的该立体结构的薄膜晶体管结构，使得有效导电沟道宽度大大增加，使得相应电子门的数量增加，至少包括3个电子门，即在相同的栅电压，±膜i占用面积相同的情况下，饱和电流比传统的平面薄膜晶体管要大，这样可以在一定程度上降低驱动电压减少驱动电路功耗，减少薄膜晶体管占用面积增加通光率。
根据饱和电流公式可知，随着沟道宽度的增大，饱和电流也随之增大，其中W为沟道宽度，VGS为栅电极1相对于半导体层3的电压，VTH为感应出载子所需最小电压，K为玻尔兹曼常数，L为有效沟道长度，这样可以在一定程度上降低驱动电压减少驱动电路功耗，减少薄膜晶体管占用面积增加通光率。
实施例2
如图1－图10所示，本发明的实施例还提供一种薄膜晶体管，包括：一衬底基板；形成在所述衬底基板上的立体结构的栅电极1；覆盖所述栅电极的栅绝缘层2；形成在所述栅绝缘层2上的半导体层3；形成在所述半导体层3上的缓冲层4；形成在所述缓冲层4上的源漏电极5，所述薄膜晶体管形成的沟道为立体结构，其中，所述立体结构为长方体形，如图1中半导体3所示结构。其中，所述薄膜晶体管的沟道至少包括三电子门。
由此可见，在长方体形的栅电极1基础上进一步设置其他结构，可以使整个薄膜晶体管据有长方体形的结构；需要指出的是，长方体形的只作为薄膜晶体管立体结构中的一种优选方式，以便于生产和加工；本发明的实施例还可以包括：如正方体形或者其它立体结构的薄膜晶体管结构，只要能相比于一层薄膜的平面结构而言，在相同的栅电压，薄膜晶体管占用面积相同的情况下，饱和电流比传统的平面薄膜晶体管大的结构均可。
本实施例的薄膜晶体管采用立体结构，可以增加相应电子门的数量，即在相同的栅电压，薄膜晶体管用面积相同的情况下，饱和电流比传统的平面薄膜晶体管要大，根据饱和电流公式可知，随着沟道宽度的增大，饱和电流也随之增大，其中W为沟道宽度，VGs为栅电极1相对于半导体层3的电压，VTH为感应出载子所需最小电压，K为玻尔兹曼常数，L为有效沟道长度，这样可以在一定程度上降低驱动电压减少驱动电路功耗，减少薄膜晶体管占用面积增加通光率。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

1.一种薄膜晶体管的制备方法，所述薄膜晶体管应用于具有阵列基板的液晶显示装置，所述薄膜晶体管形成于所述阵列基板上，其特征在于，所述方法包括：
提供一衬底基板；
在所述衬底基板上形成立体结构的栅电极；
在形成有所述栅电极的衬底基板上形成覆盖所述栅电极的栅绝缘层；
在形成有所述栅绝缘层的衬底基板上形成半导体层；
形成有所述半导体层的衬底基板上形成缓冲层；
在形成有所述缓冲层的衬底基板上形成金属层，通过构图工艺对所述金属层进行处理，形成源漏电极，所述薄膜晶体管形成的沟道为立体结构。
2.根据权利要求1所述的方法，其特征在于，所述立体结构为长方体。
3.根据权利要求2所述的方法，其特征在于，在所述衬底基板上形成立体结构的栅电极的步骤包括：
在所述衬底基板上，沉积第一金属层；
通过构图工艺，对所述第一金属层进行处理，形成立体结构的栅电极。
4.根据权利要求2所述的方法，其特征在于，在形成有所述栅电极的衬底基板上形成覆盖所述栅电极的栅绝缘层的步骤包括：
在形成有所述长方体结构的栅电极的衬底基板上，沉积一层绝缘材料；
通过构图工艺，对所述绝缘材料进行处理，在所述栅电极的顶面以及两个侧面上形成栅绝缘层。
5.根据权利要求2所述的方法，其特征在于，在形成有所述栅绝缘层的衬底基板上形成半导体层的步骤包括：
在形成有所述栅绝缘层的衬底基板上，沉积一层半导体材料；
通过构图工艺，对所述半导体材料进行处理，在所述栅绝缘层上形成半导体层。
6.根据权利要求2所述的方法，其特征在于，形成有所述半导体层的衬底基板上形成缓冲层的步骤包括：
在形成有所述半导体层的衬底基板上，沉积一层N+非晶硅材料；
通过构图工艺，对所述N+非晶硅材料进行处理，在所述半导体层上形成缓冲层。
7.根据权利要求2所述的方法，其特征在于，在形成有所述缓冲层的衬底基板上形成金属层，通过构图工艺对所述金属层进行处理，形成源漏电极的步骤包括：
在形成有所述缓冲层的衬底基板上，沉积第二金属层；
通过构图工艺，对所述第二金属层进行处理，在所述缓冲层上形成源漏电极。
8.一种薄膜晶体管，应用于具有阵列基板的液晶显示装置，所述薄膜晶体管形成于所述阵列基板上，其特征在于，所述薄膜晶体管包括：
一衬底基板；
形成在所述衬底基板上的立体结构的栅电极；
覆盖所述栅电极的栅绝缘层；
形成在所述栅绝缘层上的半导体层；
形成在所述半导体层上的缓冲层；
形成在所述缓冲层上的源漏电极，所述薄膜晶体管形成的沟道为立体结构。
9.根据权利要求8所述的薄膜晶体管，其特征在于，所述立体结构为长方体形。
10.根据权利要求9所述的薄膜晶体管，其特征在于，所述薄膜晶体管的沟道至少包括三电子门。
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