CN202487578U - 薄膜晶体管、阵列基板及显示装置 - Google Patents
薄膜晶体管、阵列基板及显示装置 Download PDFInfo
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Abstract
本实用新型公开了一种薄膜晶体管,涉及显示技术领域,包括:依次层叠的栅极、栅绝缘层、有源层及源/漏极,源极和漏极之间形成有沟道,所述栅极具有至少一个栅极突出部,所述至少一个栅极突出部位于所述沟道两侧的开口的一侧,且不与有源层及源/漏极接触;所述栅绝缘层覆盖所述栅极和所述至少一个栅极突出部。还公开了一种包括上述薄膜晶体管的阵列基板及包括所述阵列基板的显示装置。本实用新型的薄膜晶体管中,栅绝缘层和栅极向沟道方向延伸包裹沟道两侧的开口(或其中一侧),因此,提高了TFT的开启电流Ion,降低了开启电压和负载,提升了开口率。
Description
技术领域
本实用新型涉及显示技术领域,特别涉及一种薄膜晶体管、阵列基板及显示装置。
背景技术
现有的薄膜晶体管TFT如图1和2所示,包括在基板上由下至上依次层叠的栅极100、栅绝缘层200、有源层300及源/漏极400,源极和漏极之间形成有沟道,TFT的栅极100与阵列基板上的栅线500连接,TFT的源极与阵列基板上的数据线600连接。如图2所示,现有的TFT的栅极100位于沟道底部,只从底部影响沟道,TFT导通后只形成一个漏电流沟道。因此,现有的TFT的开启电流Ion较低,开口率低,且开启电压和负载较高。
实用新型内容
(一)要解决的技术问题
本实用新型要解决的技术问题是:如何提升薄膜晶体管的开启电流。
(二)技术方案
为解决上述技术问题,本实用新型提供了一种薄膜晶体管,包括:依次层叠的栅极、栅绝缘层、有源层及源/漏极,源极和漏极之间形成有沟道,所述栅极具有至少一个栅极突出部,所述至少一个栅极突出部位于所述沟道两侧的开口的一侧,且不与有源层及源/漏极接触,所述栅绝缘层覆盖所述栅极和至少一个栅极突出部。
其中,所述栅极具有两个栅极突出部:第一栅极突出部和第二栅极突出部,所述第一栅极突出部位于所述沟道两侧的开口的一侧,所述第二栅极突出部位于所述沟道两侧的开口的另一侧,且所述第一栅极突出部和第二栅极突出部均不与有源层及源/漏极接触,所述栅绝缘层覆盖所述栅极和两个栅极突出部。
其中,所述栅极突出部的长度大于或等于所述沟道的长度。
其中,所述栅极突出部的高度大于或等于所述栅绝缘层、有源层及源/漏极的厚度之和。
本实用新型还提供了一种阵列基板,所述阵列基板包括上述的薄膜晶体管。
本实用新型还提供了一种显示装置,所述显示装置包括上述的阵列基板。
(三)有益效果
本实用新型的薄膜晶体管TFT中,栅绝缘层和栅极向沟道方向延伸包裹沟道两侧的开口(或其中一侧),相当于形成多个漏电流沟道,因此,提高了TFT的开启电流Ion。
附图说明
图1是现有技术的一种薄膜晶体管结构示意图;
图2是沿图1中A-A向的剖视图;
图3是本实用新型实施例1的一种薄膜晶体管结构示意图;
图4是沿图3中A-A向的剖视图;
图5是本实用新型实施例2的一种薄膜晶体管结构示意图;
图6是沿图5中A-A向的剖视图。
具体实施方式
下面结合附图和实施例,对本实用新型的具体实施方式作进一步详细描述。以下实施例用于说明本实用新型,但不用来限制本实用新型的范围。
实施例1
如图3和图4所示,本实施例的薄膜晶体管包括:包括在基板上由下至上依次层叠的栅极100、栅绝缘层200、有源层300及源/漏极400,源极和漏极之间形成有沟道,TFT的栅极100与阵列基板上的栅线500连接,TFT的源极与阵列基板上的数据线600连接。栅极100具有一个向上的栅极突出部101。栅极突出部101位于沟道的两侧开口(沟道沿A-A向的两个开口)的一侧,且栅极突出部101不与有源层300和源/漏极400接触。栅绝缘层200覆盖整个栅极100和栅极突出部101,如图4所示,由于栅极突出部101的存在,栅绝缘层200也形成了一个绝缘突出部201,绝缘突出部201介于栅极突出部101与有源层300及源/漏极400之间,隔离了栅极100和有源层300及源/漏极400,并覆盖栅极突出部101。
其中,栅极100和栅极突出部101分两次沉积等工艺制作,先做栅极100再在栅极100上制作栅极突出部101,这两者可以采用同种金属材料也可以采用不同的金属材料。制作完栅极突出部101再制作栅绝缘层200、有源层300及源/漏极400。
由图4可看出,栅极100从沟道的底部和一侧包裹沟道,从两个方向对沟道产生影响,相当于形成了两个漏电流沟道,从而提高了TFT的开启电流Ion。在TFT大小相同的情况下,本实施例的TFT的Ion更大。而面板开启所需要的Ion是一致的,也就是说在本实施例的TFT可以做的更小,由此减小了部分面板上的电容。在相同功耗的前提下,电容减低,可以适当提高栅线的电阻,保持功耗一致,也就是总的电容电阻衰减一致。提高电阻是通过减宽栅线的方式,栅线变窄,开口率提升。而且TFT的缩小本身也可以在某些形态的象素结构下提升开口率,比如横向TFT,或大尺寸产品的象素结构。同时,TFT减小了以后,栅极与源极之间的电容也随之减小,电容减小,其他对应的电路结构也可适当改变,提升开口率。由于TFT沟道在两个方向被包围,载流子活性在相同电压下也会更高。需要的开启电压也更低。可以解决低温开启不良等问题。
优选地,如图3所示,栅极突出部101的长度L等于或大于沟道的长度L′。如图4所示,栅极突出部101的高度H大于或等于栅绝缘层200、有源层300及源/漏极400的厚度之和,以将沟道一侧的开口完全包围,从而进一步地提高TFT的开启电流Ion。
实施例2
如图5和图6所示,本实施例的薄膜晶体管包括:包括在基板上由下至上依次层叠的栅极100、栅绝缘层200、有源层300及源/漏极400,源极和漏极之间形成有沟道,TFT的栅极100与阵列基板上的栅线500连接,TFT的源极与阵列基板上的数据线600连接。栅极100具有两个向上的栅极突出部101a和101b。栅极突出部101a位于沟道两侧的开口的一侧,栅极突出部101b位于沟道两侧的开口的另一侧,且栅极突出部101a和栅极突出部101b均不与有源层300及源/漏极400接触。栅绝缘层200覆盖整个栅极100和栅极突出部101a和101b。如图6所示,由于栅极突出部101a和101b的存在,栅绝缘层200也形成了两个绝缘突出部201a和201b,绝缘突出部201a介于栅极突出部101a与有源层300及源/漏极400之间,并覆盖栅极突出部101a。绝缘突出部201b介于栅极突出部101b与有源层300及源/漏极400之间,并覆盖栅极突出部101b。绝缘突出部201a和201b隔离了栅极100和有源层300及源/漏极400。
由图6可看出,栅极100、栅极突出部101a和栅极突出部101b从三个方向包围了沟道。即从沟道的底部和两侧包裹沟道,从三个方向对沟道产生影响,相当于形成了三个漏电流沟道,从而提高了TFT的开启电流Ion。在TFT大小相同的情况下,本实施例的TFT的Ion更大。而面板开启所需要的Ion是一致的,也就是说在本实施例的TFT可以做的更小,与现有的TFT相比,TFT更小,TFT的宽长比降低,TFT负载降低,可以进一步缩小栅极线宽,从而提升开口率。同时,TFT减小了以后,栅极与源极之间的电容也随之减小,电容减小,其他对应的电路结构也可适当改变,提升开口率。由于TFT沟道在三个方向被包围,载流子活性在相同电压下也会更高。需要的开启电压也更低。可以解决低温开启不良等问题。
优选地,如图5所示,栅极突出部101a和101b的长度L等于或大于沟道的长度L′。如图6所示,栅极突出部101a和101b的高度H大于或等于栅绝缘层200、有源层300及源/漏极400的厚度之和,以将沟道一侧的开口完全包围,从而进一步地提高TFT的开启电流Ion。
由于本实施例相对与实施例1对沟道的包围从两面增加到三面,因此相对于实施例1在提高TFT的开启电流Ion等效果上会更好。
上述实施例1和2是以底栅型的TFT为例进行说明的,对于顶栅型的TFT,栅极在顶部,因此栅极突出部向下延伸包围源/漏极之间形成的沟道或位于沟道两侧的开口的一侧,栅极突出部的结构与实施例1及实施例2中栅极突出部的结构类似,此处不再赘述。
实施例3
本实施例还提供了一种阵列基板,该阵列基板中的TFT为实施例1或实施例2所述的TFT。
实施例4
本实施例还提供了一种显示装置,该显示装置中的阵列基板为实施例3所述的阵列基板。
以上实施方式仅用于说明本实用新型,而并非对本实用新型的限制,有关技术领域的普通技术人员,在不脱离本实用新型的精神和范围的情况下,还可以做出各种变化和变型,因此所有等同的技术方案也属于本实用新型的范畴,本实用新型的专利保护范围应由权利要求限定。
Claims (6)
1.一种薄膜晶体管,包括:依次层叠的栅极、栅绝缘层、有源层及源/漏极,源极和漏极之间形成有沟道,其特征在于,所述栅极具有至少一个栅极突出部,所述至少一个栅极突出部位于所述沟道两侧的开口的一侧,且不与有源层及源/漏极接触;所述栅绝缘层覆盖所述栅极和所述至少一个栅极突出部。
2.如权利要求1所述的薄膜晶体管,其特征在于,所述栅极具有两个栅极突出部:第一栅极突出部和第二栅极突出部,所述第一栅极突出部位于所述沟道两侧的开口的一侧,所述第二栅极突出部位于所述沟道两侧的开口的另一侧,且所述第一栅极突出部和第二栅极突出部均不与有源层及源/漏极接触,所述栅绝缘层覆盖所述栅极和两个栅极突出部。
3.如权利要求1或2所述的薄膜晶体管,其特征在于,所述栅极突出部的长度大于或等于所述沟道的长度。
4.如权利要求1或2所述的薄膜晶体管,其特征在于,所述栅极突出部的高度大于或等于所述栅绝缘层、有源层及源/漏极的厚度之和。
5.一种阵列基板,其特征在于,所述阵列基板包括如权利要求1~4中任一项所述的薄膜晶体管。
6.一种显示装置,其特征在于,所述显示装置包括如权利要求5所述的阵列基板。
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Application Number | Priority Date | Filing Date | Title |
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CN201220120967XU CN202487578U (zh) | 2012-03-27 | 2012-03-27 | 薄膜晶体管、阵列基板及显示装置 |
PCT/CN2013/071935 WO2013143370A1 (zh) | 2012-03-27 | 2013-02-27 | 薄膜晶体管、阵列基板及显示装置 |
US13/982,122 US9123813B2 (en) | 2012-03-27 | 2013-02-27 | Thin film transistor, array substrate and display device |
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CN201220120967XU CN202487578U (zh) | 2012-03-27 | 2012-03-27 | 薄膜晶体管、阵列基板及显示装置 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102945807A (zh) * | 2012-11-15 | 2013-02-27 | 京东方科技集团股份有限公司 | 一种薄膜晶体管的制备方法及薄膜晶体管 |
CN102955314A (zh) * | 2012-10-18 | 2013-03-06 | 京东方科技集团股份有限公司 | 一种薄膜晶体管tft阵列基板、其制备方法及显示装置 |
WO2013143370A1 (zh) * | 2012-03-27 | 2013-10-03 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板及显示装置 |
WO2017080004A1 (zh) * | 2015-11-10 | 2017-05-18 | 深圳市华星光电技术有限公司 | 液晶显示面板及液晶显示装置 |
WO2017201822A1 (zh) * | 2016-05-27 | 2017-11-30 | 深圳市华星光电技术有限公司 | 一种显示装置、阵列基板及其制造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN106684125B (zh) * | 2015-11-05 | 2020-05-08 | 群创光电股份有限公司 | 显示设备 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5473168A (en) | 1993-04-30 | 1995-12-05 | Sharp Kabushiki Kaisha | Thin film transistor |
KR20040043116A (ko) * | 2001-04-10 | 2004-05-22 | 사르노프 코포레이션 | 유기 박막 트랜지스터를 이용한 고성능 액티브 매트릭스화소 제공방법 및 제공장치 |
JP5532803B2 (ja) * | 2009-09-30 | 2014-06-25 | ソニー株式会社 | 半導体デバイスおよび表示装置 |
CN201845776U (zh) * | 2010-10-15 | 2011-05-25 | 京东方科技集团股份有限公司 | 阵列基板和液晶显示面板 |
CN202487578U (zh) * | 2012-03-27 | 2012-10-10 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板及显示装置 |
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- 2012-03-27 CN CN201220120967XU patent/CN202487578U/zh not_active Expired - Lifetime
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- 2013-02-27 US US13/982,122 patent/US9123813B2/en active Active
- 2013-02-27 WO PCT/CN2013/071935 patent/WO2013143370A1/zh active Application Filing
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2013143370A1 (zh) * | 2012-03-27 | 2013-10-03 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板及显示装置 |
US9123813B2 (en) | 2012-03-27 | 2015-09-01 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate and display device |
CN102955314A (zh) * | 2012-10-18 | 2013-03-06 | 京东方科技集团股份有限公司 | 一种薄膜晶体管tft阵列基板、其制备方法及显示装置 |
CN102945807A (zh) * | 2012-11-15 | 2013-02-27 | 京东方科技集团股份有限公司 | 一种薄膜晶体管的制备方法及薄膜晶体管 |
CN102945807B (zh) * | 2012-11-15 | 2015-11-25 | 京东方科技集团股份有限公司 | 一种薄膜晶体管的制备方法及薄膜晶体管 |
US9620606B2 (en) | 2012-11-15 | 2017-04-11 | Boe Technology Group Co., Ltd. | Method for manufacturing thin film transistor, and thin film transistor thereof |
WO2017080004A1 (zh) * | 2015-11-10 | 2017-05-18 | 深圳市华星光电技术有限公司 | 液晶显示面板及液晶显示装置 |
WO2017201822A1 (zh) * | 2016-05-27 | 2017-11-30 | 深圳市华星光电技术有限公司 | 一种显示装置、阵列基板及其制造方法 |
Also Published As
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US20140077298A1 (en) | 2014-03-20 |
US9123813B2 (en) | 2015-09-01 |
WO2013143370A1 (zh) | 2013-10-03 |
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