CN104167448A - 薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

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CN104167448A
CN104167448A CN201410381242.XA CN201410381242A CN104167448A CN 104167448 A CN104167448 A CN 104167448A CN 201410381242 A CN201410381242 A CN 201410381242A CN 104167448 A CN104167448 A CN 104167448A
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thin
film transistor
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CN104167448B (zh
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姜春生
辛龙宝
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BOE Technology Group Co Ltd
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Abstract

本发明提供一种薄膜晶体管及其制备方法、阵列基板和显示装置。该薄膜晶体管的制备方法包括在衬底基板上形成栅极、栅绝缘层、有源区、源极和漏极，有源区采用ZnON材料形成，在形成有源区的同时对有源区进行氮离子注入，以使薄膜晶体管的亚阈值摆幅≤0.5mV/dec。该制备方法通过在形成有源区的同时对有源区进行氮离子注入，使有源区中处于有效导电位置的氮离子浓度大大提高，由此使得薄膜晶体管工作时，有源区因为扩散效应而损失的氮元素能够得到足够的补充，从而大大提高了有源区中氮空位的迁移率，也即大大提高了有源区中载流子的迁移率，进而降低了薄膜晶体管的亚阈值摆幅，提升了薄膜晶体管的半导体特性。

Description

薄膜晶体管及其制备方法、阵列基板和显示装置
技术领域
本发明涉及显示技术领域，具体地，涉及一种薄膜晶体管及其制备方法、阵列基板和显示装置。
背景技术
薄膜晶体管(TFT)由于其良好的开关特性，目前已广泛应用于平板显示装置。
通常，薄膜晶体管包括栅极、有源区、源极和漏极，源极和漏极分设于有源区的两端且分别与有源区接触。当栅极电压高于其阈值电压时，源极和漏极通过有源区导通，载流子从源极流向漏极或者从漏极流向源极。
薄膜晶体管的有源区目前可以采用ZnON(锌氮氧化物)材料，ZnON材料在导电的过程中，其中的氮空位具有较高的迁移率，能够大大提高薄膜晶体管的导电性能，另外，由于ZnON材料相对于IGZO(铟镓锌氧化物)材料价格低廉，所以有源区采用ZnON材料能够大大降低薄膜晶体管的制备成本。
但是，形成有源区的ZnON材料中氮元素含量不同会导致不同的迁移率，而且在薄膜晶体管的导通过程中以及在显示装置的显示基板(如阵列基板)的ITO(铟锡氧化物)退火过程中，有源区会因为扩散效应导致其中的氮元素移动到相邻的栅绝缘层或钝化层中，从而降低了有源区中氮空位的迁移率，进而导致薄膜晶体管的亚阈值摆幅增大，亚阈值摆幅的增大会严重影响薄膜晶体管的半导体特性。
发明内容
本发明针对现有技术中存在的上述技术问题，提供一种薄膜晶体管及其制备方法、阵列基板和显示装置。该制备方法通过在形成有源区的同时对有源区进行氮离子注入，使有源区中处于有效导电位置的氮离子浓度大大提高，由此使得薄膜晶体管工作时，有源区因为扩散效应而损失的氮元素能够得到足够的补充，从而大大提高了有源区中氮空位的迁移率，也即大大提高了有源区中载流子的迁移率，进而降低了薄膜晶体管的亚阈值摆幅，提升了薄膜晶体管的半导体特性。
本发明提供一种薄膜晶体管的制备方法，包括在衬底基板上形成栅极、栅绝缘层、有源区、源极和漏极，所述有源区采用ZnON材料形成，在形成所述有源区的同时对所述有源区进行氮离子注入，以使所述薄膜晶体管的亚阈值摆幅≤0.5mV/dec。
优选地，形成所述有源区包括先后形成第一有源区层和第二有源区层，所述在形成所述有源区的同时对所述有源区进行氮离子注入具体包括：
步骤S1：采用ZnON材料沉积形成所述第一有源区层；
步骤S2：对所述第一有源区层进行氮离子注入，注入剂量为1011-1012个/cm2的氮离子；
步骤S3：采用ZnON材料沉积形成所述第二有源区层。
优选地，所述第一有源区层的厚度范围为所述第二有源区层的厚度范围为
优选地，在形成所述有源区之后、并在形成所述源极和所述漏极之前，还包括形成刻蚀阻挡层，在所述刻蚀阻挡层中并对应所述有源区的两端形成第一过孔和第二过孔，所述源极通过所述第一过孔与所述有源区连接，所述漏极通过所述第二过孔与所述有源区连接。
优选地，所述有源区形成于所述栅极上方，或者，所述栅极形成于所述有源区上方。
本发明还提供一种薄膜晶体管，所述薄膜晶体管采用上述制备方法制成。
优选地，所述薄膜晶体管的有源区包括第一有源区层和第二有源区层，所述第二有源区层位于所述第一有源区层上，且所述第一有源区层中处于有效导电位置的氮离子的浓度大于所述第二有源区层中处于有效导电位置的氮离子的浓度。
优选地，还包括刻蚀阻挡层，所述刻蚀阻挡层位于所述有源区与所述源极和所述漏极之间，所述刻蚀阻挡层中在对应所述有源区两端的区域开设有第一过孔和第二过孔，所述源极通过所述第一过孔与所述有源区连接，所述漏极通过所述第二过孔与所述有源区连接。
本发明还提供一种阵列基板，包括上述薄膜晶体管。
本发明还提供一种显示装置，包括上述阵列基板。
本发明的有益效果：本发明所提供的薄膜晶体管的制备方法，通过在形成有源区的同时对有源区进行氮离子注入，使有源区中处于有效导电位置的氮离子浓度大大提高，由此使得薄膜晶体管工作时，有源区因为扩散效应而损失的氮元素能够得到足够的补充，从而大大提高了有源区中氮空位的迁移率，也即大大提高了有源区中载流子的迁移率，进而降低了薄膜晶体管的亚阈值摆幅，提升了薄膜晶体管的半导体特性。
本发明所提供的薄膜晶体管，通过采用上述制备方法，亚阈值摆幅大大降低，半导体特性也得到了极大提升。本发明所提供的阵列基板，通过采用上述薄膜晶体管，使该阵列基板的性能得到了进一步提升。本发明所提供的显示装置，通过采用上述阵列基板，进一步提升了该显示装置的性能。
附图说明
图1为本发明实施例1中形成栅极和栅绝缘层的步骤；
图2为本发明实施例1中形成第一有源区层的步骤；
图3为本发明实施例1中对第一有源区层进行氮离子注入的步骤；
图4为本发明实施例1中形成第二有源区层的步骤；
图5为本发明实施例1中形成刻蚀阻挡层、第一过孔和第二过孔的步骤；
图6为本发明实施例1中形成源极和漏极的步骤。
其中的附图标记说明：
1.衬底基板；2.栅极；3.栅绝缘层；4.有源区；41.第一有源区层；42.第二有源区层；5.源极；6.漏极；7.刻蚀阻挡层；8.第一过孔；9.第二过孔。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种薄膜晶体管及其制备方法、阵列基板和显示装置作进一步详细描述。
实施例1：
本实施例提供一种薄膜晶体管的制备方法，如图1-6所示，包括在衬底基板1上形成栅极2、栅绝缘层3、有源区4、源极5和漏极6，有源区4采用ZnON材料形成，在形成有源区4的同时对有源区4进行氮离子注入，以使薄膜晶体管的亚阈值摆幅≤0.5mV/dec。
其中，亚阈值摆幅为半导体输出特性曲线中从关态(截止状态)到开态(导通状态)的这部分曲线的斜率，该斜率越小，表示薄膜晶体管从关态到开态的响应速度越快，相应地，亚阈值摆幅特性越好，薄膜晶体管的性能也越好；该斜率越大，表示薄膜晶体管从关态到开态的响应速度越慢，相应地，亚阈值摆幅特性较差，薄膜晶体管的性能也较差。
本实施例中，有源区4形成于栅极2上方，且栅极2、栅绝缘层3、有源区4、源极5和漏极6依次形成在衬底基板1上。即本实施例中的薄膜晶体管为底栅型结构。栅极2、栅绝缘层3、源极5和漏极6采用传统的构图工艺形成，这里不再详述。
本实施例中，形成有源区4包括先后形成第一有源区层41和第二有源区层42，在形成有源区4的同时对有源区4进行氮离子注入具体包括：
步骤S1：采用ZnON材料沉积形成第一有源区层41(如图2)。
步骤S2：对第一有源区层41进行氮离子注入，注入剂量为1011-1012个/cm2的氮离子(如图3)。
该氮离子注入剂量能使有源区4中的处于有效导电位置的氮离子浓度增加，处于有效导电位置的氮离子浓度的增加能够进一步提高有源区4中氮空位的迁移率，也即进一步提高了有源区4中载流子的迁移率，从而降低了薄膜晶体管的亚阈值摆幅，进而提升了薄膜晶体管的半导体特性。
步骤S3：采用ZnON材料沉积形成第二有源区层42(如图4)。
第二有源区层42作为有源区4的导电层，当薄膜晶体管处于工作状态时，作为导电层的第二有源区层42会因为扩散效应导致其中的氮离子移动到相邻的栅绝缘层或钝化层中，从而降低第二有源区层42中氮空位的迁移率。第一有源区层41中处于有效导电位置的氮离子浓度高于第二有源区层42，当薄膜晶体管处于工作状态(包括线性状态和饱和状态)时，第一有源区层41中的氮离子会补充到第二有源区层42中，并在第二有源区层42中处于有效导电位置，处于有效导电位置的氮离子浓度的增加会进一步提高第二有源区层42中氮空位的迁移率，也即进一步提高了有源区4中载流子的迁移率，从而降低了薄膜晶体管的亚阈值摆幅，进而提升了薄膜晶体管的半导体特性。
需要说明的是，有效导电位置指ZnON材料的有源区4中有效空位的位置，当薄膜晶体管通电时，在栅极电场的作用下，处于有效空位位置的氮元素能够快速驱离该有效空位的位置，使有效空位的位置被让出来，从而使有源区4能够快速实现半空位导电。这使得薄膜晶体管在通电的情况下能够实现快速导通(即快速地从关态发展到开态)，不仅降低了薄膜晶体管的亚阈值摆幅，同时还提升了薄膜晶体管的半导体特性。
其中，第一有源区层41的厚度范围为第二有源区层42的厚度范围为如此设置，使第一有源区层41能够通过氮离子注入存储一定量的氮离子，同时还使第二有源区层42在导电过程中通过处于有效导电位置的氮离子浓度的增加，提高了氮空位的迁移率，也即进一步提高了有源区4中载流子的迁移率，从而降低了薄膜晶体管的亚阈值摆幅，进而提升了薄膜晶体管的半导体特性。
本实施例中，在形成有源区4之后、并在形成源极5和漏极6(如图6)之前，还包括形成刻蚀阻挡层7，在所述刻蚀阻挡层7中并对应有源区4的两端形成第一过孔8和第二过孔9(如图5)，源极5通过第一过孔8与有源区4连接，漏极6通过第二过孔9与有源区4连接。刻蚀阻挡层7能够在刻蚀形成源极5和漏极6时保护有源区4免受刻蚀损坏。
需要说明的是，在有源区4与源极5和漏极6之间也可以不形成刻蚀阻挡层，只要确保在刻蚀形成源极5和漏极6时不要对有源区4造成刻蚀损坏即可。
实施例2：
本实施例提供一种薄膜晶体管的制备方法，与实施例1不同的是，栅极形成于有源区上方，即本实施例中的薄膜晶体管为顶栅型结构。
本实施例中薄膜晶体管的其他结构的制备方法与实施例1中相同，此处不再赘述。
实施例1-2的有益效果：实施例1-2中所提供的薄膜晶体管的制备方法，通过在形成有源区的同时对有源区进行氮离子注入，使有源区中处于有效导电位置的氮离子浓度大大提高，由此使得薄膜晶体管处于工作状态时，有源区因为扩散效应而损失的氮元素能够得到足够的补充，从而大大提高了有源区中氮空位的迁移率，也即大大提高了有源区中载流子的迁移率，进而降低了薄膜晶体管的亚阈值摆幅，提升了薄膜晶体管的半导体特性。
实施例3：
本实施例提供一种薄膜晶体管，该薄膜晶体管采用实施例1-2任意一个中的制备方法制成。
本实施例中，薄膜晶体管的有源区包括第一有源区层和第二有源区层，第二有源区层位于第一有源区层上，且第一有源区层中处于有效导电位置的氮离子浓度大于第二有源区层中处于有效导电位置的氮离子浓度。如此设置，能使薄膜晶体管在工作过程中，第一有源区层中的氮离子能够补充到第二有源区层中，并在第二有源区层中处于有效导电位置，从而提高了整个有源区中氮空位的迁移率，也即进一步提高了有源区中载流子的迁移率，从而降低了薄膜晶体管的亚阈值摆幅，进而提升了薄膜晶体管的半导体特性。
本实施例中，薄膜晶体管还包括刻蚀阻挡层，刻蚀阻挡层位于有源区与源极和漏极之间，刻蚀阻挡层中在对应有源区两端的区域开设有第一过孔和第二过孔，源极通过第一过孔与有源区连接，漏极通过第二过孔与有源区连接。刻蚀阻挡层能够在刻蚀形成源极和漏极时保护有源区免受刻蚀损坏。
通过采用实施例1-2任意一个中的制备方法制成的薄膜晶体管，亚阈值摆幅大大降低，半导体特性也得到了极大提升。
实施例4：
本实施例提供一种阵列基板，包括实施例3中的薄膜晶体管。
通过采用实施例3中的薄膜晶体管，使该阵列基板的性能得到了进一步提升。
实施例5：
本实施例提供一种显示装置，包括实施例4中的阵列基板。
通过采用实施例4中的阵列基板，进一步提升了该显示装置的性能。
本发明所提供的显示装置可以为，液晶面板、液晶电视、显示器、OLED面板、OLED电视、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种薄膜晶体管的制备方法，包括在衬底基板上形成栅极、栅绝缘层、有源区、源极和漏极，所述有源区采用ZnON材料形成，其特征在于，在形成所述有源区的同时对所述有源区进行氮离子注入，以使所述薄膜晶体管的亚阈值摆幅≤0.5mV/dec。
2.根据权利要求1所述的制备方法，其特征在于，形成所述有源区包括先后形成第一有源区层和第二有源区层，所述在形成所述有源区的同时对所述有源区进行氮离子注入具体包括：
步骤S1：采用ZnON材料沉积形成所述第一有源区层；
步骤S2：对所述第一有源区层进行氮离子注入，注入剂量为1011-1012个/cm2的氮离子；
步骤S3：采用ZnON材料沉积形成所述第二有源区层。
3.根据权利要求2所述的制备方法，其特征在于，所述第一有源区层的厚度范围为所述第二有源区层的厚度范围为
4.根据权利要求1所述的制备方法，其特征在于，在形成所述有源区之后、并在形成所述源极和所述漏极之前，还包括形成刻蚀阻挡层，在所述刻蚀阻挡层中并对应所述有源区的两端形成第一过孔和第二过孔，所述源极通过所述第一过孔与所述有源区连接，所述漏极通过所述第二过孔与所述有源区连接。
5.根据权利要求1所述的制备方法，其特征在于，所述有源区形成于所述栅极上方，或者，所述栅极形成于所述有源区上方。
6.一种薄膜晶体管，其特征在于，所述薄膜晶体管采用权利要求1-5任意一项所述的制备方法制成。
7.根据权利要求6所述的薄膜晶体管，其特征在于，所述薄膜晶体管的有源区包括第一有源区层和第二有源区层，所述第二有源区层位于所述第一有源区层上，且所述第一有源区层中处于有效导电位置的氮离子的浓度大于所述第二有源区层中处于有效导电位置的氮离子的浓度。
8.根据权利要求6所述的薄膜晶体管，其特征在于，还包括刻蚀阻挡层，所述刻蚀阻挡层位于所述有源区与所述源极和所述漏极之间，所述刻蚀阻挡层中在对应所述有源区两端的区域开设有第一过孔和第二过孔，所述源极通过所述第一过孔与所述有源区连接，所述漏极通过所述第二过孔与所述有源区连接。
9.一种阵列基板，其特征在于，包括权利要求6-8任意一项所述的薄膜晶体管。
10.一种显示装置，其特征在于，包括权利要求9所述的阵列基板。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107004721A (zh) * 2014-12-16 2017-08-01 乐金显示有限公司 薄膜晶体管阵列基板
CN107516661A (zh) * 2017-07-28 2017-12-26 上海天马有机发光显示技术有限公司 显示基板、显示装置及显示基板的制作方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104167449B (zh) * 2014-08-05 2017-09-22 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
US20160225915A1 (en) * 2015-01-30 2016-08-04 Cindy X. Qiu Metal oxynitride transistor devices
WO2022188011A1 (zh) * 2021-03-08 2022-09-15 京东方科技集团股份有限公司 一种显示基板的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581092A (en) * 1993-09-07 1996-12-03 Semiconductor Energy Laboratory Co., Ltd. Gate insulated semiconductor device
JP2007311453A (ja) * 2006-05-17 2007-11-29 Nec Lcd Technologies Ltd 薄膜トランジスタ及びその製造方法
CN103855194A (zh) * 2012-11-30 2014-06-11 三星电子株式会社 半导体材料、包括其的晶体管和包括晶体管的电子装置
CN103872138A (zh) * 2012-12-10 2014-06-18 三星电子株式会社 晶体管、制造晶体管的方法和包括该晶体管的电子器件

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4609797B2 (ja) * 2006-08-09 2011-01-12 Ｎｅｃ液晶テクノロジー株式会社 薄膜デバイス及びその製造方法
KR100851215B1 (ko) * 2007-03-14 2008-08-07 삼성에스디아이 주식회사 박막 트랜지스터 및 이를 이용한 유기 전계 발광표시장치
KR100982395B1 (ko) * 2007-04-25 2010-09-14 주식회사 엘지화학 박막 트랜지스터 및 이의 제조방법
JP5241143B2 (ja) * 2007-05-30 2013-07-17 キヤノン株式会社 電界効果型トランジスタ
US20080303037A1 (en) * 2007-06-04 2008-12-11 Irving Lyn M Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
KR101496148B1 (ko) * 2008-05-15 2015-02-27 삼성전자주식회사 반도체소자 및 그 제조방법
US8258511B2 (en) * 2008-07-02 2012-09-04 Applied Materials, Inc. Thin film transistors using multiple active channel layers
JP5430113B2 (ja) * 2008-10-08 2014-02-26 キヤノン株式会社 電界効果型トランジスタ及びその製造方法
US8013339B2 (en) * 2009-06-01 2011-09-06 Ishiang Shih Thin film transistors and arrays with controllable threshold voltages and off state leakage current
US7988470B2 (en) * 2009-09-24 2011-08-02 Applied Materials, Inc. Methods of fabricating metal oxide or metal oxynitride TFTs using wet process for source-drain metal etch
US8642380B2 (en) * 2010-07-02 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
TWI555205B (zh) * 2010-11-05 2016-10-21 半導體能源研究所股份有限公司 半導體裝置及半導體裝置的製造方法
TWI654764B (zh) * 2010-11-11 2019-03-21 日商半導體能源研究所股份有限公司 半導體裝置及其製造方法
US8629496B2 (en) * 2010-11-30 2014-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5993141B2 (ja) * 2010-12-28 2016-09-14 株式会社半導体エネルギー研究所 記憶装置
WO2012090973A1 (en) * 2010-12-28 2012-07-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8669552B2 (en) * 2011-03-02 2014-03-11 Applied Materials, Inc. Offset electrode TFT structure
KR101900525B1 (ko) * 2011-03-18 2018-09-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 산화물 반도체막, 반도체 장치, 및 반도체 장치의 제작 방법
JP6104522B2 (ja) * 2011-06-10 2017-03-29 株式会社半導体エネルギー研究所 半導体装置
KR101878731B1 (ko) * 2011-12-06 2018-07-17 삼성전자주식회사 트랜지스터와 그 제조방법 및 트랜지스터를 포함하는 전자소자
TW201901972A (zh) * 2012-01-26 2019-01-01 日商半導體能源研究所股份有限公司 半導體裝置及半導體裝置的製造方法
US9349849B2 (en) * 2012-03-28 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device including the semiconductor device
US8860023B2 (en) * 2012-05-01 2014-10-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101975929B1 (ko) * 2012-06-29 2019-05-09 삼성전자주식회사 질산화물 채널층을 구비한 트랜지스터 및 그 제조방법
KR20140009023A (ko) * 2012-07-13 2014-01-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP6080141B2 (ja) * 2012-09-18 2017-02-15 エルジー・ケム・リミテッド 透明導電膜、透明導電膜の製造方法、電子素子、及び薄膜トランジスタ
KR102147849B1 (ko) * 2013-08-05 2020-08-25 삼성전자주식회사 박막 트랜지스터 및 그 제조방법
KR20150025621A (ko) * 2013-08-29 2015-03-11 삼성전자주식회사 트랜지스터와 그 제조방법 및 트랜지스터를 포함하는 전자소자

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581092A (en) * 1993-09-07 1996-12-03 Semiconductor Energy Laboratory Co., Ltd. Gate insulated semiconductor device
JP2007311453A (ja) * 2006-05-17 2007-11-29 Nec Lcd Technologies Ltd 薄膜トランジスタ及びその製造方法
CN103855194A (zh) * 2012-11-30 2014-06-11 三星电子株式会社 半导体材料、包括其的晶体管和包括晶体管的电子装置
CN103872138A (zh) * 2012-12-10 2014-06-18 三星电子株式会社 晶体管、制造晶体管的方法和包括该晶体管的电子器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EUNHA LEE,ET AL: "Nanocrystalline ZnON:High mobility and low band gap semiconductor material for high performance switch transistor and image sensor application", 《SCIENTIFIC REPOSTS》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107004721A (zh) * 2014-12-16 2017-08-01 乐金显示有限公司 薄膜晶体管阵列基板
US10692975B2 (en) 2014-12-16 2020-06-23 Lg Display Co., Ltd. Thin-film transistor array substrate
CN107004721B (zh) * 2014-12-16 2020-10-20 乐金显示有限公司 薄膜晶体管阵列基板
CN107516661A (zh) * 2017-07-28 2017-12-26 上海天马有机发光显示技术有限公司 显示基板、显示装置及显示基板的制作方法

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