CN106558592B - 阵列基板、显示装置及阵列基板的制备方法 - Google Patents

阵列基板、显示装置及阵列基板的制备方法 Download PDF

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CN106558592B
CN106558592B CN201610360433.7A CN201610360433A CN106558592B CN 106558592 B CN106558592 B CN 106558592B CN 201610360433 A CN201610360433 A CN 201610360433A CN 106558592 B CN106558592 B CN 106558592B
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film transistor
grid
layer
tft
insulating layer
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CN106558592A (zh
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林欣桦
高逸群
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Abstract

本发明提供一种阵列基板，其包括基板、设置于基板上的像素阵列以及驱动电路，所述像素阵列包括多个像素单元，每一个像素单元包括一发光二极管、一开关薄膜晶体管、一驱动薄膜晶体管，所述开关薄膜晶体管连接于所述驱动电路与所述驱动薄膜晶体管之间以控制所述驱动薄膜晶体管的导通，所述驱动薄膜晶体管与所述开关薄膜晶体管均为金属氧化物薄膜晶体管，所述驱动薄膜晶体管的栅极绝缘层的厚度大于所述开关薄膜晶体管的栅极绝缘层的厚度。本发明还提供应用该阵列基板的显示装置及该阵列基板的制备方法。本发明可精细的控制所述发光二极管的亮度变化，较好的定义灰阶；可降低操作电压与增加电路操作速度。

Description

阵列基板、显示装置及阵列基板的制备方法
技术领域
本发明涉及一种阵列基板、应用该阵列基板的显示装置、以及该阵列基板的制备方法，尤其涉及一种应用于有机发光二极管Organic Light Emitting Diode，OLED）显示装置的阵列基板。
背景技术
平面显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示装置主要包括液晶显示器（Liquid Crystal Display，LCD）及有机电致发光器件（Organic Electroluminescence Device，OELD），也称为有机发光二极管（Organic LightEmitting Diode，OLED）。一般而言，OLED显示器的显示阵列基板包括一基板，所述基板上设置有连接像素单元的像素阵列及驱动所述像素阵列的驱动电路。
发明内容
有鉴于此，有必要提供一种性能良好的阵列基板。
一种阵列基板，其包括基板、设置于基板上的像素阵列以及驱动电路，所述像素阵列包括多个像素单元，每一个像素单元包括一发光二极管、一开关薄膜晶体管、一驱动薄膜晶体管，所述开关薄膜晶体管连接于所述驱动电路与所述驱动薄膜晶体管之间以控制所述驱动薄膜晶体管的导通，该驱动薄膜晶体管包括依次设置在该基板上的缓冲层、栅极、第一栅极绝缘层、第二栅极绝缘层和金属氧化物半导体层，该驱动薄膜晶体管还包括分别连接于该驱动薄膜晶体管的金属氧化物半导体层的源极与漏极；该开关薄膜晶体管包括依次设置在该基板上的缓冲层、栅极、第二栅极绝缘层、和金属氧化物半导体层，该开关薄膜晶体管还包括分别连接于该开关薄膜晶体管的金属氧化物半导体层的源极与漏极。
一种应用上述阵列基板的显示装置。
一种阵列基板的制备方法，其包括如下步骤：
提供一基板，在基板上形成多晶硅半导体层；
在基板及多晶硅半导体层上沉积形成缓冲层，且在所述缓冲层上沉积第一金属层，蚀刻并图案化所述第一金属层形成多晶硅薄膜晶体管的栅极、驱动薄膜晶体管的栅极、及开关薄膜晶体管的栅极，多晶硅薄膜晶体管的栅极正对所述多晶硅半导体层；
形成第一栅极绝缘层覆盖所述多晶硅薄膜晶体管的栅极与驱动薄膜晶体管的栅极；
形成第二栅极绝缘层覆盖所述第一栅极绝缘层及开关薄膜晶体管的栅极，并开设贯穿所述第一栅极绝缘层与所述第一栅极绝缘层的第一通孔与第二通孔以露出部分多晶硅半导体层；
在第二栅极绝缘层上沉积金属氧化物材料并图案化所述金属氧化物材料从而对应所述驱动薄膜晶体管的栅极及形成驱动薄膜晶体管的氧化物半导体层，并对应开关薄膜晶体管的栅极形成开关薄膜晶体管的氧化物半导体层；
沉积第二金属层并蚀刻图案化所述第二金属层形成填充于第一通孔与第二通孔中且分别连接多晶硅半导体层的源极和漏极、连接所述驱动薄膜晶体管的氧化物半导体层的源极和漏极、及连接所述开关薄膜晶体管的氧化物半导体层的源极和漏极。
一种阵列基板的制备方法，其包括如下步骤：
提供一基板，在基板上形成多晶硅半导体层；
在基板及多晶硅半导体层上沉积形成缓冲层，且在所述缓冲层上沉积第一金属层，蚀刻并图案化所述第一金属层形成多晶硅薄膜晶体管的栅极、驱动薄膜晶体管的栅极、及开关薄膜晶体管的栅极，多晶硅薄膜晶体管的栅极正对所述多晶硅半导体层；
形成第一栅极绝缘层覆盖所述多晶硅薄膜晶体管的栅极与驱动薄膜晶体管的栅极；
形成第二栅极绝缘层覆盖所述第一栅极绝缘层及开关薄膜晶体管的栅极，并开设贯穿所述第一栅极绝缘层与所述第一栅极绝缘层的第一通孔与第二通孔以露出部分多晶硅半导体层；
沉积第二金属层于第二栅极绝缘层上并蚀刻图案化所述第二金属层形成填充于第一通孔与第二通孔中且分别连接多晶硅半导体层的源极和漏极、驱动薄膜晶体管的源极和漏极、开关薄膜晶体管的源极和漏极；
在第二栅极绝缘层上沉积金属氧化物材料并图案化所述金属氧化物材料从而形成驱动薄膜晶体管的氧化物半导体层以连接驱动薄膜晶体管的源极和漏极，并形成开关薄膜晶体管的氧化物半导体层以连接开关薄膜晶体管的源极和漏极。
一种阵列基板的制备方法，其包括如下步骤：
提供一基板，在基板上形成多晶硅半导体层；
在基板及多晶硅半导体层上沉积形成缓冲层，且在所述缓冲层上沉积第一金属层，蚀刻并图案化所述第一金属层形成多晶硅薄膜晶体管的栅极、驱动薄膜晶体管的栅极、及开关薄膜晶体管的栅极，多晶硅薄膜晶体管的栅极正对所述多晶硅半导体层；
形成第一栅极绝缘层覆盖所述多晶硅薄膜晶体管的栅极与驱动薄膜晶体管的栅极；
形成第二栅极绝缘层覆盖所述第一栅极绝缘层及开关薄膜晶体管的栅极，并开设贯穿所述第一栅极绝缘层与所述第一栅极绝缘层的第一通孔与第二通孔以露出部分多晶硅半导体层；
在第二栅极绝缘层上沉积金属氧化物材料并图案化所述金属氧化物材料从而对应所述开关薄膜晶体管的栅极形成开关薄膜晶体管的氧化物半导体层；
沉积第二金属层于第二栅极绝缘层上并蚀刻图案化所述第二金属层形成填充于第一通孔与第二通孔中且分别连接多晶硅半导体层的源极和漏极、驱动薄膜晶体管的源极和漏极、开关薄膜晶体管的源极和漏极；
在第二栅极绝缘层上沉积金属氧化物材料并图案化所述金属氧化物材料从而形成驱动薄膜晶体管的氧化物半导体层以连接驱动薄膜晶体管的源极和漏极。
所述阵列基板的开关薄膜晶体管包括一层栅极绝缘层，而所述驱动薄膜晶体管包括两层栅极绝缘层，所述驱动薄膜晶体管的栅极绝缘层的厚度厚于所述开关薄膜晶体管的栅极绝缘层，从而可以使得所述驱动薄膜晶体管的栅极电容值小于所述开关薄膜晶体管的栅极电容值，进而使得所述驱动薄膜晶体管的亚阈值摆幅大于所述开关薄膜晶体管的亚阈值摆幅。由于驱动薄膜晶体管的亚阈值摆幅较大，可以精细的控制所述发光二极管的亮度变化，很好的定义灰阶。同时由于开关薄膜晶体管的亚阈值摆幅较小，可以降低操作电压与增加电路操作速度。
附图说明
图1为本发明的阵列基板的的示意图。
图2为图1中像素单元的等效电路图。
图3为是图1中阵列基板第一实施方式的剖面结构示意图。
图4至图9为图3所示的阵列基板各制作步骤之剖面结构示意图。
图10为图3中阵列基板的的制造流程图。
图11为图1中阵列基板第二实施方式的剖面结构示意图。
图12为图1中阵列基板第三实施方式的剖面结构示意图。
主要元件符号说明
显示器 1000
阵列基板 100
基板 10
像素阵列 20
驱动电路 30
源极驱动器 36
栅极驱动器 38
像素单元 22
开关薄膜晶体管 223
驱动薄膜晶体管 222
发光二极管 221
多晶硅薄膜晶体管 31
多晶硅半导体层 301
缓冲层 303，403，503
栅极 305，405，505
第一栅极绝缘层 307，407
第二栅极绝缘层 308，408，508
源极 309，409，509
漏极 311，411，511
金属氧化物半导体层 413，513
第一通孔 313
第二通孔 315
平坦层 90
下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请参考图1，一种显示器1000其包括一阵列基板100。所述显示器1000为OLED显示器。所述阵列基板100包括一基板10、多个像素单元22连接形成的像素阵列20、以及驱动电路30。所述基板10为平面矩形材料层，所述基板10可以是，但不限于，玻璃基板、石英基板或柔性基板。所述像素阵列20用于为使用者显示图像，所述像素阵列20由基板10上的多行及多列像素单元22形成。所述驱动电路30包括栅极驱动器38及源极驱动器36。所述驱动电路30可由基板10上的薄膜晶体管形成。其中，所述阵列基板100为一混合型薄膜晶体管(Hybrid thin film transistor)阵列基板，且至少具有低温多晶硅(Low TemperaturePoly Silicon, LTPS)薄膜晶体管与金属氧化物(Metal Oxide)薄膜晶体管设置于其上。
请一并参考图2，每一像素单元22包括一发光二极管221、一开关薄膜晶体管223、一驱动薄膜晶体管222及一电容C。所述开关薄膜晶体管223连接于所述驱动电路30与所述驱动薄膜晶体管222之间，以控制所述驱动薄膜晶体管222的导通与否。所述驱动薄膜晶体管222还连接于一电源VDD与所述发光二极管221之间。所述驱动薄膜晶体管222用于根据流过自身的电流控制所述发光二极管221发射的光的量。所述电容C为一存储电容，连接于所述驱动薄膜晶体管222的栅极与漏极之间，以调整所述驱动薄膜晶体管222状态进而调整所述述发光二极管221发射的光的量。其中所述驱动薄膜晶体管222为一金属氧化物薄膜晶体管。本实施方式中，所述驱动薄膜晶体管222的亚阈值摆幅（Subthreshold Swing）大于所述开关薄膜晶体管223的亚阈值摆幅。其中亚阈值摆幅在数值上表示为使晶体管的漏极电流变化一个数量级时所需要的栅极电压的增量。在本实施例中，所述阵列基板100通过调整驱动薄膜晶体管222及开关薄膜晶体管223的栅极绝缘层的厚度来实现亚阈值摆幅的调整。
请参考图3，为具有不同厚度栅极绝缘层的驱动薄膜晶体管222及开关薄膜晶体管223的阵列基板100的薄膜晶体管的剖面结构示意图，可以理解的是，剖面结构示意图仅示出所述阵列基板100的部分（如所述阵列基板100的一个多晶硅薄膜晶体管31、一个开关薄膜晶体管223及一个驱动薄膜晶体管222）。其中，所述多晶硅薄膜晶体管31可设置在驱动电路30中，用于形成所述栅极驱动器38或源极驱动器36所需的开关元件，也可设置在像素单元22中，作为补偿用的薄膜晶体管。
可以理解的是，所述阵列基板100还包括所述发光二极管221的阴极、阳极、发射材料（图未示）。其中，所述发光二极管221的阳极连接所述驱动薄膜晶体管222的漏极，所述发射材料设置于所述发光二极管的阴极与阳极之间。所述阵列基板100还包括介电层（图未示）及平坦层90，所述介电层形成于所述发射材料的两侧，用于界定像素单元的布局，所述平坦层90形成于所述薄膜晶体管的顶部。
本实施方式中，所述多晶硅薄膜晶体管31为一低温多晶硅薄膜晶体管，所述驱动薄膜晶体管222为一金属氧化物薄膜晶体管，所述开关薄膜晶体管223同样为一金属氧化物薄膜晶体管。
所述多晶硅薄膜晶体管31包括多晶硅半导体层301、缓冲层303、栅极305、第一栅极绝缘层307、第二栅极绝缘层308、源极309与漏极311。所述多晶硅半导体层301、缓冲层303、栅极305、第一栅极绝缘层307及第二栅极绝缘层308依次层叠设置在所述基板10上。所述源极309经贯穿所述缓冲层303、第一栅极绝缘层307、第二栅极绝缘层308的第一通孔313与所述多晶硅半导体层301连接，所述漏极311经贯穿所述缓冲层303、第一栅极绝缘层307、第二栅极绝缘层308的第二通孔315与所述多晶硅半导体层301连接。
所述驱动薄膜晶体管222包括缓冲层403、栅极405、第一栅极绝缘层407、第二栅极绝缘层408、源极409、漏极411及金属氧化物半导体层413。所述缓冲层403、栅极405、第一栅极绝缘层407、第二栅极绝缘层408、所述金属氧化物半导体层413依次设置在所述基板10上。所述源极409与所述漏极411同层设置。所述金属氧化物半导体层413用于连接所述源极409与所述漏极411。在本实施方式中，所述金属氧化物半导体层413为氧化铟镓锌(IndiumGallium Zinc Oxide, IGZO)。
所述开关薄膜晶体管223包括缓冲层503、栅极505、第二栅极绝缘层508、源极509、漏极511及金属氧化物半导体层513。所述缓冲层503、栅极505、第二栅极绝缘层508及金属氧化物半导体层513依次设置在所述基板10上。所述源极509与所述漏极511同层设置。所述金属氧化物半导体层513用于连接所述源极509与所述漏极511。在本实施方式中，所述金属氧化物半导体层513为氧化铟镓锌。
本实施方式中，所述缓冲层303、缓冲层403与缓冲层503同层设置，所述第一栅极绝缘层307与第一栅极绝缘层407同层设置，所述第二栅极绝缘层308、第二栅极绝缘层408与第二栅极绝缘层508同层设置。同层设置之所述缓冲层303、缓冲层403与缓冲层503采用绝缘材料制成。同层设置之所述第一绝缘层307、第一栅极绝缘层407采用氮化硅制成；同层设置之所述第二栅极绝缘层308、第二栅极绝缘层408与第二栅极绝缘层508采用氧化硅制成。或同层设置之所述第一绝缘层307、第一栅极绝缘层407采用氧化硅制成；同层设置之所述第二栅极绝缘层308、第二栅极绝缘层408与第二栅极绝缘层508采用氮化硅制成。
请一并参阅4至图10，其中图4至图9为图3所示的阵列基板100各制作步骤之结构示意图，图10为图3所示的阵列基板100的制造流程图。该阵列基板100的制备方法包括如下步骤：
步骤601，请参阅图4，提供一基板10，在基板10上沉积非晶硅并经过退火(annealing)、离子掺杂形成多晶硅半导体层301。所述基板10可以是，但不限于，玻璃基板、石英基板或柔性基板。
步骤603，请参阅图5，沉积形成所述缓冲层303、403、503，且在所述缓冲层303、403、503上沉积第一金属层，蚀刻并图案化所述第一金属层形成栅极305、405、505。其中，在本实施方式中，先在形成有所述多晶硅半导体层301的所述基板10上涂布一绝缘材料层，从而形成覆盖所述多晶硅半导体层301的缓冲层303以及缓冲层403与503。接着，沉积所述第一金属层，通过黄光微影蚀刻法蚀刻第一金属层以形成所述栅极305、405、505，所述第一金属层可为金属材料或金属合金，如钼(Mo)、铝(Al)、铬(Cr)、铜(Cu)、钕(Nd)等。所述黄光微影蚀刻法为液晶显示面板的阵列基板制备工艺中常见的工艺步骤，此处不再赘述。
步骤605，请参阅图6，沉积一第一绝缘层并覆盖所述栅极305、405、505，并利用光罩屏蔽所述栅极305、405以剥离所述栅极505上的第一绝缘层形成所述第一栅极绝缘层307、407。
其中，所述第一绝缘层采用氮化硅或氧化硅制成，优选地，所述第一绝缘层采用氮化硅制成。
步骤607，请参阅图7，接续沉积一第二绝缘层形成第二栅极绝缘层308、408、508，并利用光罩屏蔽所述第二栅极绝缘层308、408、508及所述缓冲层203上定义出贯穿所述第一绝缘层与所述第二绝缘层的第一通孔313与第二通孔315，从而曝露处出部分多晶硅半导体层301。
其中，所述第二绝缘层采用氮化硅或氧化硅制成，优选地，所述第二绝缘层采用氧化硅制成。且所述当第一绝缘层为氮化硅，第二绝缘层为氧化硅时，会使得开关薄膜晶体管223及驱动薄膜晶体管222的功能稳定。
步骤609，请参阅图8，沉积金属氧化物材料并图案化所述金属氧化物材料从而对应所述栅极405、505形成所述氧化物半导体层413、513。在本实施方式中，所述氧化物半导体层413、513材料为氧化铟镓锌(Indium Gallium Zinc Oxide, IGZO)、氧化锌(ZincOxide, ZnO)、氧化铟(Indium Oxide, InO)、氧化镓(Gallium Oxide, GaO)或其混合物。
步骤611，请参阅图9，沉积第二金属层并蚀刻图案化所述第二金属层形成源极309、409、509与漏极311、411及511。其中，所述源极309经所述第一通孔313与所述多晶硅半导体层301连接，所述漏极311经所述第二通孔315与所述多晶硅半导体层301连接。
步骤613，请参阅图3，形成平坦化层90覆盖所述薄膜晶体管31、222、223，然后形成发光二极管221的发射材料、阴极、介电层及与所述驱动薄膜晶体管222连接的阳极。
本实施方式中，所述多晶硅薄膜晶体管31为低温多晶硅式薄膜晶体管，其可以但不限于设置于所述显示器1000的非显示区内。当所述多晶硅薄膜晶体管31设置于所述显示器1000的非显示区内时，所述多晶硅式薄膜晶体管31具有高电子迁移率进而提高的驱动电路的反应速度，且所述多晶硅式薄膜晶体管31体积小可使显示装置达到窄边框。
进一步，所述开关薄膜晶体管223包括一层栅极绝缘层而所述驱动薄膜晶体管222包括两层栅极绝缘层，所述驱动薄膜晶体管222的栅极绝缘层的厚度大于所述开关薄膜晶体管223的栅极绝缘层的厚度，从而可以使得所述驱动薄膜晶体管222的栅极电容值小于所述开关薄膜晶体管223的栅极电容值，进而使得所述驱动薄膜晶体管222的亚阈值摆幅大于所述开关薄膜晶体管223的亚阈值摆幅。由于驱动薄膜晶体管222的亚阈值摆幅较大，可以精细的控制所述发光二极管221的亮度变化，很好的定义灰阶。同时由于开关薄膜晶体管223的亚阈值摆幅较小，可以降低操作电压与增加电路操作速度。
请参考图11，为OLED之阵列基板的薄膜晶体管第二实施方式的剖面结构示意图。后续的描述中与前述实施方式相同的元件采用相同的元件标号，且本实施方式与前述实施方式的薄膜晶体管阵列的结构相同之处不再重复描述，后续仅描述不同之处。在本实施方式中，为避免氧化物薄膜晶体管进行高温氢化制程时对所述金属氧化物半导体的损害，所述驱动薄膜晶体管222的金属氧化物半导体层413在驱动薄膜晶体管222的源极409与漏极411形成之后形成，以避免蚀刻所述第二金属层形成源极409与漏极411时对所述金属氧化物半导体413的损害。也就是说，所述驱动薄膜晶体管222的源极409与所述漏极411同层设置完成之后，所述金属氧化物半导体层413对应栅极405设置在第二栅极绝缘层408上。
对应的，在制作如图11所示的OLED之阵列基板时，在形成第二栅极绝缘层并定义第一及第二通孔之后，沉积金属氧化物材料形成开关薄膜晶体管223的氧化物半导体层513，接着沉积第二金属层并蚀刻图案化所述第二金属层形成所述多晶硅薄膜晶体管31、所述开关薄膜晶体管223及所述驱动薄膜晶体管222的源极与漏极，然后再次沉积金属氧化物材料形成驱动薄膜晶体管222的金属氧化物半导体层413。
如图12所示，所述开关薄膜晶体管223或驱动薄膜晶体管222的金属氧化物半导体层413、513均在形成源极409、509与漏极411、511之后形成，以避免蚀刻所述第二金属层形成源极409、509与漏极411、511时，对所述金属氧化物半导体造成损害。
可以理解的是，其他实施方式中，可选的，所述开关薄膜晶体管223或驱动薄膜晶体管222中其中之一的金属氧化物半导体层413、513在形成源极409、509与漏极411、511之后形成。如，仅选择开关薄膜晶体管223的金属氧化物半导体层513在形成源极509与漏极511之后形成。
另外，本领域技术人员还可在本发明权利要求公开的范围和精神内做其它形式和细节上的各种修改、添加和替换。当然，这些依据本发明精神所做的各种修改、添加和替换等变化，都应包含在本发明所要求保护的范围之内。

Claims (11)

1.一种阵列基板，其包括基板、设置于基板上的像素阵列以及驱动电路，所述像素阵列包括多个像素单元，每一个像素单元包括一发光二极管、一开关薄膜晶体管、一驱动薄膜晶体管，所述开关薄膜晶体管连接于所述驱动电路与所述驱动薄膜晶体管之间以控制所述驱动薄膜晶体管的导通，其特征在于：该驱动薄膜晶体管包括依次设置在该基板上的缓冲层、栅极、第一栅极绝缘层、第二栅极绝缘层和金属氧化物半导体层，该驱动薄膜晶体管还包括分别连接于该驱动薄膜晶体管的金属氧化物半导体层的源极与漏极；该开关薄膜晶体管包括依次设置在该基板上的缓冲层、栅极、第二栅极绝缘层、和金属氧化物半导体层，该开关薄膜晶体管还包括分别连接于该开关薄膜晶体管的金属氧化物半导体层的源极与漏极；所述阵列基板还包括至少一多晶硅薄膜晶体管，所述多晶硅薄膜晶体管包括依次设置在基板上的多晶硅半导体层、缓冲层、栅极、第一栅极绝缘层及第二栅极绝缘层。
2.如权利要求1所述的阵列基板，其特征在于：所述阵列基板还包括平坦化层，该平坦化层覆盖所述开关薄膜晶体管、所述驱动薄膜晶体管和所述多晶硅薄膜晶体管。
3.如权利要求1所述的阵列基板，其特征在于：所述驱动电路包括栅极驱动器及源极驱动器，所述多晶硅薄膜晶体管设置在驱动电路中，用于形成所述栅极驱动器或源极驱动器的开关元件。
4.如权利要求1所述的阵列基板，其特征在于：所述多晶硅薄膜晶体管设置在所述像素单元中。
5.如权利要求1所述的阵列基板，其特征在于：所述驱动薄膜晶体管、所述开关薄膜晶体管与所述多晶硅薄膜晶体管的缓冲层为同层设置，所述多晶硅薄膜晶体管与所述驱动薄膜晶体管的第一栅极绝缘层为同层设置，所述驱动薄膜晶体管、所述开关薄膜晶体管与所述多晶硅薄膜晶体管的第二栅极绝缘层为同层设置。
6.如权利要求5所述的阵列基板，其特征在于：所述多晶硅薄膜晶体管还包括分别贯穿所述缓冲层、第一栅极绝缘层、第二栅极绝缘层且与所述多晶硅半导体层连接的源极和漏极。
7.一种应用权利要求1-6中任意一项所述阵列基板的显示装置。
8.一种阵列基板的制备方法，其特征在于，包括如下步骤：
提供一基板，在基板上形成多晶硅半导体层；
在所述基板及所述多晶硅半导体层上沉积形成缓冲层，且在所述缓冲层上沉积第一金属层，蚀刻并图案化所述第一金属层形成多晶硅薄膜晶体管的栅极、驱动薄膜晶体管的栅极、及开关薄膜晶体管的栅极，所述多晶硅薄膜晶体管的栅极正对所述多晶硅半导体层；
形成第一栅极绝缘层覆盖所述多晶硅薄膜晶体管的栅极与所述驱动薄膜晶体管的栅极；
形成第二栅极绝缘层覆盖所述第一栅极绝缘层及所述开关薄膜晶体管的栅极，并开设贯穿所述第一栅极绝缘层与所述第一栅极绝缘层的第一通孔与第二通孔以露出部分所述多晶硅半导体层；
在所述第二栅极绝缘层上沉积金属氧化物材料并图案化所述金属氧化物材料从而对应所述驱动薄膜晶体管的栅极及形成驱动薄膜晶体管的氧化物半导体层，并对应该开关薄膜晶体管的栅极形成开关薄膜晶体管的氧化物半导体层；
沉积第二金属层并蚀刻图案化所述第二金属层形成填充于第一通孔与第二通孔中且分别连接多晶硅半导体层的源极和漏极、连接所述驱动薄膜晶体管的氧化物半导体层的源极和漏极、及连接所述开关薄膜晶体管的氧化物半导体层的源极和漏极。
9.如权利要求8所述的制备方法，其特征在于：所述方法还包括形成平坦化层覆盖所述开关薄膜晶体管、所述驱动薄膜晶体管和所述多晶硅薄膜晶体管；然后然后依次形成与所述驱动薄膜晶体管连接发射材料、阴极、介电层及阳极。
10.一种阵列基板的制备方法，其特征在于，包括如下步骤：
提供一基板，在基板上形成多晶硅半导体层；
在基板及多晶硅半导体层上沉积形成缓冲层，且在所述缓冲层上沉积第一金属层，蚀刻并图案化所述第一金属层形成多晶硅薄膜晶体管的栅极、驱动薄膜晶体管的栅极、及开关薄膜晶体管的栅极，多晶硅薄膜晶体管的栅极正对所述多晶硅半导体层；
形成第一栅极绝缘层覆盖所述多晶硅薄膜晶体管的栅极与驱动薄膜晶体管的栅极；
形成第二栅极绝缘层覆盖所述第一栅极绝缘层及开关薄膜晶体管的栅极，并开设贯穿所述第一栅极绝缘层与所述第一栅极绝缘层的第一通孔与第二通孔以露出部分多晶硅半导体层；
沉积第二金属层于第二栅极绝缘层上并蚀刻图案化所述第二金属层形成填充于第一通孔与第二通孔中且分别连接多晶硅半导体层的源极和漏极、驱动薄膜晶体管的源极和漏极、开关薄膜晶体管的源极和漏极；
在第二栅极绝缘层上沉积金属氧化物材料并图案化所述金属氧化物材料从而形成驱动薄膜晶体管的氧化物半导体层以连接驱动薄膜晶体管的源极和漏极，并形成开关薄膜晶体管的氧化物半导体层以连接开关薄膜晶体管的源极和漏极。
11.一种阵列基板的制备方法，其特征在于，包括如下步骤：
提供一基板，在基板上形成多晶硅半导体层；
在基板及多晶硅半导体层上沉积形成缓冲层，且在所述缓冲层上沉积第一金属层，蚀刻并图案化所述第一金属层形成多晶硅薄膜晶体管的栅极、驱动薄膜晶体管的栅极、及开关薄膜晶体管的栅极，多晶硅薄膜晶体管的栅极正对所述多晶硅半导体层；
形成第一栅极绝缘层覆盖所述多晶硅薄膜晶体管的栅极与驱动薄膜晶体管的栅极；
形成第二栅极绝缘层覆盖所述第一栅极绝缘层及开关薄膜晶体管的栅极，并开设贯穿所述第一栅极绝缘层与所述第一栅极绝缘层的第一通孔与第二通孔以露出部分多晶硅半导体层；
在第二栅极绝缘层上沉积金属氧化物材料并图案化所述金属氧化物材料从而对应所述开关薄膜晶体管的栅极形成开关薄膜晶体管的氧化物半导体层；
沉积第二金属层于第二栅极绝缘层上并蚀刻图案化所述第二金属层形成填充于第一通孔与第二通孔中且分别连接多晶硅半导体层的源极和漏极、驱动薄膜晶体管的源极和漏极、开关薄膜晶体管的源极和漏极；
在第二栅极绝缘层上沉积金属氧化物材料并图案化所述金属氧化物材料从而形成驱动薄膜晶体管的氧化物半导体层以连接驱动薄膜晶体管的源极和漏极。
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