TWI565082B - 薄膜電晶體及其製造方法 - Google Patents

薄膜電晶體及其製造方法 Download PDF

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TWI565082B
TWI565082B TW104111918A TW104111918A TWI565082B TW I565082 B TWI565082 B TW I565082B TW 104111918 A TW104111918 A TW 104111918A TW 104111918 A TW104111918 A TW 104111918A TW I565082 B TWI565082 B TW I565082B
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layer
film transistor
thin film
photoresist pattern
photoresist
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TW201637220A (zh
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方國龍
高逸群
林欣樺
李誌隆
施博理
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鴻海精密工業股份有限公司
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Priority to US14/726,160 priority patent/US9437750B1/en
Priority to US15/215,911 priority patent/US9576990B2/en
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Description

薄膜電晶體及其製造方法
本發明涉及一種薄膜電晶體及一種該自對準的金屬氧化物薄膜電晶體的製造方法。
現有薄膜電晶體製造方法需要六道光罩製程。六道光罩製程使製程複雜、製造成本較高。且經過六道光罩製程的薄膜電晶體由於每道製程均需要光罩與薄膜電晶體的對位而降低薄膜電晶體的精度。
有鑑於此，有必要提供一種可簡化製程的薄膜電晶體的製造方法及薄膜電晶體。
一種薄膜電晶體，包括：基板；閘極，設置在該基板上；閘極絕緣層覆蓋該閘極；通道層，設置在該閘極絕緣層上；蝕刻阻擋層，設置在該通道層上，且該蝕刻阻擋層定義第一通孔 與第二通孔；源極設置在該蝕刻阻擋層上經該第一通孔與該通道層連接，且沿該蝕刻阻擋層延伸到該閘極絕緣層的一側；及汲極設置在該蝕刻阻擋層上經該第二通孔與該通道層連接，且沿該蝕刻阻擋層延伸到該閘極絕緣層的另一側。
優選的，該通道層沿該閘極的中心線相互對稱。
優選的，該通道層兩側邊未被該蝕刻阻擋層覆蓋的長度相同。
優選的，該通道層兩側邊未被該蝕刻阻擋層覆蓋的長度為0.3-0.5微米。
一種薄膜電晶體的製造方法，包括：提供一基板，在該基板上依次形成閘極、閘極絕緣層、半導體層及蝕刻阻擋圖案；在該蝕刻阻擋圖案上塗布光阻層；利用遮罩遮罩光刻該光阻層形成第一光阻圖案，該第一光阻圖案包括至少二梯形凹槽；以該第一光阻圖案作遮罩蝕刻該蝕刻阻擋圖案形成蝕刻阻擋層；加熱該第一光阻圖案形成回流到達該通道層形成第二光阻圖案；以該第二光阻圖案作遮罩蝕刻該半導體層，該半導體層形成該薄膜電晶體的通道層；灰化該第三光阻圖案形成第四光阻圖案，該梯形凹槽被灰化至與該蝕刻阻擋層連接； 以該第三光阻圖案作遮罩蝕刻該蝕刻阻擋層形成第一通孔及第二通孔；及移除第四光阻圖案，並在該第一通孔與該第二通孔上形成源極與汲極。
優選的，該遮罩是半透遮罩或灰透遮罩。
優選的，該半透遮罩包括設置在該遮罩相對兩端的二全透射部，三個非透射部與二半透射部間隔設置在該二全透射部之間，該二全透射部設置在該光阻層的相對兩端，其中一非透射部設置在該光阻層中部，該二半透射部用於形成該二梯形凹槽。
優選的，該二梯形凹槽的深度為該第一光阻圖案厚度的一半。
優選的，該第一光阻圖案的加熱溫度介於80-175℃範圍內。
優選的，通過注入氧氣或臭氧灰化該第三光阻圖案形成第四光阻圖案。
相較於先前技術，本發明的薄膜電晶體的製造方法在同一道光罩製程中形成通道層、蝕刻阻擋層的第一通孔及第二通孔，從而簡化製程降低薄膜電晶體的製造成本。進一步，由於薄膜電晶體的製造方法減少了製程步驟，薄膜電晶體可以得到更高的精度。特別是，該通道層沿該閘極的中心線相互對稱，該通道層兩側邊位於該二側邊未被該蝕刻阻擋層覆蓋的長度相同。
100‧‧‧薄膜電晶體
110‧‧‧基板
120‧‧‧閘極
130‧‧‧閘極絕緣層
140‧‧‧半導體層
142‧‧‧通道層
150‧‧‧蝕刻阻擋層
152‧‧‧第一通孔
154‧‧‧第二通孔
172‧‧‧源極
174‧‧‧汲極
140‧‧‧半導體層
1422‧‧‧側邊
160‧‧‧光阻層
200‧‧‧製造方法
202‧‧‧全透射部
204‧‧‧非透射部
206‧‧‧半透射部
162‧‧‧第一光阻圖案
1621‧‧‧梯形凹槽
1622‧‧‧第一高度部
1624‧‧‧第二高度部
151‧‧‧蝕刻阻擋圖案
163‧‧‧第三光阻圖案
1634‧‧‧底部
164‧‧‧第四光阻圖案
111‧‧‧中心線
S201-S209‧‧‧步驟
圖1是本發明自對準薄膜電晶體一實施方式的平面示意圖。
圖2是圖1所示的薄膜電晶體沿II-II線的剖面結構示意圖。
圖3是圖1所示的薄膜電晶體製造流程示意圖。
圖4至圖11是圖1所示薄膜電晶體各製作步驟結構示意圖。
請一併參閱圖1、圖2，圖1是本發明自對準薄膜電晶體一實施方式的平面示意圖，圖2是圖1所示的薄膜電晶體沿II-II線的剖面結構示意圖。薄膜電晶體100為自對準金屬氧化物薄膜電晶體(self-aligned metal oxide thin film transistor)。該薄膜電晶體100包括基板110、設置在基板110中部的閘極120、設置在基板110與閘極120上的閘極絕緣層130、設置在該閘極絕緣層130上且對應該閘極120的通道層142、設置在該通道層142上蝕刻阻擋層150，該蝕刻阻擋層150定義第一通孔152與第二通孔154，該源極172設置在該蝕刻阻擋層150上經該第一通孔152與該通道層142連接，該汲極174經該第二通孔154與該通道層142連接。
該閘極絕緣層130覆蓋該閘極120以使該閘極120與通道層142相互絕緣。該通道層142設置在閘極絕緣層130上用於連接源極172與汲極174。該源極172由該閘極絕緣層130延伸至該第一通孔152，該汲極174由該閘極絕緣層130延伸至該第二通孔154。
請一併參閱圖3-圖11，圖3是本發明薄膜電晶體100製造方法200流程示意圖，圖4至圖11是圖1所示薄膜電晶體各製作步驟結構示意圖。
步驟201，請參閱圖4，提供一基板110，在基板110中部形成閘極120。閘極絕緣層130覆蓋該閘極120。然後，半導體層140、蝕刻阻擋圖案151及光阻層160依次層疊形成在該閘極絕緣層130上。
具體地，在基板110上沉積金屬層，圖案化該金屬層形成閘極120。在本實施方式中，基板110可為玻璃基板、者石英基板，有機聚合物基板或其他透明基板。該金屬層可為金屬材料或金屬合金，如鉬(Mo)、鋁(Al)、鉻(Cr)、銅(Cu)、釹(Nd)或其合金等。
該閘極絕緣層130為無機材料，如氧化矽、氮化矽、或氮氧化矽等。在本實施方式中，可利用等離子增強化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition,PEVCD)形成。該通道層142材料為金屬氧化物半導體，如氧化銦鎵鋅(IGZO)、氧化鋅(ZnO)、氧化銦(InO)、氧化鎵(GaO)或其混合物。該蝕刻阻擋圖案151的材料為氮化矽、氧化矽或其他絕緣材料。該光阻層160是光感化合物與樹脂的混合。該樹脂為熱塑性樹脂。該光阻層160的厚度為1.25-2.5微米，優選地，本實施方式中，該光阻層160的厚度為1.5微米。該光阻層160為正向光阻，該正向光阻被光照部分溶於光阻顯影液。在其他實施方式中，該光阻層160可為負向光阻。
步驟S202，請參閱圖5，半透(half-tone)或灰透(gray-tone)遮罩200設置在該光阻層160上方用於光刻該光阻層160。該半透遮罩200包括設置在該遮罩200相對兩端的二全透射部202。三個遮擋部204與二半透射部206間隔設置在三個遮擋部204之間。該二全透射部202設置在該光阻層160的相對兩端，其中一非透射部204設置在該光阻層160中部。
步驟S203，請參閱圖6，對該光阻層160執行光刻步驟，該光阻層被圖案化為第一光阻圖案162。該第一光阻圖案162位置對應該閘極120。利用該半透遮罩200曝光、蝕刻該光阻層160得到該第一 光阻圖案162。該第一光阻圖案162包括二梯形凹槽1621，三第一高度部1622與二第二高度部1624。該第一高度部1622與該梯形凹槽1621間隔設置，該第二高度部1624為該梯形凹槽1621的底部。在本實施方式中，該每一第一高度部1622的厚度為該第二高度部1624厚度的兩倍。該全透射部202所對應之光阻層160全部被蝕刻至該蝕刻阻擋層150。
步驟S204，請參閱圖7，以該第一光阻圖案162作遮罩蝕刻該蝕刻阻擋圖案151形成蝕刻阻擋圖層150。該蝕刻阻擋層150的側邊與該第一光阻圖案162的底部側邊對齊。在步驟204中可以使用幹蝕刻，如等離子蝕刻(Plasma Etching)該蝕刻阻擋圖案151。
步驟S205，請參閱圖8，加熱該第一光阻圖案162形成回流。通過紅外爐或加熱滾筒加熱使該第一光阻圖案162軟化並向下流至該半導體層140形成第三光阻圖案163。在本實施方式中，該第一光阻圖案162的加熱溫度介於80-175℃範圍之間。該第三光阻圖案163的底部1634形成傾斜部覆蓋該半導體層140。
步驟S206，請參閱圖9，以該第三光阻圖案163作遮罩蝕刻該半導體層140。在本實施方式中，蝕刻該半導體層140的方法可以是濕蝕刻，如酸溶液蝕刻移除未被該第三光阻圖案163覆蓋的半導體層140。在步驟206中，該半導體層140形成該薄膜電晶體100的通道層142。
步驟S207，請參閱圖10，通過注入氧氣(O2)或臭氧(O3)灰化該第三光阻圖案163形成第四光阻圖案164。該梯形凹槽1621被灰化至與該蝕刻阻擋圖案151連接。
步驟S208，請參閱圖11，以該第四光阻圖案164作遮罩蝕刻該蝕刻阻擋圖案151形成第一通孔152與第二通孔154。
步驟S209，請再次參閱圖1，移除第四光阻圖案14，在該第一通孔152與該第二通孔154上形成源極172與汲極174。該源極172設置在該蝕刻阻擋層150上經該第一通孔152與該通道層142連接，且沿該蝕刻阻擋層150延伸到該閘極絕緣層130；及該汲極174設置在該蝕刻阻擋層150上經該第二通孔154與該通道層142連接，且沿該蝕刻阻擋層150延伸到該閘極絕緣層130。該源、汲極172、174為金屬材料或金屬合金，如鉬(Mo)、鋁(Al)、鉻(Cr)、銅(Cu)、釹(Nd)或其合金等
本發明的薄膜電晶體100的製造方法在同一道光罩製程中形成通道層142、第一通孔152與第二通孔154，從而簡化製程降低薄膜電晶體100的製造成本。進一步，由於薄膜電晶體100的製造方法減少了製程步驟，薄膜電晶體可以得到更高的精度。特別是，該通道層142沿該閘極120的中心線111相互對稱，該通道層142兩側邊1422位於未被該蝕刻阻擋層150覆蓋區域的長度相同，且該長度為0.3-0.5微米。
如上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，本發明之範圍並不以上述實施方式為限，舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。
100‧‧‧薄膜電晶體
110‧‧‧基板
120‧‧‧閘極
130‧‧‧閘極絕緣層
142‧‧‧通道層
150‧‧‧蝕刻阻擋層
152‧‧‧第一通孔
154‧‧‧第二通孔
172‧‧‧源極
174‧‧‧汲極
140‧‧‧半導體層
1422‧‧‧側邊
111‧‧‧中心線

Claims (10)

  1. 一種薄膜電晶體，包括：基板；閘極，設置在該基板上；閘極絕緣層覆蓋該閘極；通道層，設置在該閘極絕緣層上；蝕刻阻擋層，設置在該通道層上，且該蝕刻阻擋層定義第一通孔與第二通孔，該通道層的兩側邊未被該蝕刻阻擋層覆蓋；源極設置在該蝕刻阻擋層上經該第一通孔與該通道層連接，且沿該蝕刻阻擋層延伸到該閘極絕緣層的一側；及汲極設置在該蝕刻阻擋層上經該第二通孔與該通道層連接，且沿該蝕刻阻擋層延伸到該閘極絕緣層的另一側。
  2. 如請求項1所述之薄膜電晶體，其中，該通道層沿該閘極的中心線相互對稱。
  3. 如請求項1所述之薄膜電晶體，其中，該通道層兩側邊未被該蝕刻阻擋層覆蓋的長度相同。
  4. 如請求項3所述之薄膜電晶體，其中，該通道層兩側邊未被該蝕刻阻擋層覆蓋的長度為0.3-0.5微米。
  5. 一種薄膜電晶體的製造方法，包括：提供一基板，在該基板上依次形成閘極、閘極絕緣層、半導體層及蝕刻阻擋圖案；在該蝕刻阻擋圖案上塗布光阻層；利用遮罩遮罩光刻該光阻層形成第一光阻圖案，該第一光阻圖案包括至 少二梯形凹槽；以該第一光阻圖案作遮罩蝕刻該蝕刻阻擋圖案形成蝕刻阻擋層；加熱該第一光阻圖案形成回流到達該半導體層形成第二光阻圖案；以該第二光阻圖案作遮罩蝕刻該半導體層，該半導體層形成該薄膜電晶體的通道層；灰化該第三光阻圖案形成第四光阻圖案，該梯形凹槽被灰化至與該蝕刻阻擋層連接；以該第三光阻圖案作遮罩蝕刻該蝕刻阻擋層形成第一通孔及第二通孔；及移除第四光阻圖案，並在該第一通孔與該第二通孔上形成源極與汲極。
  6. 如請求項5所述之薄膜電晶體的製造方法，其中，該遮罩是半透遮罩或灰透遮罩。
  7. 如請求項6所述的薄膜電晶體的製造方法，其中，該半透遮罩包括設置在該遮罩相對兩端的二全透射部，三個非透射部與二半透射部間隔設置在該二全透射部之間，該二全透射部設置在該光阻層的相對兩端，其中一非透射部設置在該光阻層中部，該二半透射部用於形成該二梯形凹槽。
  8. 如請求項7所述的薄膜電晶體的製造方法，其中，該二梯形凹槽的深度為該第一光阻圖案厚度的一半。
  9. 如請求項6所述的薄膜電晶體的製造方法，其中，該第一光阻圖案的加熱溫度介於80-175℃範圍內。
  10. 如請求項6所述的薄膜電晶體的製造方法，其中，通過注入氧氣或臭氧灰化該第三光阻圖案形成第四光阻圖案。
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