WO2016078134A1 - 薄膜晶体管的制造方法 - Google Patents

薄膜晶体管的制造方法 Download PDF

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Publication number
WO2016078134A1
WO2016078134A1 PCT/CN2014/092778 CN2014092778W WO2016078134A1 WO 2016078134 A1 WO2016078134 A1 WO 2016078134A1 CN 2014092778 W CN2014092778 W CN 2014092778W WO 2016078134 A1 WO2016078134 A1 WO 2016078134A1
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layer
metal layer
thin film
film transistor
substrate
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PCT/CN2014/092778
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English (en)
French (fr)
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阙祥灯
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深圳市华星光电技术有限公司
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Publication of WO2016078134A1 publication Critical patent/WO2016078134A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34

Definitions

  • the present invention relates to the field of manufacturing thin film transistors, and more particularly to a method of fabricating a thin film transistor having a high yield.
  • a thin film transistor is widely used as a switching element in an electronic device such as a liquid crystal display device.
  • the thin film transistor first forms a metal layer and then lays a photoresist layer on the metal layer.
  • the photomask has full light transmission.
  • the pattern of the opaque area and the semi-transmissive area such that the light passes through the reticle and is completely transparent, and the amount of light transmitted by the opaque area and the semi-transmissive area is different, and the amount of light perceived by the photoresist is different.
  • the deposited photoresist forms different residual film amounts.
  • the photoresist film in the opaque region is thickest, and the photoresist in the semi-transmissive region is residual. The remaining half of the film.
  • the metal is protected by the residue of the photoresist, so that when the metal is etched, the metal is protected by the photoresist.
  • the channel region is formed by forming a photoresist film having a thickness of about half of the thickness through the semi-transmissive region of the photomask.
  • the semi-transmissive region of the channel is usually designed to be relatively small, and is affected by the diffraction of light.
  • the photoresist layer that needs to form the channel region has a strong light and the photoresist film is thin. That is, the residual film value of the photoresist layer after exposure is low.
  • a low residual film value causes an abnormal design of the thin film transistor at the source and drain formed, and an abnormality of the source and the drain may cause the thin film transistor to malfunction, resulting in a low yield of the thin film transistor.
  • the present invention provides a method of manufacturing a thin film transistor, which can improve the low residual film value of the photoresist layer after exposure of the thin film transistor at the time of manufacture, thereby improving the yield of the thin film transistor.
  • a method of manufacturing a thin film transistor comprising:
  • a gate insulating layer, a semiconductor layer, and a second metal layer on a surface of the substrate on which the first metal layer is formed and the first metal layer, the gate insulating layer, the semiconductor layer, and the second a metal layer is sequentially stacked; wherein the semiconductor layer is used to form a channel that is turned on or off between a source and a drain of the thin film transistor;
  • the photoresist layer includes a first portion and a second portion at opposite edges of the first portion, the width of the first portion being the same as the width of the second metal layer and superimposed The second portion is extended by the edge of the first portion in the width direction, and the width of the photoresist layer is greater than the width of the second metal layer;
  • the "gate insulating layer, the semiconductor layer and the second metal layer are formed on the surface of the substrate on which the first metal layer is formed and the first metal layer, the gate insulating layer, the semiconductor The layer and the second metal layer are sequentially stacked and arranged" includes:
  • the second metal layer is formed on the ohmic contact layer.
  • step of "patterning the second metal layer and the semiconductor layer to form the channel to define the source and drain” comprises:
  • the semi-transmissive region of the photoresist layer is removed.
  • the material of the channel layer is polysilicon, and the material of the ohmic contact layer is n-type heavily doped amorphous silicon.
  • the step of "providing a substrate” and the step of “forming a first metal layer in a middle portion of one surface of the substrate, the first metal layer being a gate of the thin film transistor” further includes step:
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the material of the first metal layer is selected from one of copper, tungsten, chromium, aluminum and a combination thereof
  • the material of the second metal layer is selected from the group consisting of copper, tungsten, chromium, aluminum and combinations thereof.
  • the method includes:
  • the photoresist layer is removed.
  • the method for manufacturing the thin film transistor further includes: after the step of “defining the source and the drain”.
  • the first pass hole and the second through hole are defined in the passivation layer corresponding to the source and the drain;
  • a first electrode is disposed corresponding to the first through hole, and a second electrode is disposed corresponding to the second through hole, and the first electrode and the second electrode are respectively connected to the source and the drain.
  • the second portion of the photoresist layer has a width dimension greater than 0.5 um.
  • the manufacturing method of the thin film transistor of the present invention after the light emitted from the light source passes through the photomask
  • the width of the semi-transmissive region formed by the remaining photoresist layer is larger than the width of the semi-transmissive region formed by the photoresist layer remaining after the photoresist layer passes through the mask in the prior art;
  • the second portion of the semi-transmissive region absorbs the diffracted light around the semi-transmissive region, thereby avoiding a decrease in the residual film value of the channel region, thereby improving the residual of the semi-transmissive region in the prior art.
  • the low film value causes the semiconductor between the source and the drain of the thin film transistor to be punctured, causing a problem of defining an abnormality, thereby improving the manufacturing yield of the thin film transistor.
  • FIG. 1 is a flow chart of a method of fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • FIGS. 9 to 15 and 17 to 19 are cross-sectional views of a thin film transistor in each manufacturing process of a thin film transistor according to a preferred embodiment of the present invention.
  • Fig. 8(a) is a schematic cross-sectional view of the thin film transistor shown in Fig. 7 taken along the A-A direction.
  • Fig. 8(b) is a plan view of the thin film transistor shown in Fig. 7.
  • Fig. 16 is a plan view showing the process of manufacturing the thin film transistor shown in Fig. 15.
  • FIG. 1 is a flow chart of a method for fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • the manufacturing method of the thin film transistor (TFT) 1 includes the following steps.
  • a substrate 100 is provided.
  • the substrate 100 is a glass substrate. It can be understood that in other embodiments, the substrate 100 is not limited to a glass substrate.
  • Step S102 forming a first metal layer 120 on one surface of the substrate 100.
  • This embodiment is formed in the middle of the surface of the substrate 100.
  • the first metal layer 120 serves as a gate of the thin film transistor 10.
  • the substrate 100 includes a first surface a and a second surface b opposite to the second surface a.
  • the first metal layer 120 is formed in a middle portion of the first surface a of the substrate 100 to serve as a gate of the thin film transistor 10 .
  • the first metal layer 120 is formed in the middle of the second surface b of the substrate 100 to serve as a gate of the thin film transistor 10.
  • the material of the first metal layer 120 is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the manufacturing method of the thin film transistor 10 further includes the step of forming a buffer layer (not shown) on the substrate 100.
  • the buffer layer is used to buffer stress that the substrate 100 is subjected to during the process of manufacturing the thin film transistor 10 to avoid damage or cracking of the substrate 100.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the first metal layer 120 is disposed in the middle of one surface of the substrate 100 through the buffer layer.
  • the buffer layer is disposed on one surface of the substrate 100 and is stacked with the substrate 100, and the first metal layer 120 is disposed at a middle portion of the surface of the buffer layer.
  • Step S103 forming a gate insulating layer 130, a semiconductor layer 140, and a second metal layer 150 on the surface of the substrate 100 on which the first metal layer 120 is formed and the first metal layer 120.
  • the gate insulating layer 130 The semiconductor layer 140 and the second metal layer 150 are stacked in this order.
  • the gate insulating layer 130 is disposed adjacent to the surface of the substrate 100 on which the first metal layer 120 is disposed adjacent to the semiconductor layer 140 and the second metal layer 150 and the first metal layer 120.
  • the gate insulating layer 130 is formed on the surface of the 120 and the first metal layer 120.
  • the material of the gate insulating layer 130 is selected from one of silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the semiconductor layer 140 is formed on the gate insulating layer 130 , and the semiconductor layer 140 is stacked on the gate insulating layer 130 . Forming on the semiconductor layer 140 In the second metal layer 150, the second metal layer 150 and the semiconductor layer 140 and the gate insulating layer 130 are sequentially stacked.
  • the material of the second metal layer 150 is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the semiconductor layer 140 is used to form a channel that is turned on or off between the source and the drain of the thin film transistor 10.
  • the semiconductor layer 140 includes a channel layer (not shown) and an ohmic contact layer (not shown). Then, in step S103, a gate insulating layer 130, a semiconductor layer 140, and a second metal layer 150 are formed on the surface of the substrate 100 on which the first metal layer 120 is formed and the first metal layer 120. The gate insulating layer 130, the semiconductor layer 140, and the second metal layer 150 are sequentially stacked. The gate insulating layer 130 is disposed adjacent to the semiconductor layer 140 and the second metal layer 150. The surface of the substrate 100 of a metal layer 120 and the first metal layer 120 are disposed to include the following steps.
  • step I the gate insulating layer 130 is formed on a surface of the substrate 100 on which the first metal layer 120 is formed and the first metal layer 120.
  • step II the channel layer and the ohmic contact layer are sequentially formed on the gate insulating layer 130 as the semiconductor layer 140.
  • Step III forming the second metal layer 150 on the ohmic contact layer.
  • the channel layer is a channel that is turned on or off between a source and a drain of the thin film transistor 10.
  • the ohmic contact layer may reduce contact resistance between the channel layer and the second metal layer 150.
  • the material of the channel layer is polysilicon, and the material of the ohmic contact layer is n-type heavily doped amorphous silicon.
  • a photoresist layer 160 is formed on the second metal layer 150.
  • the photoresist layer 160 includes a first portion 161 and a second portion 162 at opposite edges of the first portion 161.
  • the width of the first portion 161 is the same as the width of the second metal 150 layer and is superimposed on On the second metal layer 150, the second portion 162 extends from the edge of the first portion 161, and the width of the photoresist layer 160 is greater than the width of the second metal layer 150.
  • the photoresist layer 160 finally formed is compared with the prior art, on the premise that the first portion 161 of the photoresist layer 160 is the same size as the photoresist layer in the prior art, due to the photoresist layer 160.
  • There is a second part 162 The width of the finally formed photoresist layer 160 is made larger than that of the prior art photoresist layer.
  • the width of the second portion 162 is greater than 0.5 um.
  • Step S105 patterning the photoresist layer 160 to leak out an edge portion of the second metal layer 150.
  • the patterned photoresist layer 160 includes a semi-transmissive region 163 and an edge region 164, and the width of the semi-transmissive region 163 and the edge region 164 is greater than the width of the semi-transmissive region and the edge region in the prior art.
  • FIG. 9 Please refer to FIG. 9 together to provide a photomask 200 and a light source (not shown) disposed on a side of the photomask 200 away from the photoresist layer 160.
  • the light source is for generating light that is incident from a surface of the reticle 200 remote from the photoresist layer 160.
  • the reticle 200 is disposed above the photoresist layer 160.
  • the reticle 200 includes three transparent portions 210 and two light blocking portions 220.
  • the light-transmitting portion 210 is disposed at both ends and the middle of the mask 200 such that the light-transmitting portion 210 and the light-shielding portion 220 are sequentially spaced apart.
  • the light transmitting portion 210 When light is incident on the light transmitting portion 210, the light can be irradiated onto the photoresist layer 160 through the light transmitting portion 210, when light is irradiated onto the light blocking portion 220, Light cannot be irradiated onto the photoresist layer 160 through the light shielding portion 220.
  • the photoresist material of the photoresist layer 160 is a negative photoresist, that is, the photoresist layer 160 irradiated by the light is not dissolved, and the photoresist layer 160 not irradiated with the light is dissolved. Therefore, when the photomask 200 is placed over the photoresist layer 160, the photoresist layer 160 under the light transmissive portion 210 of the photomask 200 is insoluble; and is located under the light shielding portion 220 of the photomask 200. The photoresist layer 160 dissolves. After passing through the reticle 200, the photoresist layer 160 is patterned into a pattern as shown in FIG.
  • the edge portion of the second metal layer 150 is leaked out, and the corresponding photoresist layer 160 under the transparent portion 210 of the mask 200 is partially dissolved to form the semi-transmissive region 163 of the photoresist layer 160.
  • the corresponding photoresist layer under the light shielding portion 220 of the photomask 200 is insoluble, and thus the edge region 164 of the photoresist layer 160 is formed.
  • the light source passes through the reticle 200 after the exposure process to make the periphery of the semi-transmissive region 16 and the second region around the edge region 164.
  • the portion 162 absorbs the diffracted light around the semi-transmissive region 163 to prevent the residual film value of the semi-transmissive region from decreasing, thereby improving the prior art in which the residual film value of the semi-transmissive region is low.
  • the semiconductor between the source and the drain is punctured The problem of abnormality is defined, which in turn increases the manufacturing yield of the thin film transistor 10.
  • Step S106 patterning the second metal layer 150 and the semiconductor layer 140 to form a channel 180 to define a source and a drain, wherein the length of the channel is longer than the width of the second metal layer 150.
  • the step 106 includes the following steps.
  • the second metal layer 150 not covered with the photoresist layer 160 is removed.
  • the semiconductor layer 140 not covered with the second metal layer 150 is removed.
  • the semi-transmissive region 163 of the photoresist layer 160 and the second portion 161 of the edge of the semi-transmissive region 163 are removed.
  • the original photoresist is removed.
  • a second metal layer 150 covered by the semi-transmissive region 163 of the layer 160; referring to FIG. 14, a portion of the semiconductor layer 140 covered by the semi-transmissive region 163 of the photoresist layer 160 is removed, and finally formed.
  • the source region 151 and the drain region 152 and the channel 180 form a length of the channel 180 longer than a width of the second metal layer 150, that is, a length of the channel 180 and the photoresist layer 160.
  • the width H is the same (see Figure 16).
  • the edge region 164 of the photoresist layer 160 is removed, and the source 151 and the drain 152 of the thin film transistor 10 are formed through the steps of FIGS. 10 to 15 described above.
  • step S106, patterning the second metal layer 150 and the semiconductor layer 140 to define a source and a drain includes : patterning the second metal layer 150, the ohmic contact level of the channel layer to define the source 151 and the drain 152.
  • a passivation layer 170 is formed. Referring to FIG. 18, the passivation layer 170 is disposed on the gate insulating layer 130, the source 151, the drain 152, and the source 151 and the drain that do not cover the semiconductor layer 140. On the semiconductor layer 140 between the poles 152.
  • step S108 a first through hole 171 and a second through hole 172 are defined in the passivation layer 170 corresponding to the source 151 and the drain 152. Please refer to FIG. 19 together.
  • Step S109 a first electrode 181 is disposed corresponding to the first through hole 171, and a second electrode 182 is disposed corresponding to the second through hole 172.
  • the first electrode 181 and the second electrode 182 are respectively connected to the source. 151 and the drain 152. Referring to FIG. 18, the first electrode 181 is connected to the source 151 through the first through hole 171, and the second electrode 182 is connected to the sixth stage 152 through the second through hole 172. .
  • the first electrode 181 and the second electrode 182 are respectively used as TFTs.
  • the source 151 and the drain 152 are pinned to be electrically connected to other components.

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Abstract

本发明提供一种薄膜晶体管的制造方法，包括提供一基板；在所述基板的一个表面的中部形成第一金属层；在形成所述第一金属层的基板的表面及所述第一金属层上形成栅极绝缘层、半导体层及第二金属层，在所述第二金属层上形成光阻层，光阻层包括第一部分及位于第一部分相对两边缘的第二部分，所述第一部分的宽度与所述第二金属层宽度相同并叠加于所述第二金属层上，所述第二部分由所述第一部分边缘延伸，进而所述第二部分使所述光阻层宽度尺寸大于所述源极和漏极之间的通道的长度尺寸；图案化所述光阻层，以露出所述第二金属层的边缘部分，图案化所述第二金属层及所述半导体层形成所述通道，以定义源极及漏极。

Description

薄膜晶体管的制造方法
本发明要求2014年11月20日递交的发明名称为“薄膜晶体管的制造方法”的申请号201410667352.2的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及薄膜晶体管的制造领域，尤其涉及一种具有较高良率的薄膜晶体管的制造方法。
背景技术
薄膜晶体管(thin film transistor，TFT)作为一种开关元件被广泛地应用在液晶显示装置等电子装置中。然而，薄膜晶体管在制造源极(source)和漏极(drain)的时候，先形成一层金属层再在金属层上铺设光阻层，通过在光罩上设计图案，光罩有全透光区，不透光区和半透光区的图案，这样光线透过光罩后全透光区，不透光区和半透光区的透光量不一样，光阻感受到的光量不一样，铺设的光阻形成不同的残膜量，对于正性光阻而言，全透光区不存在光阻，不透光区的光阻膜厚最厚，而半透光区的光阻残膜剩余一半左右。通过光阻的残留来保护金属，这样在蚀刻金属时，金属受到光阻的保护会保留下来。而在薄膜晶体管(thin film transistor，TFT)四道工艺中，沟道区域是通过光罩的半透光区形成一半厚度左右的光阻残膜形成的。但沟道这部分半透光区域通常设计比较小，受到光的衍射影响，需要形成沟道区域的光阻层光线较强而使光阻膜偏薄。即，经过曝光之后的光阻层的残膜值偏低。偏低的残膜值会造成薄膜晶体管在形成的源极和漏极时的设计异常，源极和漏极的异常会导致薄膜晶体管无法正常的工作，从而造成薄膜晶体管的良率较低。
发明内容
本发明提供一种薄膜晶体管的制造方法，能够改善薄膜晶体管在制造的时候经过曝光之后的光阻层的残膜值偏低的情况，从而提高薄膜晶体管的良率。
一种薄膜晶体管的制造方法，所述薄膜晶体管的制造方法包括：
提供一基板；
在所述基板的一个表面形成第一金属层，所述第一金属层为所述薄膜晶体管的栅极；
在形成所述第一金属层的基板的表面及所述第一金属层上形成栅极绝缘层、半导体层及第二金属层，所述栅极绝缘层、所述半导体层及所述第二金属层依次层叠设置；其中所述半导体层用于形成所述薄膜晶体管的源极和漏极之间导通或者断开的通道；
在所述第二金属层上形成光阻层，其中，光阻层包括第一部分及位于第一部分相对两边缘的第二部分，所述第一部分的宽度与所述第二金属层宽度相同并叠加于所述第二金属层上，所述第二部分由所述第一部分宽度方向的边缘延伸，进而所述光阻层的宽度大于所述第二金属层的宽度；
图案化所述光阻层，以露出所述第二金属层的边缘部分，其中图案化后的所述光阻层包括半透光区域及边缘区域；
图案化所述第二金属层及所述半导体层形成所述通道，以定义源极及漏极，其中所述通道的长度长于所述第二金属层的宽度。
其中，在所述“在形成所述第一金属层的基板的表面及所述第一金属层上形成栅极绝缘层、半导体层及第二金属层，所述栅极绝缘层、所述半导体层及所述第二金属层依次层叠设置”步骤中包括：
在形成所述第一金属层的基板的表面及所述第一金属层上形成栅极绝缘层；
在所述栅极绝缘层上依次形成沟道层及欧姆接触层作为所述半导体层；
在所述欧姆接触层上形成所述第二金属层。
其中，所述步骤“图案化所述第二金属层及所述半导体层形成所述通道，以定义所述源极和漏极”包括：
图案化所述第二金属层；
移除所述半透光区域所覆盖的部分第二金属层、部分所述欧姆接触层及所述沟道层，以定义所述源极和漏极；
移除所述光阻层半透光区域。
其中，所述沟道层的材质为多晶硅，所述欧姆接触层的材质为n型重掺杂的非晶硅。
其中，在所述步骤“提供一基板”与所述步骤“在所述基板的一个表面的中部形成第一金属层，所述第一金属层为所述薄膜晶体管的栅极”之间还包括步骤：
在所述基板上形成缓冲层；
所述步骤“在所述基板的一个表面的中部形成第一金属层，所述第一金属层为所述薄膜晶体管的栅极”具体为所述第一金属层通过所述缓冲层设置于所述基板的一个表面的中部。
其中，所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
其中，所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一，所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
其中，在所述步骤“图案化所述第二金属层及所述半导体层形成所述通道，以定义源极及漏极”包括：
移除未覆盖有所述光阻层的所述第二金属层；
移除未覆盖有所述第二金属层的所述半导体层；
移除所述半透光区域所覆盖的部分第二金属层及部分半导体层，形成通道；
移除所述光阻层。
其中，在所述步骤“定义源极及漏极”之后，所述薄膜晶体管的制造方法还包括：
形成钝化层；
在所述钝化层对应所述源极及所述漏极开设第一贯孔及第二贯孔；
对应所述第一贯孔设置第一电极，对应所述第二贯孔设置第二电极，所述第一电极及所述第二电极分别连接所述源极及所述漏极。
其中，在所述第二金属层上形成光阻层时，使所述光阻层的的第二部分宽度尺寸为大于0.5um。
本发明的薄膜晶体管的制造方法自所述光源发出的光线经过所述光罩后 残留下来的光阻层形成的半透光区域的宽度比现有技术中的光阻层经过光罩后残留下来的光阻层形成的半透光区域的宽度大；在曝光过程中光源经过所述光罩之后使得所述半透光区域的第二部分吸收半透光区域周围的衍射光，避免沟道区域的残膜值减小，从而能够改善现有技术中由于半透光区域的残膜值偏低造成所述薄膜晶体管的源极(source)和漏极(drain)之间的半导体被戳穿，产生定义异常的问题，进而提高所述薄膜晶体管的制造良率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的制造方法的流程图。
图2至图7以及图9至图15、17-19为本发明较佳实施方式的薄膜晶体管的各个制造流程中薄膜晶体管的剖面图。
图8(a)为图7所示的薄膜晶体管沿着A-A方向的剖面示意图。
图8(b)为图7所示的薄膜晶体管的俯视图。
图16为图15所示的薄膜晶体管制作过程中的俯视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，其为本发明一较佳实施方式的薄膜晶体管的制造方法的流程图。所述薄膜晶体管(thin film transistor，TFT)1的制造方法包括如下步骤。
步骤S101，提供一基板100。请一并参阅图2，在本实施方式中，所述基板100为一玻璃基板。可以理解地，在其他实施方式中，所述基板100并不仅限于为玻璃基板。
步骤S102，在所述基板100的一个表面的形成第一金属层120，本实施例在基板100表面中部形成。所述第一金属层120作为所述薄膜晶体管10的栅极(gate)。请一并参阅图3，所述基板100包括第一表面a及与所述第二表面a相对的第二表面b。在本实施方式中，所述基板100的所述第一表面a的中部形成所述第一金属层120，以作为所述薄膜晶体管10的栅极。在另一实施方式中，所述基板100的所述第二表面b的中方形成所述第一金属层120，以作为所述薄膜晶体管10的栅极。所述第一金属层120的材质选自铜、钨、铬、铝及其组合的其中之一。
在另一实施方式中，在所述步骤S101之后且在所述步骤S102之前，所述薄膜晶体管10的制造方法还包括以下步骤：在所述基板100上形成一缓冲层(图未示)。所述缓冲层用于缓冲所述基板100在制造所述薄膜晶体管10的过程中受到的应力，以避免所述基板100的损坏或者破裂。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。在此实施方式中，所述“步骤S102，在所述基板100的一个表面的中部形成第一金属层120，所述第一金属层120作为所述薄膜晶体管10的栅极(gate)”具体为：所述第一金属层120通过所述缓冲层设置于所述基板100的一个表面的中部。换句话说，所述缓冲层设置于所述基板100的一个表面，且与所述基板100层叠设置，所述第一金属层120设置于所述缓冲层的表面的中部。
步骤S103，在形成所述第一金属层120的基板100的表面及所述第一金属层120上形成栅极绝缘层130、半导体层140及第二金属层150，所述栅极绝缘层130、所述半导体层140及所述第二金属层150依次层叠设置。所述栅极绝缘层130相较于所述半导体层140及所述第二金属层150邻近设置所述第一金属层120的基板100的表面及所述第一金属层120设置。
具体地，请一并参阅图4，由于所述第一金属层120形成在所述基板100的所述第一表面a的中部，在所述第一表面a的未覆盖所述第一金属层120的表面及所述第一金属层120上形成所述栅极绝缘层130。所述栅极绝缘层130的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
请一并参阅图5与图6，在所述栅极绝缘层130上形成所述半导体层140，所述半导体层140与所述栅极绝缘层130层叠设置。在所述半导体层140上形 成所述第二金属层150，所述第二金属层150与所述半导体层140及所述栅极绝缘层130依次层叠设置。所述第二金属层150的材质选自铜、钨、铬、铝及其组合的其中之一。其中所述半导体层140用于形成所述薄膜晶体管10的源极和漏极之间导通或者断开的通道。
在另一实施方式中，所述半导体层140包括沟道层(图未示)及欧姆接触层(图未示)。则所述“步骤S103，在形成所述第一金属层120的基板100的表面及所述第一金属层120上形成栅极绝缘层130、半导体层140及第二金属层150，所述栅极绝缘层130、所述半导体层140及所述第二金属层150依次层叠设置。所述栅极绝缘层130相较于所述半导体层140及所述第二金属层150邻近设置所述第一金属层120的基板100的表面及所述第一金属层120设置”包括以下步骤。
步骤I，在形成所述第一金属层120的所述基板100的表面及所述第一金属层120上形成所述栅极绝缘层130。
步骤II，在所述栅极绝缘层130上依次形成所述沟道层及所述欧姆接触层作为所述半导体层140。
步骤III，在所述欧姆接触层上形成所述第二金属层150。所述沟道层为所述薄膜晶体管10的源极和漏极之间导通或者断开的通道。所述欧姆接触层可以减小所述沟道层与所述第二金属层150之间的接触电阻。所述沟道层的材质为多晶硅，所述欧姆接触层的材质为n型重掺杂的非晶硅。
请一并参阅图7，步骤S104，在所述第二金属层150上形成光阻层160。在本实施方式中，其中，光阻层160包括第一部分161及位于第一部分161相对两边缘的第二部分162，所述第一部分161的宽度与所述第二金属150层宽度相同并叠加于所述第二金属层150上，所述第二部分162由所述第一部分161边缘延伸，进而所述光阻层160的宽度大于所述第二金属层150的宽度。
请参阅图8(a-b)，由于所述所述第一部分161边缘延伸有第二部分162使所述光阻层160宽度H尺寸大于最终薄膜晶体管的第二金属层150的宽度尺寸L，请参阅图14(第二金属层150的宽度尺寸为预设值)。因此，最终形成的所述光阻层160相较于现有技术，在所述光阻层160第一部分161同现有技术中光阻层尺寸相同的前提下，由于在所述光阻层160设有第二部分162， 使得最终形成的光阻层160整体的宽比现有技术中光阻层的宽度大。第二部分162的宽度大于0.5um。
步骤S105，图案化所述光阻层160，以漏出所述第二金属层150的边缘部分。图案化后的所述光阻层160包括半透光区域163及边缘区域164，并且半透光区域163及边缘区域164的宽度大于现有技术中半透光区域及边缘区域的宽度。
具体地，在本实施方式中，请一并参阅图9，提供一光罩200及设置在所述光罩200远离所述光阻层160一侧的光源(图未示)。所述光源用于产生光线，所述光线自所述光罩200远离所述光阻层160的表面入射。所述光罩200设置于所述光阻层160的上方，所述光罩200包括三个透光部210及两个遮光部220。所述光罩200的两端及中间均为透光部210，以使得所述透光部210及所述遮光部220依次间隔设置。当有光线照射到所述透光部210上时，所述光线能够通过所述透光部210照射到所述光阻层160上，当有光线照射到所述遮光部220上时，所述光线不能通过所述遮光部220照射至所述光阻层160上。
在本实施方式中，所述光阻层160的光阻材料为负光阻，即被光线照射到的光阻层160不溶解，没有被光线照射到的光阻层160溶解。因此，所述光罩200放置于所述光阻层160的上方时，位于所述光罩200的透光部210下方的光阻层160不溶解；位于所述光罩200的遮光部220下方的光阻层160溶解。经过所述光罩200后，所述光阻层160被图案化成如图9所示的图案。漏出所述第二金属层150的边缘部分，且所述光罩200的中间的透光部210下方对应的光阻层160部分溶解以形成所述光阻层160的所述半透光区域163，所述光罩200的遮光部220下方对应的光阻层不溶解，因此形成了所述光阻层160的边缘区域164。
由于所述光阻层160的宽度大于现有技术中的光阻层宽度，在上述曝光过程中光源经过所述光罩200之后使得所述半透光区域16周围以及边缘区域164周围的第二部分162吸收半透光区域163周围的衍射光，避免半透光区域的残膜值减小，从而能够改善现有技术中由于半透光区域的残膜值偏低造成所述薄膜晶体管10的源极(source)和漏极(drain)之间的半导体被戳穿，产 生定义异常的问题，进而提高所述薄膜晶体管10的制造良率。
步骤S106，图案化所述第二金属层150及所述半导体层140形成通道180以定义源极及漏极，其中所述通道的长度长于所述第二金属层150的宽度。具体地，所述步骤106包括以下步骤。
请一并参阅图10，移除未覆盖有所述光阻层160的所述第二金属层150。
请一并参阅图11，移除未覆盖有所述第二金属层150的所述半导体层140。
请一并参阅图12，移除所述光阻层160的所述半透光区域163及半透光区域163边缘的第二部分161；请一并参阅图13，移除原来所述光阻层160的所述半透光区域163所覆盖的第二金属层150；请参阅图14，移除原来所述光阻层160的所述半透光区域163覆盖的部分半导体层140，最后形成源极区151及漏极区152以及所述通道180，形成所述通道180的长度长于所述第二金属层150的宽度，也就是说所述通道180的长度与所述光阻层160的宽度H相同(请参阅图16)。
请参阅图17，移除所述光阻层160的所述边缘区域164，经过上述图10至图15的各个步骤，形成了所述薄膜晶体管10的源极151及漏极152。
当所述半导体层包括所述沟道层及所述欧姆接触层时，则所述“步骤S106，图案化所述第二金属层150及所述半导体层140以定义源极及漏极”包括：图案化所述第二金属层150、所述欧姆接触层级所述沟道层以定义所述源极151及所述漏极152。
步骤S107，形成钝化层170。请参阅图18，所述钝化层170设置在未覆盖所述半导体层140的栅极绝缘层130、所述源极151、所述漏极152，以及位于所述源极151及所述漏极152之间的半导体层140上。
步骤S108，在所述钝化层170上对应所述源极151及所述漏极152开设第一贯孔171及第二贯孔172，请一并参阅图19。
步骤S109，对应所述第一贯孔171设置第一电极181，对应所述第二贯孔172设置第二电极182，所述第一电极181及所述第二电极182分别连接所述源极151及所述漏极152。请一并参阅图18，所述第一电极181通过所述第一贯孔171与所述源极151连接，所述第二电极182通过所述第二贯孔172于所述六级152连接。所述第一电极181及所述第二电极182分别作为TFT的所 述源极151及所述漏极152的引脚，以便与其他元件电连接。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管的制造方法，其特征在于，所述薄膜晶体管的制造方法包括：
    提供一基板；
    在所述基板的一个表面形成第一金属层，所述第一金属层为所述薄膜晶体管的栅极；
    在形成所述第一金属层的基板的表面及所述第一金属层上形成栅极绝缘层、半导体层及第二金属层，所述栅极绝缘层、所述半导体层及所述第二金属层依次层叠设置；其中所述半导体层用于形成所述薄膜晶体管的源极和漏极之间导通或者断开的通道；
    在所述第二金属层上形成光阻层，其中，光阻层包括第一部分及位于第一部分相对两边缘的第二部分，所述第一部分的宽度与所述第二金属层宽度相同并叠加于所述第二金属层上，所述第二部分由所述第一部分宽度方向的边缘延伸，进而所述光阻层的宽度大于所述第二金属层的宽度；
    图案化所述光阻层，以露出所述第二金属层的边缘部分，其中图案化后的所述光阻层包括半透光区域及边缘区域；
    图案化所述第二金属层及所述半导体层形成所述通道，以定义源极及漏极，其中所述通道的长度长于所述第二金属层的宽度。
  2. 如权利要求1所述的薄膜晶体管的制造方法，其特征在于，在所述“在形成所述第一金属层的基板的表面及所述第一金属层上形成栅极绝缘层、半导体层及第二金属层，所述栅极绝缘层、所述半导体层及所述第二金属层依次层叠设置”步骤中包括：
    在形成所述第一金属层的基板的表面及所述第一金属层上形成栅极绝缘层；
    在所述栅极绝缘层上依次形成沟道层及欧姆接触层作为所述半导体层；
    在所述欧姆接触层上形成所述第二金属层。
  3. 如权利要求2所述的薄膜晶体管的制造方法，其特征在于，所述步骤“图案化所述第二金属层及所述半导体层形成所述通道，以定义所述源极和漏 极”包括：
    图案化所述第二金属层；
    移除所述半透光区域所覆盖的部分第二金属层、部分所述欧姆接触层及所述沟道层，以定义所述源极和漏极；
    移除所述光阻层半透光区域。
  4. 如权利要求2所述的薄膜晶体管的制造方法，其特征在于，所述沟道层的材质为多晶硅，所述欧姆接触层的材质为n型重掺杂的非晶硅。
  5. 如权利要求1所述的薄膜晶体管的制造方法，其特征在于，在所述步骤“提供一基板”与所述步骤“在所述基板的一个表面的中部形成第一金属层，所述第一金属层为所述薄膜晶体管的栅极”之间还包括步骤：
    在所述基板上形成缓冲层；
    所述步骤“在所述基板的一个表面的中部形成第一金属层，所述第一金属层为所述薄膜晶体管的栅极”具体为所述第一金属层通过所述缓冲层设置于所述基板的一个表面的中部。
  6. 如权利要求5所述的薄膜晶体管的制造方法，其特征在于，所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
  7. 如权利要求1所述的薄膜晶体管的制造方法，其特征在于，所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一，所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
  8. 如权利要求1所述的薄膜晶体管的制造方法，其特征在于，在所述步骤“图案化所述第二金属层及所述半导体层形成所述通道，以定义源极及漏极”包括：
    移除未覆盖有所述光阻层的所述第二金属层；
    移除未覆盖有所述第二金属层的所述半导体层；
    移除所述半透光区域所覆盖的部分第二金属层及部分半导体层，形成通道；
    移除所述光阻层。
  9. 如权利要求1所述的薄膜晶体管的制造方法，其特征在于，在所述步骤“定义源极及漏极”之后，所述薄膜晶体管的制造方法还包括：
    形成钝化层；
    在所述钝化层对应所述源极及所述漏极开设第一贯孔及第二贯孔；
    对应所述第一贯孔设置第一电极，对应所述第二贯孔设置第二电极，所述第一电极及所述第二电极分别连接所述源极及所述漏极。
  10. 如权利要求1所述的薄膜晶体管的制造方法，其特征在于，在所述第二金属层上形成光阻层时，使所述光阻层的的第二部分宽度尺寸为大于0.5um。
PCT/CN2014/092778 2014-11-20 2014-12-02 薄膜晶体管的制造方法 WO2016078134A1 (zh)

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