CN105070724A - Tft基板的制作方法及制得的tft基板 - Google Patents
Tft基板的制作方法及制得的tft基板 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 102
- 238000000034 method Methods 0.000 claims abstract description 60
- 238000002425 crystallisation Methods 0.000 claims abstract description 13
- 239000007790 solid phase Substances 0.000 claims abstract description 12
- 230000008025 crystallization Effects 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 160
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 37
- 229920005591 polysilicon Polymers 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 28
- 239000004411 aluminium Substances 0.000 claims description 28
- 229910052782 aluminium Inorganic materials 0.000 claims description 28
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 239000011248 coating agent Substances 0.000 claims description 25
- 238000000576 coating method Methods 0.000 claims description 25
- 239000012212 insulator Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 239000002356 single layer Substances 0.000 claims description 16
- 229910052750 molybdenum Inorganic materials 0.000 claims description 14
- 239000011733 molybdenum Substances 0.000 claims description 14
- 239000011521 glass Substances 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 6
- -1 boron ion Chemical class 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 6
- 238000007715 excimer laser crystallization Methods 0.000 abstract description 3
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 239000010409 thin film Substances 0.000 description 8
- 238000005224 laser annealing Methods 0.000 description 4
- 238000005265 energy consumption Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Abstract
本发明提供一种TFT基板的制作方法及制得的TFT基板,该方法采用固相结晶技术制备低温多晶硅层,与准分子激光晶化技术相比,更加节省成本,并且形成的晶粒均一性更好;同时引入双栅极结构,加强了栅极对沟道的控制,增大薄膜晶体管的开电流,减小关电流,抑制翘曲效应,降低阈值电压和亚阈值斜率,提高薄膜晶体管的驱动能力,同时顶栅极还可以起到遮光作用,减少沟道光致漏电现象的发生。本发明提供的一种TFT基板,其低温多晶硅层采用固相结晶方法制备,生产成本较低,并且该TFT基板还具有双栅极结构,使得薄膜晶体管的电性较好,驱动能力强,且不容易发生沟道光致漏电现象。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种TFT基板的制作方法及制得的TFT基板。
背景技术
随着平板显示的发展,高分辨率,低能耗的面板需求不断被提出。低温多晶硅(LowTemperaturePoly-Silicon,LTPS)由于具有较高的电子迁移率,而在液晶显示器(LiquidCrystalDisplay,LCD)与有机发光二极管显示器(OrganicLightEmittingDiode,OLED)技术中得到了业界的重视,被视为实现低成本全彩平板显示的重要材料。对平板显示而言,低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点,而且低温多晶硅可在低温下制作,并可用于制作C-MOS(ComplementaryMetalOxideSemiconductor,互补金属氧化物半导体)电路,因而被广泛研究,用以达到面板高分辨率,低能耗的需求。
在多晶硅技术发展的初期,为了将玻璃基板从非晶硅结构转变为多晶硅结构,就必须借助一道激光退火(LaserAnneal)的高温氧化工序,制得高温多晶硅(HighTemperaturePoly-Silicon,HTPS),此时玻璃基板的温度将超过摄氏1000度。与传统的高温多晶硅相比,低温多晶硅虽然也需要激光照射,但它一般采用的是准分子激光作为热源,激光经过透射系统后,会产生能量均匀分布的激光束并被投射于非晶硅结构的玻璃基板上,当非晶硅结构的玻璃基板吸收准分子激光的能量后,就会转变成为多晶硅结构。由于整个处理过程基本是在600摄氏度以下完成,一般普通的玻璃基板均可承受,这就大大降低了制造成本。而除了制造成本降低外,低温多晶硅的优点还体现在:电子迁移速率更快、稳定性更高。
目前制作低温多晶硅的方法主要有:固相结晶(SolidPhaseCrystallization,SPC)、金属诱导结晶(Metal-InducedCrystallization,MIC)、与准分子激光退火(ExcimerLaserAnnealing,ELA)等多种制作方法。其中,ELA是目前使用最为广泛、相对成熟的制作低温多晶硅的方法,该方法的主要过程为:首先在玻璃基板上形成缓冲层,然后在缓冲层上形成非晶硅层,高温去氢,再利用ELA激光束扫描非晶硅进行准分子激光退火,非晶硅吸收激光的能量,在极短的时间内达到高温并变成熔融状态,最后经冷却重结晶形成多晶硅。目前的情况是:通过ELA方法制得的低温多晶硅薄膜晶体管的均一性不佳且成本较高,而采用SPC方法虽然能够降低成本,提高均一性,但其开电流以及亚阈值斜率又不如ELA方法制得的低温多晶硅薄膜晶体管,并且关电流较大,因此驱动能力较差。
发明内容
本发明的目的在于提供一种TFT基板的制作方法,能够在节省生产成本的同时增大薄膜晶体管的开电流,减小关电流,抑制翘曲效应,降低阈值电压和亚阈值斜率,并减少沟道光致漏电现象的发生。
本发明的目的还在于提供一种TFT基板,该TFT基板生产成本较低,同时还能够增大薄膜晶体管的开电流,减小关电流,抑制翘曲效应,降低阈值电压和亚阈值斜率,且不容易发生沟道光致漏电现象。
为实现上述目的,本发明提供一种TFT基板的制作方法,包括如下步骤:
步骤1、提供一基板,对所述基板进行清洗与预烘烤后,在所述基板上沉积一缓冲层;
步骤2、在所述缓冲层上沉积第一金属层,并对该第一金属层进行图案化处理,得到底栅极;
步骤3、在所述底栅极、及缓冲层上沉积栅极绝缘层,在所述栅极绝缘层上沉积非晶硅层;
步骤4、对所述非晶硅层进行P型掺杂,得到位于上方的P型掺杂非晶硅层、及位于所述P型掺杂非晶硅层下方的未掺杂非晶硅层;
步骤5、采用固相结晶方法将所述未掺杂非晶硅层、及P型掺杂非晶硅层转化为未掺杂低温多晶硅层、及P型掺杂低温多晶硅层,采用一道光刻制程对所述未掺杂低温多晶硅层、及P型掺杂低温多晶硅层进行图案化处理,形成低温多晶硅岛;
步骤6、在所述低温多晶硅岛、及栅极绝缘层上方沉积第二金属层,在所述低温多晶硅岛的未掺杂低温多晶硅层上定义出对应于所述底栅极上方的沟道区,采用一道光刻制程对该第二金属层、及低温多晶硅岛进行图案化处理,去除位于所述沟道区上方的P型掺杂低温多晶硅层、及第二金属层,从而形成对应所述沟道区两侧的源极与漏极、及第一P型掺杂低温多晶硅层与第二P型掺杂低温多晶硅层;
所述源、漏极分别与所述第一、第二P型掺杂低温多晶硅层相接触;
步骤7、在所述源、漏极、沟道区、及栅极绝缘层上沉积钝化层;
步骤8、在所述钝化层上沉积第三金属层,并对该第三金属层进行图案化处理,得到对应所述底栅极的顶栅极。
所述步骤4中,采用乙硼烷气体对所述非晶硅层进行硼离子掺杂。
所述步骤5中,在固相结晶的过程中,采用快速热退火的方法对所述未掺杂非晶硅层、及P型掺杂非晶硅层进行加热,加热温度为670~730℃,时间为10~30min。
所述步骤2中,所述底栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构;所述底栅极的厚度为1500~2000A;
所述步骤8中,所述顶栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构;所述顶栅极的厚度为1500~2000A。
所述顶栅极与底栅极的大小、厚度、及材料完全相同。
本发明还提供一种TFT基板,包括:基板,设于所述基板上的缓冲层,设于所述缓冲层上的底栅极,设于所述缓冲层及底栅极上的栅极绝缘层,设于所述栅极绝缘层上的低温多晶硅岛,设于所述低温多晶硅岛及栅极绝缘层上的源极与漏极,设于所述源、漏极、低温多晶硅岛及栅极绝缘层上的钝化层,及设于所述钝化层上且对应所述底栅极的顶栅极;
其中,所述低温多晶硅岛包括未掺杂低温多晶硅层及设于所述未掺杂低温多晶硅层上的P型掺杂低温多晶硅层,所述未掺杂低温多晶硅层上设有对应于所述底栅极与顶栅极的沟道区,所述P型掺杂低温多晶硅层包括对应所述沟道区两侧的第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层;所述源、漏极分别与所述第一、第二P型掺杂低温多晶硅层相接触。
所述第一P型掺杂低温多晶硅层、及第二P型掺杂低温多晶硅层中掺入的杂质为硼离子。
所述基板为玻璃基板;所述缓冲层为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。
所述底栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构;所述底栅极的厚度为1500~2000A;
所述顶栅极为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构;所述顶栅极的厚度为1500~2000A。
所述顶栅极与底栅极的大小、厚度、及材料完全相同。
本发明的有益效果:本发明提供一种TFT基板的制作方法及制得的TFT基板,该方法采用固相结晶技术制备低温多晶硅层,与准分子激光晶化技术相比,更加节省成本,并且形成的晶粒均一性更好;同时引入双栅极结构,加强了栅极对沟道的控制,增大薄膜晶体管的开电流,减小关电流,抑制翘曲效应,降低阈值电压和亚阈值斜率,提高薄膜晶体管的驱动能力,同时顶栅极还可以起到遮光作用,减少沟道光致漏电现象的发生。本发明提供的一种TFT基板,其低温多晶硅层采用固相结晶方法制备,生产成本较低,并且该TFT基板还具有双栅极结构,使得薄膜晶体管的电性较好,驱动能力强,且不容易发生沟道光致漏电现象。
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
附图中,
图1为本发明的TFT基板的制作方法的步骤1的示意图;
图2为本发明的TFT基板的制作方法的步骤2的示意图;
图3为本发明的TFT基板的制作方法的步骤3的示意图;
图4为本发明的TFT基板的制作方法的步骤4的示意图;
图5-6为本发明的TFT基板的制作方法的步骤5的示意图;
图7-8为本发明的TFT基板的制作方法的步骤6的示意图;
图9为本发明的TFT基板的制作方法的步骤7的示意图;
图10为本发明的TFT基板的制作方法的步骤8的示意图暨本发明的TFT基板的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
本发明首先提供一种TFT基板的制作方法,包括如下步骤:
步骤1、如图1所示,提供一基板1,对所述基板1进行清洗与预烘烤后,在所述基板1上沉积一缓冲层2。
具体的,所述基板1可以为玻璃基板。
具体的,所述缓冲层2可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的,所述缓冲层2的厚度为500~2000A。
步骤2、如图2所示,在所述缓冲层2上沉积第一金属层,并对该第一金属层进行图案化处理,得到底栅极3。
具体的,所述底栅极3可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的,所述底栅极3的厚度为1500~2000A。
步骤3、如图3所示,在所述底栅极3、及缓冲层2上沉积栅极绝缘层4,在所述栅极绝缘层4上沉积非晶硅层5。
具体的,所述栅极绝缘层4可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的,所述栅极绝缘层4的厚度为500~2000A。
优选的,所述非晶硅层5的厚度为500~2000A。
步骤4、如图4所示,对所述非晶硅层5进行P型掺杂,得到位于上方的P型掺杂非晶硅层52、及位于所述P型掺杂非晶硅层52下方的未掺杂非晶硅层51。
具体的,采用乙硼烷(B2H6)气体对所述非晶硅层5进行硼离子(B+)掺杂。
步骤5、如图5所示,采用固相结晶方法(SPC,SolidPhaseCrystallization,)将所述未掺杂非晶硅层51、及P型掺杂非晶硅层52转化为未掺杂低温多晶硅层61、及P型掺杂低温多晶硅层62,如图6所示,采用一道光刻制程对所述未掺杂低温多晶硅层61、及P型掺杂低温多晶硅层62进行图案化处理,形成低温多晶硅岛6。
具体的,在固相结晶的过程中,采用快速热退火(RTA,RapidThermalAnnealing)的方法对所述未掺杂非晶硅层51、及P型掺杂非晶硅层52进行加热,加热温度为670~730℃,时间为10~30min。
步骤6、如图7所示,在所述低温多晶硅岛6、及栅极绝缘层4上方沉积第二金属层7,如图8所示,在所述低温多晶硅岛6的未掺杂低温多晶硅层61上定义出对应于所述底栅极3上方的沟道区613,采用一道光刻制程对该第二金属层7、及低温多晶硅岛6进行图案化处理,去除位于所述沟道区613上方的P型掺杂低温多晶硅层62、及第二金属层7,从而形成对应所述沟道区613两侧的源极71与漏极72、及第一P型掺杂低温多晶硅层621与第二P型掺杂低温多晶硅层622;
所述源、漏极71、72分别与所述第一、第二P型掺杂低温多晶硅层621、622相接触。
具体的,所述沟道区613的宽度小于所述底栅极3的宽度。
具体的,所述源、漏极71、72可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的,所述源、漏极71、72的厚度为1500~2000A。
步骤7、如图9所示,在所述源、漏极71、72、沟道区613、及栅极绝缘层4上沉积钝化层8。
具体的,所述钝化层8可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的,所述钝化层8的厚度为3000~4000A。
步骤8、如图10所示,在所述钝化层8上沉积第三金属层,并对该第三金属层进行图案化处理,得到对应所述底栅极3的顶栅极9。
具体的,所述顶栅极9可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的,所述顶栅极9的厚度为1500~2000A。
优选的,所述顶栅极9与底栅极3的大小、厚度、及材料完全相同。
请参阅图10,基于上述TFT基板的制作方法,本发明还提供一种采用上述方法制备的TFT基板,包括:基板1,设于所述基板1上的缓冲层2,设于所述缓冲层2上的底栅极3,设于所述缓冲层2及底栅极3上的栅极绝缘层4,设于所述栅极绝缘层4上的低温多晶硅岛6,设于所述低温多晶硅岛6及栅极绝缘层4上的源极71与漏极72,设于所述源、漏极71、72、低温多晶硅岛6及栅极绝缘层4上的钝化层8,及设于所述钝化层8上且对应所述底栅极3的顶栅极9;
其中,所述低温多晶硅岛6包括未掺杂低温多晶硅层61及设于所述未掺杂低温多晶硅层61上的P型掺杂低温多晶硅层62,所述未掺杂低温多晶硅层61上设有对应于所述底栅极3与顶栅极9的沟道区613,所述P型掺杂低温多晶硅层62包括对应所述沟道区613两侧的第一P型掺杂低温多晶硅层621、及第二P型掺杂低温多晶硅层622;所述源、漏极71、72分别与所述第一、第二P型掺杂低温多晶硅层621、622相接触。
具体的,所述基板1可以为玻璃基板。
具体的,所述缓冲层2可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的,所述缓冲层2的厚度为500~2000A。
具体的,所述底栅极3可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的,所述底栅极3的厚度为1500~2000A。
具体的,所述栅极绝缘层4可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的,所述栅极绝缘层4的厚度为500~2000A。
具体的,所述低温多晶硅岛6的厚度为500~2000A。
具体的,所述沟道区613的宽度小于所述底栅极3的宽度。
具体的,所述第一P型掺杂低温多晶硅层621、及第二P型掺杂低温多晶硅层622中掺入的杂质为硼离子(B+)。
具体的,所述源、漏极71、72可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的,所述源、漏极71、72的厚度为1500~2000A。
具体的,所述钝化层8可以为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。优选的,所述钝化层8的厚度为3000~4000A。
具体的,所述顶栅极9可以为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构。优选的,所述顶栅极9的厚度为1500~2000A。
优选的,所述顶栅极9与底栅极3的大小、厚度、及材料完全相同。
综上所述,本发明提供一种TFT基板的制作方法及制得的TFT基板,该方法采用固相结晶技术制备低温多晶硅层,与准分子激光晶化技术相比,更加节省成本,并且形成的晶粒均一性更好;同时引入双栅极结构,加强了栅极对沟道的控制,增大薄膜晶体管的开电流,减小关电流,抑制翘曲效应,降低阈值电压和亚阈值斜率,提高薄膜晶体管的驱动能力,同时顶栅极还可以起到遮光作用,减少沟道光致漏电现象的发生。本发明提供的一种TFT基板,其低温多晶硅层采用固相结晶方法制备,生产成本较低,并且该TFT基板还具有双栅极结构,使得薄膜晶体管的电性较好,驱动能力强,且不容易发生沟道光致漏电现象。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。
Claims (10)
1.一种TFT基板的制作方法,其特征在于,包括如下步骤:
步骤1、提供一基板(1),对所述基板(1)进行清洗与预烘烤后,在所述基板(1)上沉积一缓冲层(2);
步骤2、在所述缓冲层(2)上沉积第一金属层,并对该第一金属层进行图案化处理,得到底栅极(3);
步骤3、在所述底栅极(3)、及缓冲层(2)上沉积栅极绝缘层(4),在所述栅极绝缘层(4)上沉积非晶硅层(5);
步骤4、对所述非晶硅层(5)进行P型掺杂,得到位于上方的P型掺杂非晶硅层(52)、及位于所述P型掺杂非晶硅层(52)下方的未掺杂非晶硅层(51);
步骤5、采用固相结晶方法将所述未掺杂非晶硅层(51)、及P型掺杂非晶硅层(52)转化为未掺杂低温多晶硅层(61)、及P型掺杂低温多晶硅层(62),采用一道光刻制程对所述未掺杂低温多晶硅层(61)、及P型掺杂低温多晶硅层(62)进行图案化处理,形成低温多晶硅岛(6);
步骤6、在所述低温多晶硅岛(6)、及栅极绝缘层(4)上方沉积第二金属层(7),在所述低温多晶硅岛(6)的未掺杂低温多晶硅层(61)上定义出对应于所述底栅极(3)上方的沟道区(613),采用一道光刻制程对该第二金属层(7)、及低温多晶硅岛(6)进行图案化处理,去除位于所述沟道区(613)上方的P型掺杂低温多晶硅层(62)、及第二金属层(7),从而形成对应所述沟道区(613)两侧的源极(71)与漏极(72)、及第一P型掺杂低温多晶硅层(621)与第二P型掺杂低温多晶硅层(622);
所述源、漏极(71、72)分别与所述第一、第二P型掺杂低温多晶硅层(621、622)相接触;
步骤7、在所述源、漏极(71、72)、沟道区(613)、及栅极绝缘层(4)上沉积钝化层(8);
步骤8、在所述钝化层(8)上沉积第三金属层,并对该第三金属层进行图案化处理,得到对应所述底栅极(3)的顶栅极(9)。
2.如权利要求1所述的TFT基板的制作方法,其特征在于,所述步骤4中,采用乙硼烷气体对所述非晶硅层(5)进行硼离子掺杂。
3.如权利要求1所述的TFT基板的制作方法,其特征在于,所述步骤5中,在固相结晶的过程中,采用快速热退火的方法对所述未掺杂非晶硅层(51)、及P型掺杂非晶硅层(52)进行加热,加热温度为670~730℃,时间为10~30min。
4.如权利要求1所述的TFT基板的制作方法,其特征在于,所述步骤2中,所述底栅极(3)为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构;所述底栅极(3)的厚度为1500~2000A;
所述步骤8中,所述顶栅极(9)为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构;所述顶栅极(9)的厚度为1500~2000A。
5.如权利要求4所述的TFT基板的制作方法,其特征在于,所述顶栅极(9)与底栅极(3)的大小、厚度、及材料完全相同。
6.一种TFT基板,其特征在于,包括:基板(1),设于所述基板(1)上的缓冲层(2),设于所述缓冲层(2)上的底栅极(3),设于所述缓冲层(2)及底栅极(3)上的栅极绝缘层(4),设于所述栅极绝缘层(4)上的低温多晶硅岛(6),设于所述低温多晶硅岛(6)及栅极绝缘层(4)上的源极(71)与漏极(72),设于所述源、漏极(71、72)、低温多晶硅岛(6)及栅极绝缘层(4)上的钝化层(8),及设于所述钝化层(8)上且对应所述底栅极(3)的顶栅极(9);
其中,所述低温多晶硅岛(6)包括未掺杂低温多晶硅层(61)及设于所述未掺杂低温多晶硅层(61)上的P型掺杂低温多晶硅层(62),所述未掺杂低温多晶硅层(61)上设有对应于所述底栅极(3)与顶栅极(9)的沟道区(613),所述P型掺杂低温多晶硅层(62)包括对应所述沟道区(613)两侧的第一P型掺杂低温多晶硅层(621)、及第二P型掺杂低温多晶硅层(622);所述源、漏极(71、72)分别与所述第一、第二P型掺杂低温多晶硅层(621、622)相接触。
7.如权利要求6所述的TFT基板,其特征在于,所述第一P型掺杂低温多晶硅层(621)、及第二P型掺杂低温多晶硅层(622)中掺入的杂质为硼离子。
8.如权利要求6所述的TFT基板,其特征在于,所述基板(1)为玻璃基板;所述缓冲层(2)为由氮化硅构成的单层结构、由氧化硅构成的单层结构、或者由氮化硅层和氧化硅层构成的双层结构。
9.如权利要求6所述的TFT基板,其特征在于,所述底栅极(3)为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构;所述底栅极(3)的厚度为1500~2000A;
所述顶栅极(9)为单层铝结构、单层钼结构、或者由两层钼夹设一层铝的三层结构;所述顶栅极(9)的厚度为1500~2000A。
10.如权利要求9所述的TFT基板,其特征在于,所述顶栅极(9)与底栅极(3)的大小、厚度、及材料完全相同。
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