CN103730336A - 定义多晶硅生长方向的方法 - Google Patents
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Abstract
本发明涉及定义多晶硅生长方向的方法。该定义多晶硅生长方向的方法包括:步骤1、在基板上形成缓冲层;步骤2、在该缓冲层上形成规律的石墨烯阵列;步骤3、在形成有该石墨烯阵列的该缓冲层上形成非晶硅薄膜;步骤4、经由准分子镭射退火使该非晶硅薄膜形成多晶硅。本发明定义多晶硅生长方向的方法能够控制多晶硅形成时的生长方向,进而可以提高多晶硅晶粒大小。
Description
技术领域
本发明涉及液晶显示技术领域,尤其涉及一种定义多晶硅生长方向的方法。
背景技术
随着平板显示的发展,高分辨率,低能耗的面板需求不断被提出。不同于非晶硅电子迁移率低,低温多晶硅因可在低温下制作,具有高的电子迁移率及可制作C-MOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)电路而被广泛研究用以达到面板高分辨率,低能耗的需求。
低温多晶硅(Low Temperature Poly-Silicon,LTPS)是多晶硅技术的一个分支。对平板显示器来说,采用多晶硅液晶材料有许多优点,如薄膜电路可以做得更薄更小、功耗更低等。
在多晶硅技术发展的初期,为了将玻璃基板从非晶硅结构(a-Si)转变为多晶硅结构,就必须借助一道镭射退火(Laser Anneal)的高温氧化工序,此时玻璃基板的温度将超过摄氏1000度。与传统的高温多晶硅相比,低温多晶硅虽然也需要激光照射工序,但它采用的是准分子激光作为热源,激光经过透射系统后,会产生能量均匀分布的激光束并被投射于非晶硅结构的玻璃基板上,当非晶硅结构的玻璃基板吸收准分子激光的能量后,就会转变成为多晶硅结构。由于整个处理过程是在摄氏500-600度以下完成,普通的玻璃基板也可承受,这就大大降低了制造成本。而除了制造成本降低外,低温多晶硅技术的优点还体现在:电子迁移速率更快;薄膜电路面积更小;更高的分辨率;结构简单、稳定性更高。
目前制作低温多晶硅的方法包括固相结晶(SPC),金属诱导结晶(MIC)和准分子镭射退火(ELA)几种,其中准分子镭射退火(ELA)是目前使用最为广泛的方法。
ELA制作低温多晶硅的方法是在玻璃上生长一缓冲层,然后生长非晶硅,高温去氢后经过HF预清洗,再利用ELA的镭射扫描非晶硅,非晶硅受到高温熔化重结晶形成多晶硅。
低温多晶硅晶粒的大小(Grain size)对多晶硅的电学性能有重要影响,在ELA制程中,非晶硅受到高温后变成完全熔融(nearly completely melts)状态,然后重结晶形成多晶硅。重结晶时会按照低能量向高能量方向结晶,低温向高温方向结晶;所以结晶的起点和方向是凌乱的,导致晶粒偏小,晶粒间晶界(Grain boundary)偏多,就会影响多晶硅的电子迁移率。
发明内容
因此,本发明的目的在于提供一种定义多晶硅生长方向的方法,能够控制多晶硅形成时的生长方向。
为实现上述目的,本发明提供了一种定义多晶硅生长方向的方法,其包括:
步骤1、在基板上形成缓冲层;
步骤2、在该缓冲层上形成规律的石墨烯阵列;
步骤3、在形成有该石墨烯阵列的该缓冲层上形成非晶硅薄膜;
步骤4、经由准分子镭射退火使该非晶硅薄膜形成多晶硅。
其中,该步骤2包括:
步骤2.1、根据欲形成的石墨烯阵列在该缓冲层上形成图案化的掩膜层;
步骤2.2、通过化学气相沉积法形成该石墨烯阵列;
步骤2.3、除去掩膜层。
其中,该步骤4中进行准分子镭射退火前,对该非晶硅薄膜进行高温去氢处理。
其中,该缓冲层的材料为氮化硅或二氧化硅。
其中,该基板为玻璃。
其中,根据所欲定义的该步骤4中所形成的多晶硅的生长方向来预先设置所述石墨烯阵列在该缓冲层表面的分布。
其中,该缓冲层和非晶硅薄膜分别经由化学气相沉积法形成。
其中,在该基板和该缓冲层之间还形成有绝缘层。
其中,该绝缘层的材料为氮化铝,氮化硼,氧化铝或氧化镁。
其中,该绝缘层通过磁控溅射或化学气相沉积法形成。
本发明定义多晶硅生长方向的方法能够控制多晶硅形成时的生长方向,进而可以提高多晶硅晶粒大小。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其他有益效果显而易见。
附图中,
图1为本发明定义多晶硅生长方向的方法的流程图;
图2为按照本发明定义多晶硅生长方向的方法形成石墨烯阵列的截面图;
图3为按照本发明定义多晶硅生长方向的方法进行准分子镭射退火制程时非晶硅薄膜的截面图;
图4为按照本发明定义多晶硅生长方向的方法在非晶硅薄膜中控制多晶硅生长方向的截面图。
具体实施方式
参见图1,其为本发明定义多晶硅生长方向的方法的流程图。结合图2至图4所示的按照本发明定义多晶硅生长方向的方法生长多晶硅的一较佳实施例,本发明的定义多晶硅生长方向的方法主要包括:
步骤1、在基板10上形成缓冲层20;该基板10可以为玻璃或者其它适合的透明材料。
步骤2、在该缓冲层20上形成规律的石墨烯阵列30;该缓冲层20的材料可以为氮化硅或二氧化硅,或者其它适合的材料。
参见图2,其为按照本发明定义多晶硅生长方向的方法形成石墨烯阵列的截面图,基板10上生长一缓冲层20,然后在缓冲层20上形成规律的石墨烯阵列30,该缓冲层20可以分别经由化学气相沉积法形成,也可以通过其它适合的制程来制作。
该步骤2可以包括:
步骤2.1、根据欲形成的石墨烯阵列30在该缓冲层20上形成图案化的掩膜层;
步骤2.2、通过化学气相沉积法形成该石墨烯阵列30;
步骤2.3、除去掩膜层。
石墨烯阵列30也可以通过其它制程方式来形成。
然后,进行步骤3、在形成有该石墨烯阵列30的该缓冲层20上形成非晶硅薄膜40;以及
步骤4、经由准分子镭射退火使该非晶硅薄膜40形成多晶硅。
参见图3,其为按照本发明定义多晶硅生长方向的方法进行准分子镭射退火制程时非晶硅薄膜的截面图。非晶硅薄膜40可以经由化学气相沉积法形成,也可以通过其它适合的制程来制作。步骤4中进行准分子镭射退火前,可以对该非晶硅薄膜40进行高温去氢处理。
参见图4,其为按照本发明定义多晶硅生长方向的方法在非晶硅薄膜中控制多晶硅生长方向的截面图。
因石墨烯具有优良的导热性,且能耐高温,所以在利用激光扫描进行准分子镭射退火的过程中,非晶硅薄膜40吸收激光的能量后温度升高,在非晶硅薄膜40上产生温度差异,石墨烯阵列30对应的非晶硅区域因石墨烯的优良导热作用,温度相对无石墨烯的区域会偏低,形成如图3所示的低温区;如图4所示,多晶硅形成时即会以低温区为起点开始向四周高温区域生长变大,从而实现控制多晶硅生长方向的目的,进而可以提高多晶硅晶粒大小。
使用本发明的方法,在生长多晶硅前,可以根据所欲定义的所形成的多晶硅的生长方向来预先设置石墨烯阵列30在该缓冲层20表面的分布。例如,石墨烯阵列30可以设置为以相同的形状在缓冲层20表面均匀分布。换句话说,可以通过改变石墨烯阵列30的形状和位置等条件来改变多晶硅形成时的生长方向。
而且,在该基板10和该缓冲层20之间还可以形成有绝缘层。该绝缘层的材料可以为氮化铝,氮化硼,氧化铝或氧化镁,或者其它适合的材料。该绝缘层可以通过磁控溅射或化学气相沉积法或其它适合的制程形成。而且,本发明的定义多晶硅生长方向的方法可以应用于薄膜晶体管,阵列基板,平板显示装置等的制备。
综上所述,本发明定义多晶硅生长方向的方法能够控制多晶硅形成时的生长方向,进而可以提高多晶硅晶粒大小。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (10)
1.一种定义多晶硅生长方向的方法,其特征在于,包括:
步骤1、在基板上形成缓冲层;
步骤2、在该缓冲层上形成规律的石墨烯阵列;
步骤3、在形成有该石墨烯阵列的该缓冲层上形成非晶硅薄膜;
步骤4、经由准分子镭射退火使该非晶硅薄膜形成多晶硅。
2.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该步骤2包括:
步骤2.1、根据欲形成的石墨烯阵列在该缓冲层上形成图案化的掩膜层;
步骤2.2、通过化学气相沉积法形成该石墨烯阵列;
步骤2.3、除去掩膜层。
3.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该步骤4中进行准分子镭射退火前,对该非晶硅薄膜进行高温去氢处理。
4.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该缓冲层的材料为氮化硅或二氧化硅。
5.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该基板为玻璃。
6.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,根据所欲定义的该步骤4中所形成的多晶硅的生长方向来预先设置所述石墨烯阵列在该缓冲层表面的分布。
7.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该缓冲层和非晶硅薄膜分别经由化学气相沉积法形成。
8.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,在该基板和该缓冲层之间还形成有绝缘层。
9.如权利要求8所述的定义多晶硅生长方向的方法,其特征在于,该绝缘层的材料为氮化铝,氮化硼,氧化铝或氧化镁。
10.如权利要求8所述的定义多晶硅生长方向的方法,其特征在于,该绝缘层通过磁控溅射或化学气相沉积法形成。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104966663A (zh) * | 2015-05-22 | 2015-10-07 | 信利(惠州)智能显示有限公司 | 低温多晶硅薄膜及其制备方法、以及薄膜晶体管 |
CN105088336A (zh) * | 2015-07-24 | 2015-11-25 | 深圳市华星光电技术有限公司 | 一种多晶硅制备装置及方法 |
WO2015196521A1 (zh) * | 2014-06-25 | 2015-12-30 | 深圳市华星光电技术有限公司 | 定义多晶硅生长方向的方法 |
WO2016023246A1 (zh) * | 2014-08-15 | 2016-02-18 | 深圳市华星光电技术有限公司 | 低温多晶硅薄膜的制备方法、制备设备及低温多晶硅薄膜 |
WO2018209759A1 (zh) * | 2017-05-17 | 2018-11-22 | 武汉华星光电技术有限公司 | 利用准分子激光退火制作低温多晶硅的系统及其承载装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001060551A (ja) * | 1999-08-19 | 2001-03-06 | Fujitsu Ltd | 半導体装置の製造方法 |
CN1501449A (zh) * | 2002-11-12 | 2004-06-02 | 友达光电股份有限公司 | 多晶硅层的制作方法 |
US20040137671A1 (en) * | 2002-12-31 | 2004-07-15 | Lg. Philips Lcd Co., Ltd. | Method of crystallizing amorphous silicon for use in thin film transistor |
CN1581426A (zh) * | 2003-08-01 | 2005-02-16 | 统宝光电股份有限公司 | 多晶硅层的结晶方法 |
KR20060018533A (ko) * | 2004-08-24 | 2006-03-02 | 삼성에스디아이 주식회사 | 박막트랜지스터 제조 방법 |
CN201151753Y (zh) * | 2007-11-07 | 2008-11-19 | 常州华盛天龙机械有限公司 | 一种石墨导热块 |
CN102856173A (zh) * | 2012-09-29 | 2013-01-02 | 京东方科技集团股份有限公司 | 一种多晶硅薄膜及其制备方法、阵列基板、显示装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103124691B (zh) * | 2010-09-28 | 2016-04-27 | 英派尔科技开发有限公司 | 定向重结晶的石墨烯生长衬底 |
WO2013165620A1 (en) * | 2012-05-04 | 2013-11-07 | Stc.Unm | Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure |
-
2013
- 2013-12-30 CN CN201310746243.5A patent/CN103730336B/zh not_active Expired - Fee Related
-
2014
- 2014-01-23 WO PCT/CN2014/071291 patent/WO2015100827A1/zh active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001060551A (ja) * | 1999-08-19 | 2001-03-06 | Fujitsu Ltd | 半導体装置の製造方法 |
CN1501449A (zh) * | 2002-11-12 | 2004-06-02 | 友达光电股份有限公司 | 多晶硅层的制作方法 |
US20040137671A1 (en) * | 2002-12-31 | 2004-07-15 | Lg. Philips Lcd Co., Ltd. | Method of crystallizing amorphous silicon for use in thin film transistor |
CN1581426A (zh) * | 2003-08-01 | 2005-02-16 | 统宝光电股份有限公司 | 多晶硅层的结晶方法 |
KR20060018533A (ko) * | 2004-08-24 | 2006-03-02 | 삼성에스디아이 주식회사 | 박막트랜지스터 제조 방법 |
CN201151753Y (zh) * | 2007-11-07 | 2008-11-19 | 常州华盛天龙机械有限公司 | 一种石墨导热块 |
CN102856173A (zh) * | 2012-09-29 | 2013-01-02 | 京东方科技集团股份有限公司 | 一种多晶硅薄膜及其制备方法、阵列基板、显示装置 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015196521A1 (zh) * | 2014-06-25 | 2015-12-30 | 深圳市华星光电技术有限公司 | 定义多晶硅生长方向的方法 |
CN104037066B (zh) * | 2014-06-25 | 2017-05-31 | 深圳市华星光电技术有限公司 | 定义多晶硅生长方向的方法 |
WO2016023246A1 (zh) * | 2014-08-15 | 2016-02-18 | 深圳市华星光电技术有限公司 | 低温多晶硅薄膜的制备方法、制备设备及低温多晶硅薄膜 |
CN104966663A (zh) * | 2015-05-22 | 2015-10-07 | 信利(惠州)智能显示有限公司 | 低温多晶硅薄膜及其制备方法、以及薄膜晶体管 |
CN104966663B (zh) * | 2015-05-22 | 2020-01-14 | 信利(惠州)智能显示有限公司 | 低温多晶硅薄膜及其制备方法、以及薄膜晶体管 |
CN105088336A (zh) * | 2015-07-24 | 2015-11-25 | 深圳市华星光电技术有限公司 | 一种多晶硅制备装置及方法 |
CN105088336B (zh) * | 2015-07-24 | 2018-05-18 | 深圳市华星光电技术有限公司 | 一种多晶硅制备装置及方法 |
WO2018209759A1 (zh) * | 2017-05-17 | 2018-11-22 | 武汉华星光电技术有限公司 | 利用准分子激光退火制作低温多晶硅的系统及其承载装置 |
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