WO2015192558A1 - 低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置 - Google Patents

低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置 Download PDF

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WO2015192558A1
WO2015192558A1 PCT/CN2014/088764 CN2014088764W WO2015192558A1 WO 2015192558 A1 WO2015192558 A1 WO 2015192558A1 CN 2014088764 W CN2014088764 W CN 2014088764W WO 2015192558 A1 WO2015192558 A1 WO 2015192558A1
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layer
insulating layer
active layer
thin film
film transistor
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PCT/CN2014/088764
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English (en)
French (fr)
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白妮妮
张琨鹏
康峰
高鹏飞
韩帅
刘宇
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2015192558A1 publication Critical patent/WO2015192558A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • Embodiments of the present invention relate to a low temperature polysilicon thin film transistor, a method of fabricating the same, and an array substrate and display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • Embodiments of the present invention provide a low temperature polysilicon thin film transistor.
  • the low temperature polysilicon thin film transistor includes a substrate, a buffer layer formed on the substrate, an active layer formed on the buffer layer by a patterning process, and an insulating heat insulating layer formed on the active layer.
  • the edges of the active layer are not covered by the insulating insulation layer.
  • the edge width of the active layer not covered by the insulating layer is not more than 1/4 of the width of the active layer.
  • the insulating insulation layer is formed by a spraying process and has a thickness ranging from
  • the material of the insulating insulation layer includes silicon nitride and silicon oxide.
  • the low temperature polysilicon thin film transistor of the present invention further includes a gate insulating layer, a gate electrode, an interlayer insulating layer, and source and drain electrodes sequentially formed over the insulating heat insulating layer, the source electrode And the drain electrode are respectively connected to both ends of the active layer through via holes penetrating through the interlayer insulating layer, the gate insulating layer, and the insulating heat insulating layer.
  • Embodiments of the present invention also provide a method for fabricating a low temperature polysilicon thin film transistor, comprising: providing a substrate on which a buffer layer is formed; forming an active layer on the buffer layer by a patterning process; An insulating thermal insulation layer is formed on the active layer.
  • the edges of the active layer are not covered by the insulating insulation layer.
  • the edge width of the active layer that is not covered by the insulating layer is not more than 1/4 of the width of the active layer.
  • the method further includes depositing a gate insulating layer over the insulating insulating layer; forming a gate metal film over the gate insulating layer, forming a pattern of a gate electrode by a patterning process, and forming the active
  • the regions at both ends of the layer are doped to form an ion doped region;
  • an interlayer insulating layer is formed over the gate electrode, and an insulating layer penetrating through the insulating insulating layer, the gate insulating layer and the interlayer insulating layer is formed by a patterning process a via hole to expose an ion doped region at both ends of the active layer;
  • a source/drain metal film is formed over the interlayer insulating layer, and a source electrode and a drain electrode are formed by a patterning process, the source electrode and the drain electrode respectively
  • the via hole of the insulating layer is connected to the ion doping region at both ends of the active layer.
  • Embodiments of the present invention further provide an array substrate comprising the above-described low temperature polysilicon thin film transistor.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • FIG. 1 is a process flow diagram of forming a polysilicon thin film transistor in accordance with an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a TFT according to an embodiment of the present invention.
  • An organic light emitting display may include an active switch, an insulating layer, a transparent electrode, a light emitting layer, and a metal electrode sequentially formed on a substrate.
  • the active switch is connected to the transparent electrode through the contact hole to control the writing of image data.
  • active switches are usually adopted.
  • a low temperature poly-silicon TFT (LTPS-TFT) is used as the pixel switch control element; and the quality of the low temperature polysilicon film used to prepare the LTPS-TFT is good or bad for the electrical performance of the LTPS-TFT. Direct impact, therefore, the manufacturing technology of low-temperature polysilicon film is also receiving more and more attention.
  • the formation of the active layer is generally performed by depositing a certain thickness of the amorphous silicon layer, and then using a special process to crystallize the amorphous silicon to form polysilicon to improve the active layer.
  • the mobility of the stream is excimer laser crystallization (ELA).
  • the crystallization method is to irradiate the surface of the amorphous silicon film with a high-energy laser of a certain wavelength. After the irradiation, the temperature of the surface of the silicon film rapidly rises to about 1400 ° C, and the amorphous silicon is in a molten state. When the laser energy is withdrawn, the substrate is rapidly cooled, and the amorphous silicon crystallizes to form polysilicon during the cooling process. In this process, the cooling rate of the substrate is too fast, the crystal grains do not have sufficient time to grow, resulting in small grain size, low carrier mobility, slow reaction speed and high power consumption of TFT and semiconductor devices, and product competition. Force can not be improved and other issues.
  • Embodiments of the present invention design an insulating thermal insulation layer for the structure of the LTPS-TFT or the semiconductor device to slow down the cooling rate of the substrate during the ELA process, increase the grain size of the polycrystalline silicon, and improve the electrical performance of the TFT.
  • the low temperature polysilicon thin film transistor includes a substrate 1, and a buffer layer 2, an active layer 3, and an adiabatic thermal insulation layer 4 which are sequentially formed on the substrate.
  • the active layer 3 is formed by a patterning process on the amorphous silicon layer of the low temperature polysilicon thin film transistor. The edge of the active layer 3 not exceeding 1/4 of its width is not covered by the insulating heat insulating layer 4.
  • the low temperature polysilicon thin film transistor of the present embodiment further includes a gate insulating layer 5, a gate electrode 7, an interlayer insulating layer 6, and a source electrode 8 and a drain electrode 9 which are sequentially formed over the insulating heat insulating layer 4.
  • the source electrode 8 and the drain electrode 9 are connected to both ends of the active layer 3 through insulating vias penetrating the interlayer insulating layer 6, the gate insulating layer 5, and the insulating heat insulating layer 4, respectively.
  • a very thin thermal insulation layer 4 is deposited on the active layer 3 to form a specific pattern and then subjected to an ELA process.
  • the role of ELA is to melt the active layer and recrystallize it to form polysilicon.
  • the temperature propagation depth of the ELA can reach 100 nm, and the thickness of the active layer 3 generally does not exceed 50 nm, so adding a very thin thermal insulation layer 4 on the active layer 3 does not affect the ELA process and the active layer 3. Melt recrystallization has an effect.
  • the material of the heat insulating layer 4 satisfies the following basic conditions: small thermal conductivity, high compressive strength, good heat resistance, good adhesion, high stability at normal temperature, etc., and does not adversely affect the active layer at high temperatures, and Easy to prepare in the TFT process.
  • silicon oxide (SiOx), silicon nitride (SiNx), etc. which satisfy the above conditions, can be used as an ideal thermal insulation material.
  • the silicon oxide or silicon nitride material used in this embodiment is used as the material of the heat insulating layer.
  • the thickness of the insulation layer is The insulating thermal insulation layer formed by such materials can meet the design and material requirements, and form large-grain polycrystalline silicon under the corresponding process.
  • the substrate 1 can be selected from a variety of substrates which can be used for the formation of a polysilicon film, such as a glass substrate, a quartz substrate, etc., and the thickness thereof can be a conventional size, or other sizes can be used as needed.
  • the temperature of the molten silicon in the active layer 3 can be prevented from diffusing into the lower substrate 1 and the upper environment, and the crystallization time of the polysilicon is prolonged.
  • the pattern width of the heat insulating layer 4 is slightly smaller than the pattern width of the active layer 3, and during the crystallization process, the cooling rate of the edge of the pattern of the active layer 3 is not covered by the insulating layer 4 Faster, crystallizes to form polycrystalline silicon, and acts as a seed crystal to guide the growth of a portion of the crystal grains covered by the adiabatic thermal insulating layer 4. This method is more conducive to the growth of large-sized crystal grains and improves the mobility of the TFT.
  • the embodiment provides a method for preparing a low temperature polysilicon thin film transistor, comprising:
  • Step 1 A substrate 1 is provided, a buffer layer 2 is formed on the substrate 1, an active layer 3 is formed on the buffer layer 2, and a heat insulating layer 4 is formed on the active layer 3.
  • FIG. 1 For example, a flow chart of the process of forming the active layer 3 is shown in FIG. 1:
  • the buffer layer 2, the active layer 3, and the heat insulating layer 4 are sequentially deposited on the substrate 1 to obtain an initial structure.
  • a photoresist 10 is formed on the heat insulating layer 4.
  • the pattern of the heat insulating layer 4 is formed through etching and stripping processes.
  • the amorphous silicon of the active layer 3 is crystallized to form polycrystalline silicon by a crystallization process (the crystallized active layer 3 is shown in the shaded layered structure in the final structure of Fig. 1).
  • the crystallization process refers to the ELA process to instantly bring the surface temperature of the amorphous silicon layer to 1400 ° C, and the amorphous silicon is melted at a high temperature. After the laser irradiation is finished, As the temperature decreases, the molten amorphous silicon layer recrystallizes to form polysilicon.
  • a glass substrate is selected as the substrate 1, the substrate 1 is pre-cleaned, the buffer layer 2 is deposited by plasma enhanced chemical vapor deposition, the active layer 3 is deposited, and the insulating heat insulating layer 4 is deposited on the surface of the active layer 3.
  • the buffer layer 2 may employ, for example, a two-layer structure of a silicon nitride layer and a silicon dioxide layer, the lower layer is a silicon nitride layer having a thickness of 50 to 150 nm, and the upper layer is a silicon oxide layer having a thickness of 100 to 350 nm.
  • the upper surface of the silicon dioxide layer is an active layer 3 having a thickness of 300 to 600 nm.
  • the thickness of the insulation layer 4 is Made of silicon nitride material.
  • the gate insulating layer 5, the gate electrode 7, the interlayer dielectric layer 6, and the source electrode 8 and the drain electrode 9 are sequentially deposited on the heat insulating layer 4 to form a basic structure of the TFT and the semiconductor device.
  • a gate insulating layer 5 is deposited over the insulating insulating layer 4; a gate metal film is formed over the gate insulating layer 5, a pattern of the gate electrode 7 is formed by a patterning process, and a region at both ends of the active layer 3 is doped Processing to form an ion doped region.
  • An interlayer insulating layer 6 is formed over the gate electrode 7, and an insulating layer via hole penetrating the insulating insulating layer 4, the gate insulating layer 5, and the interlayer insulating layer 6 is formed by a patterning process, thereby exposing the active layer 3 The ion doping region of the end.
  • a source/drain metal film is formed over the interlayer insulating layer 6, and a source electrode 8 and a drain electrode 9 are formed by a patterning process, and the source electrode 8 and the drain electrode 9 are respectively doped with ions at both ends of the active layer 3 through the insulating layer via hole. Miscellaneous area connection.
  • the active layer can be insulated with the buffer layer 2 after the high-energy laser is removed during the crystallization process, thereby greatly reducing the amorphous silicon layer.
  • the cooling rate is such that the crystal grains have sufficient time to grow after formation, and the grain size is increased. For example, a crystal grain having an average particle diameter of about 2 ⁇ m is obtained, and the thin film transistor described in Embodiment 1 can be prepared. .
  • Embodiments of the present invention design an insulating thermal insulation layer for the structure of the LTPS-TFT or the semiconductor device to slow down the cooling rate of the substrate during the ELA process, increase the grain size of the polycrystalline silicon, and improve the electrical performance of the TFT.
  • An embodiment of the present invention is a heat insulating and insulating layer formed with a pattern on an upper surface of an active layer, the insulating layer and the buffer layer respectively suppressing temperature diffusion in the molten silicon on the upper surface and the lower surface of the active layer , plays the role of double-layer insulation, which significantly prolongs the crystallization time of polysilicon.
  • the pattern design of the insulating layer can make the active layer crystallize at the edge of the pattern to form a polycrystalline silicon seed crystal, guide the growth of the molten silicon, contribute to the growth of large-sized crystal grains, and effectively improve the mobility of the TFT.
  • This embodiment provides an array substrate including the low temperature polysilicon thin film transistor described in Embodiment 1.
  • the array substrate thus formed is used in a display back sheet, display reaction speed, power consumption, and the like can be improved.
  • Such a display substrate is suitable for an active matrix organic light emitting diode display (AMOLED), a low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD), and the like.
  • AMOLED active matrix organic light emitting diode display
  • LTPS TFT-LCD low temperature polysilicon thin film transistor liquid crystal display
  • This embodiment provides a display device including the array substrate described in Embodiment 3.
  • the display device of this embodiment may be an active matrix organic light emitting diode display (AMOLED) or a liquid crystal display or the like. Since the low-temperature polysilicon thin film transistor is used in the display device, the electrical performance is greatly improved compared with the amorphous silicon, and the competitiveness of the display device can be improved.
  • AMOLED active matrix organic light emitting diode display
  • the embodiment of the present invention increases the thermal insulation layer on the surface of the active layer, and in the crystallization process of the active layer by the ELA method, when the high-energy laser is evacuated, the thermal insulation layer is
  • the buffer layer can jointly heat the silicon film, greatly reducing the cooling rate, allowing the crystal grains to grow for a sufficient time after formation, increasing the grain size, increasing the carrier mobility, and improving the TFT and the semiconductor device.
  • the response rate reduces power consumption and increases the competitiveness of the product.
  • the method adopted in the embodiment of the invention is easy to operate in the production process, the process is simple and the raw materials are not consumed. By increasing the size of the polycrystalline silicon crystal grains, a low-temperature polysilicon thin film transistor having a good mobility can be obtained.
  • the low-temperature polysilicon film obtained by the method can be used as an active layer of a low-temperature polysilicon thin film transistor, and is suitable for the fields of an active matrix organic light emitting diode display (AMOLED) and a low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD).
  • AMOLED active matrix organic light emitting diode display
  • LTPS TFT-LCD low temperature polysilicon thin film transistor liquid crystal display

Abstract

一种多晶硅薄膜及薄膜晶体管、其制备方法及阵列基板与显示装置。该低温多晶硅薄膜晶体管包括基板（1）、在基板（1）上形成的缓冲层（2），以及通过构图工艺在缓冲层（2）上形成的有源层（3），以及在有源层（3）上形成的绝热保温层（4）。通过在多晶硅薄膜结构中设计绝热保温层（4），该绝热保温层（4）与缓冲层（2）分别在有源层（3）的上表面和下表面起到双层保温的作用，从而明显延长多晶硅晶化的时间。

Description

低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置 技术领域
本发明的实施例涉及一种低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置。
背景技术
随着平面显示器技术的蓬勃发展，有源矩阵式有机发光显示器(AMOLED，Active Matrix Organic Light Emitting Diode)由于其具有更轻薄、自发光和高反应速率等优良特性，成为未来显示器发展的趋势。
发明内容
本发明的实施例提供一种低温多晶硅薄膜晶体管。所述低温多晶硅薄膜晶体管包括基板、在所述基板上形成的缓冲层，通过构图工艺在所述缓冲层上形成的有源层，以及在所述有源层上形成的绝热保温层。
在一个示例中，所述有源层的边缘未被所述绝热保温层覆盖。
未被所述绝热保温层覆盖的所述有源层的边缘宽度为不大于所述有源层宽度的1/4。
在一个示例中，所述绝热保温层通过喷涂工艺形成，其厚度范围为
Figure PCTCN2014088764-appb-000001
在一个示例中，所述绝热保温层的材料包括氮化硅和氧化硅。
在一个示例中，本发明所述的低温多晶硅薄膜晶体管还包括在所述绝热保温层的上方依次形成的栅绝缘层、栅电极、层间绝缘层、以及源电极和漏电极，所述源电极和漏电极分别通过贯穿层间绝缘层、栅绝缘层及绝热保温层的过孔与所述有源层的两端连接。
本发明的实施例还提供了一种用于制备低温多晶硅薄膜晶体管的方法，包括：提供一基板，在所述基板上形成缓冲层；通过构图工艺在所述缓冲层上形成有源层；在所述有源层上形成绝热保温层。
在一个示例中，所述有源层的边缘未被所述绝热保温层覆盖。
在一个示例中，未被所述绝热保温层覆盖的所述有源层的边缘宽度为不大于有源层宽度的1/4。
在一个示例中，所述方法还包括在所述绝热保温层的上方沉积栅绝缘层；在所述栅绝缘层上方形成栅金属薄膜，通过构图工艺形成栅电极的图案，并对所述有源层两端的区域进行掺杂处理以形成离子掺杂区；在所述栅电极上方形成层间绝缘层，并通过构图工艺形成贯穿所述绝热保温层、栅绝缘层和层间绝缘层的绝缘层过孔，从而露出所述有源层两端的离子掺杂区；在所述层间绝缘层上方形成源漏金属薄膜，并通过构图工艺形成源电极和漏电极，所述源电极和漏电极分别通过所述绝缘层过孔与所述有源层两端的离子掺杂区连接。
本发明的实施例进一步提供一种阵列基板，包含上述的低温多晶硅薄膜晶体管。
本发明的实施例还提供了含有上述阵列基板的显示装置。
附图说明
图1为根据本发明的实施例的多晶硅薄膜晶体管形成的工艺流程图；
图2为根据本发明的实施例TFT结构示意图；
具体实施方式
为了更清楚的描述本方案，以下结合具体的实施例对本发明技术方案作详细说明。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其它元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
有机发光显示器(AMOLED)可以包括依次形成在基板上的有源开关、绝缘层、透明电极、发光层和金属电极。有源开关通过接触孔与透明电极连接，以控制图像数据的写入。为适应AMOLED尺寸大型化的发展，有源开关通常采 用低温多晶硅薄膜晶体管(Low Temperature Poly-silicon TFT,简称LTPS-TFT)作为像素开关控制元件；而用于制备LTPS-TFT的低温多晶硅薄膜的品质好坏与否对于LTPS-TFT的电性表现有着直接影响，因此，低温多晶硅薄膜的制造技术也越来越受到重视。
在LTPS-TFT及半导体器件的制备工艺中，有源层的形成一般都是先沉积一定厚度的非晶硅层，然后采用特殊工艺使非晶硅晶化形成多晶硅，以提高有源层中载流子的迁移率。非晶硅晶化技术采用的主要工艺为准分子激光晶化(ELA)。
在ELA工艺中，晶化方法是采用一定波长的高能量的激光照射于非晶硅薄膜表面，经照射后，硅薄膜表面的温度迅速升至1400℃左右，此时非晶硅呈熔融状态，当激光能量撤离后，基板迅速冷却，在冷却过程中非晶硅晶化形成多晶硅。在该过程中，基板的冷却速度过快，晶粒没有足够的时间生长，导致晶粒尺寸较小，载流子迁移率较低，TFT及半导体器件的反应速度慢且功耗高，产品竞争力无法得到提升等问题。
本发明的实施例对LTPS-TFT或半导体器件的结构设计了绝热保温层，以减缓ELA过程中基板的冷却速率，增大多晶硅的晶粒尺寸，提高TFT的电学性能。
实施例1
本实施例公开了一种低温多晶硅薄膜晶体管，如图2所示，该低温多晶硅薄膜晶体管包括基板1，以及在基板上1依次形成的缓冲层2、有源层3和绝热保温层4。在低温多晶硅薄膜晶体管的非晶硅层上通过构图工艺形成有源层3。所述有源层3不超过其宽度1/4的边缘未被绝热保温层4覆盖。
本实施例所述低温多晶硅薄膜晶体管还包括在绝热保温层4的上方依次形成的栅绝缘层5、栅电极7、层间绝缘层6、以及源电极8和漏电极9。源电极8和漏电极9分别通过贯穿层间绝缘层6、栅绝缘层5及绝热保温层4的绝缘过孔与有源层3的两端连接。
本实施例中，在有源层3上沉积一层很薄的绝热保温层4，形成特定图案后进行ELA工艺。ELA的作用是将有源层熔融后再结晶，形成多晶硅。目前工艺中ELA的温度传播深度可达100nm,而有源层3的厚度一般不超过50nm，所以在有源层3上增加很薄的绝热保温层4不会对ELA工艺及有源层3的熔融再结晶有影响。
绝热保温层4的材料满足如下基本条件：导热系数小，抗压强度高，耐热性好，粘附性好，常温下稳定性高等，在高温下对有源层不会产生不良影响，而且在TFT工艺中易制备。例如，硅的氧化物(SiOx)，氮化硅(SiNx)等，满足上述条件的材料都可以作为理想的绝热保温材料。
本实施例中使用的氧化硅或氮化硅材料作为绝热保温层材料。绝热保温层的厚度范围为
Figure PCTCN2014088764-appb-000002
此类材料所形成的绝热保温层能够满足设计及材料要求，在相应工艺下形成大晶粒多晶硅。
基板1可以选择多种可用于多晶硅薄膜形成的衬底，如玻璃基板、石英基板等，其厚度可以采用常规尺寸，也可以根据需要采用其它的尺寸。
本实施例通过绝热保温层4与缓冲层2的双重保温作用，可以抑制有源层3中熔融硅的温度向下方的基板1及上方的环境中扩散，延长了多晶硅的晶化时间。而且，在本实施例中，绝热保温层4的图案宽度略小于有源层3的图案宽度，在晶化过程中，有源层3图案的边缘没有被绝热保温层4覆盖部分的冷却速率会较快，先结晶形成多晶硅，并作为籽晶，引导被绝热保温层4覆盖部分晶粒的生长，该方式更有助于大尺寸晶粒的生长，提高了TFT的迁移率。
实施例2
本实施例提供了一种用于制备低温多晶硅薄膜晶体管的方法，包括：
第1步：提供一基板1，在基板1上形成缓冲层2；在缓冲层2上形成有源层3；在有源层3形成绝热保温层4。
例如，有源层3的形成的工艺方法流程图见图1：
(1)基板1上依次沉积缓冲层2、有源层3和绝热保温层4，以获得初始结构。
(2)在绝热保温层4上形成光刻胶10。
(3)经过曝光、刻蚀工艺形成有源层3图案及绝热保温层4的初步图案。
(4)经过灰化工艺去掉绝热保温层4边缘部分的光刻胶。
(5)经过刻蚀及剥离工艺形成绝热保温层4图案。
(6)经过晶化工艺将有源层3的非晶硅晶化形成多晶硅(晶化后的有源层3见图1最终结构中阴影层状结构所示)。晶化过程是指采用ELA工艺使非晶硅层表面温度瞬间达到1400℃，非晶硅在高温下熔融，激光照射结束后， 随着温度降低，熔融的非晶硅层发生再结晶，从而形成多晶硅。
例如，选择玻璃衬底作为基板1，对基板1进行预清洗，利用等离子体增强化学气相沉积法沉积缓冲层2，后沉积有源层3，并在有源层3表面沉积绝热保温层4。缓冲层2可采用例如由氮化硅层和二氧化硅层的双层结构，下层是厚度为50-150nm的氮化硅层，上层是厚度为100-350nm的二氧化硅层。二氧化硅层的上面为厚度为300-600nm的有源层3。绝热保温层4厚度为
Figure PCTCN2014088764-appb-000003
采用氮化硅材料制备而成。
在绝热保温层4上依次沉积栅绝缘层5、栅电极7、层间介质层6及源电极8和漏电极9，形成TFT及半导体器件的基本结构。
例如，在绝热保温层4的上方沉积栅绝缘层5；在栅绝缘层5上方形成栅金属薄膜，通过构图工艺形成栅电极7的图案，并对所述有源层3两端的区域进行掺杂处理以形成离子掺杂区。在栅电极7上方形成层间绝缘层6，并通过构图工艺形成贯穿所述绝热保温层4、栅绝缘层5和层间绝缘层6的绝缘层过孔，从而露出所述有源层3两端的离子掺杂区。在层间绝缘层6上方形成源漏金属薄膜，并通过构图工艺形成源电极8和漏电极9，源电极8和漏电极9分别通过所述绝缘层过孔与有源层3两端的离子掺杂区连接。
本实施例通过在有源层上表面增加了绝热保温层4，能够在晶化过程中当高能量的激光撤离后，与缓冲层2共同对有源层进行保温，大大降低了非晶硅层的冷却速度，使晶粒在形成后有足够的时间生长，增大了晶粒尺寸，例如获得平均粒径2um左右的晶粒，可制备得到实施例1所述的薄膜晶体管，结构参见图2。
本发明的实施例对LTPS-TFT或半导体器件的结构设计了绝热保温层，以减缓ELA过程中基板的冷却速率，增大多晶硅的晶粒尺寸，提高TFT的电学性能。
本发明的实施例是在有源层的上表面形成有图案(Pattern)的绝热保温层，该绝热保温层与缓冲层分别在有源层的上表面和下表面来抑制熔融硅中温度的扩散，起到双层保温的作用，从而明显延长多晶硅晶化的时间。同时，绝热保温层的图案设计可以使有源层在图案边缘部分先结晶形成多晶硅籽晶，引导熔融硅生长，有助于大尺寸晶粒的生长，有效的提高了TFT的迁移率。
实施例3
本实施例提供了一种阵列基板，该阵列基板包括实施例1中所述的低温多晶硅薄膜晶体管。由此形成的阵列基板用于显示器背板中时，能够提高显示反应速度、降低功耗等。此种陈列基板适用于有源矩阵有机发光二极管显示器(AMOLED)、低温多晶硅薄膜晶体管液晶显示器(LTPS TFT-LCD)等。
实施例4
本实施例提供一种显示装置，该显示装置包括实施例3中所述的阵列基板。本实施例的显示装置，可以为有源矩阵有机发光二极管显示器(AMOLED)或者液晶显示器等。由于该显示装置中采用了低温多晶硅薄膜晶体管，在电学性能方面较非晶硅有很大改善，能够提高该显示装置的竞争能力。
通过以上实施例可以看出，本发明的实施例通过在有源层表面增加绝热保温层，在采用ELA方式进行有源层的晶化过程中，当高能量的激光撤离后，绝热保温层与缓冲层可以共同对硅薄膜进行保温，大大降低了其冷却速率，使晶粒在形成后有足够的时间生长，增大了晶粒尺寸，提高了载流子迁移率，提高了TFT及半导体器件的反应速率，降低了功耗，提升了产品的竞争力。本发明实施例所采用的方法，在生产过程中容易操作，工艺过程简洁并且不耗费原料。通过增大多晶硅晶粒的尺寸，能够得到迁移率较好的低温多晶硅薄膜晶体管。该方法得到的低温多晶硅薄膜可以作为低温多晶硅薄膜晶体管的有源层，适用于有源矩阵有机发光二极管显示器(AMOLED)及低温多晶硅薄膜晶体管液晶显示器(LTPS TFT-LCD)等领域。
以上实施例仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有这样的变化和变形以及等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。
本申请要求于2014年06月20日提交的名称为“低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置”的中国专利申请No.201410280920.3的优先权，其全文以引用方式合并于本文。

Claims (12)

  1. 一种低温多晶硅薄膜晶体管，包括依次在基板上形成的缓冲层和有源层，以及在所述有源层上形成的绝热保温层。
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中所述有源层的边缘未被所述绝热保温层覆盖。
  3. 根据权利要求2所述的低温多晶硅薄膜晶体管，其中未被所述绝热保温层覆盖的所述有源层的边缘宽度为不大于有源层宽度的1/4。
  4. 根据权利要求1-3任一项所述的低温多晶硅薄膜晶体管，其中所述绝热保温层的厚度为
    Figure PCTCN2014088764-appb-100001
  5. 根据权利要求1-4任一项所述的低温多晶硅薄膜晶体管，其中所述绝热保温层的材料包括氮化硅或氧化硅。
  6. 根据权利要求1-5任一项所述的低温多晶硅薄膜晶体管，还包括在所述绝热保温层的上方依次形成的栅绝缘层、栅电极、层间绝缘层，以及源电极和漏电极，所述源电极和漏电极分别通过贯穿层间绝缘层、栅绝缘层及绝热保温层的过孔与所述有源层的两端连接。
  7. 一种用于制备如权利要求1-6任一项所述低温多晶硅薄膜晶体管的方法，包括：
    提供一基板，在所述基板上形成缓冲层；
    通过构图工艺在所述缓冲层上形成有源层；以及
    在所述有源层上形成绝热保温层。
  8. 根据权利要求7所述的方法，其中所述有源层的边缘未被所述绝热保温层覆盖。
  9. 根据权利要求8所述的方法，其中未被所述绝热保温层覆盖的所述有源层的边缘宽度为不大于有源层宽度的1/4。
  10. 根据权利要求7-9任一项所述的方法，还包括：
    在所述绝热保温层的上方沉积栅绝缘层；
    在所述栅绝缘层上方形成栅金属薄膜，通过构图工艺形成栅电极的图案，并对所述有源层两端的区域进行掺杂处理以形成离子掺杂区；
    在所述栅电极上方形成层间绝缘层，并通过构图工艺形成贯穿所述绝热保温层、栅绝缘层和层间绝缘层的绝缘层过孔，从而露出所述有源层两端的 离子掺杂区；以及
    在所述层间绝缘层上方形成源漏金属薄膜，并通过构图工艺形成源电极和漏电极，所述源电极和漏电极分别通过所述绝缘层过孔与所述有源层两端的离子掺杂区连接。
  11. 一种阵列基板，包含权利要求1-6任一项所述的低温多晶硅薄膜晶体管。
  12. 一种显示装置，包含权利要求11所述的阵列基板。
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CN203895510U (zh) * 2014-06-20 2014-10-22 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及其阵列基板与显示装置

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