WO2016065768A1 - 低温多晶硅的制作方法及tft基板的制作方法 - Google Patents

低温多晶硅的制作方法及tft基板的制作方法 Download PDF

Info

Publication number
WO2016065768A1
WO2016065768A1 PCT/CN2015/072349 CN2015072349W WO2016065768A1 WO 2016065768 A1 WO2016065768 A1 WO 2016065768A1 CN 2015072349 W CN2015072349 W CN 2015072349W WO 2016065768 A1 WO2016065768 A1 WO 2016065768A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
mesh film
metal mesh
amorphous silicon
polysilicon
Prior art date
Application number
PCT/CN2015/072349
Other languages
English (en)
French (fr)
Inventor
李亚
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/423,124 priority Critical patent/US20160254294A1/en
Publication of WO2016065768A1 publication Critical patent/WO2016065768A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating low temperature polysilicon and a method for fabricating a TFT substrate using the same.
  • Low Temperature Poly-Silicon has received industry attention in liquid crystal display (LCD) and Organic Light Emitting Diode (OLED) technology due to its high electron mobility. It is regarded as an important material for realizing low-cost full-color flat panel display.
  • low temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, low energy consumption, etc., and low temperature polysilicon can be fabricated at low temperature and can be used to fabricate C-MOS circuits. Widely researched to meet the needs of high resolution, low energy consumption.
  • Low temperature polysilicon is a branch of polysilicon (poly-Si) technology.
  • the molecular structure of polycrystalline silicon is neat and directional in a grain, so the electron mobility is 200-300 times faster than the disordered amorphous silicon (a-Si), which greatly improves the plate. The speed of the reaction shown.
  • low-temperature polysilicon is mainly produced by chemical vapor deposition (CVD), solid phase crystallization (SPC), metal-induced crystallography (MIC), and metal-induced lateral crystallization (Metal-Induced Lateral). Crystallization, MILC, Excimer Laser Annealing (ELA) and other crystallization processes.
  • a method for fabricating a TFT substrate generally using low-temperature polysilicon mainly includes the following steps: Step 1. Providing a substrate 100; Step 2, depositing a buffer layer 200 on the glass substrate 100; Step 3, in a buffer layer Amorphous silicon layer 300 is deposited on 200; step 4, using an existing CVD, SPC, MIC, MILC, or ELA crystallization process to convert amorphous silicon layer 300 into polysilicon layer 400; step 5, through yellow light, etching process The polysilicon layer 400 is patterned to form a polysilicon semiconductor layer 450. In step 6, a gate insulating layer 500, a gate electrode 600, an interlayer insulating layer 700, and a source/drain 800 are sequentially formed on the polysilicon semiconductor layer 450.
  • the polycrystalline silicon grain size obtained by the CVD crystallization process is particularly small and the deposition rate is low; the conventional SPC crystallization process requires high temperature and long time, which causes the substrate to be easily deformed and has high cost; the polysilicon layer metal obtained by the MIC or MILC crystallization process There are more residues, resulting in poor electrical conductivity of the TFT; The polysilicon gap state density obtained by the ELA crystallization process is low, and it is difficult to prepare a large-area polysilicon film, and the ELA device is expensive.
  • the object of the present invention is to provide a method for manufacturing low-temperature polysilicon, which can effectively reduce the crystallization process temperature, shorten the crystallization process time, reduce the cost of preparing a polycrystalline silicon film in a large area, and improve the crystallization effect to make the crystal grains larger and more uniform.
  • Another object of the present invention is to provide a method for fabricating a TFT substrate, which can reduce the crystallization process temperature, shorten the crystallization process time, and improve the crystallization effect, make the crystal grains larger and more uniform, and improve the electrical properties of the TFT.
  • the present invention first provides a method for fabricating low temperature polysilicon, comprising the following steps:
  • Step 1 Providing a substrate
  • Step 2 depositing a buffer layer on the substrate
  • Step 3 plating a metal mesh film on the buffer layer
  • Step 4 depositing an amorphous silicon layer on the metal mesh film
  • Step 5 performing rapid thermal annealing treatment on the amorphous silicon layer, and the metal material in the metal mesh film and the silicon in the amorphous silicon layer are combined into a metal silicide to induce the amorphous silicon layer to crystallize and transform into a polysilicon layer;
  • the metal mesh film with metal silicide is moved up above the polysilicon layer
  • Step 6 Remove the metal mesh film having the metal silicide.
  • the material of the metal mesh film is aluminum.
  • the rapid thermal annealing treatment temperature was 600 ° C and the time was 10 minutes.
  • the buffer layer is a single layer SiNx layer, a single layer SiOx layer, a double layer SiNx layer, a double layer SiOx layer, or a combination of both a SiNx layer and an SiOx layer.
  • the present invention also provides a method for fabricating a TFT substrate using the low-temperature polysilicon fabrication method, comprising the following steps:
  • Step 1 Providing a substrate
  • Step 2 depositing a buffer layer on the substrate
  • Step 3 plating a metal mesh film on the buffer layer
  • Step 4 depositing an amorphous silicon layer on the metal mesh film
  • Step 5 performing rapid thermal annealing treatment on the amorphous silicon layer, and the metal material in the metal mesh film and the silicon in the amorphous silicon layer are combined into a metal silicide to induce the amorphous silicon layer to crystallize and transform into a polysilicon layer;
  • the metal mesh film with metal silicide is moved up above the polysilicon layer
  • Step 6 removing a metal mesh film having a metal silicide
  • Step 7 patterning the polysilicon layer to form a polysilicon semiconductor layer
  • Step 8 A gate insulating layer, a gate electrode, an interlayer insulating layer, and a source/drain are sequentially formed on the polysilicon semiconductor layer, and the source/drain are connected to the polysilicon semiconductor layer.
  • the material of the metal mesh film is aluminum.
  • the rapid thermal annealing treatment temperature was 600 ° C and the time was 10 minutes.
  • the buffer layer is a single layer SiNx layer, a single layer SiOx layer, a double layer SiNx layer, a double layer SiOx layer, or a combination of both a SiNx layer and an SiOx layer.
  • the polysilicon layer is patterned by a yellow light or etching process.
  • the method for fabricating low-temperature polysilicon of the present invention and the method for fabricating the TFT substrate by depositing an amorphous silicon layer on the metal mesh film, using a rapid thermal annealing treatment to make the metal material and the amorphous metal in the metal mesh film
  • the silicon in the silicon layer is combined into a metal silicide, which induces crystallization of the amorphous silicon layer, transformation into a polysilicon layer, and removal of the metal mesh film, so that the amorphous silicon layer is rapidly crystallized at a lower temperature, which can effectively reduce the crystallization process.
  • FIG. 1 is a schematic view showing a step 2 of a conventional TFT substrate manufacturing method using low temperature polysilicon
  • FIG. 2 is a schematic view showing a step 3 of a conventional TFT substrate manufacturing method using low temperature polysilicon
  • FIG. 3 is a schematic view showing a step 4 of a conventional TFT substrate manufacturing method using low temperature polysilicon
  • FIG. 5 is a schematic view showing a step 6 of a conventional TFT substrate manufacturing method using low temperature polysilicon
  • FIG. 6 is a flow chart of a method for fabricating low temperature polysilicon according to the present invention.
  • FIG. 7 is a flow chart showing a method of fabricating a TFT substrate of the present invention.
  • FIG. 8 is a schematic view showing a method for fabricating a low-temperature polysilicon and a step 2 of a method for fabricating a TFT substrate;
  • FIG. 9 is a schematic view showing a method for fabricating a low temperature polysilicon and a step 3 of a method for fabricating a TFT substrate;
  • FIG. 10 is a schematic view showing a method for fabricating a low temperature polycrystalline silicon according to the present invention and a step 4 of a method for fabricating a TFT substrate;
  • FIG. 11 is a schematic view showing a rapid thermal annealing treatment in the step 5 of the method for fabricating the low-temperature polysilicon of the present invention and the method for fabricating the TFT substrate;
  • FIG. 12 is a schematic view of the method for fabricating the low-temperature polysilicon of the present invention and the step 5 of the method for fabricating the TFT substrate;
  • FIG. 13 is a schematic view showing a method of fabricating a low temperature polysilicon and a step 6 of a method for fabricating a TFT substrate;
  • FIG. 14 is a schematic view showing a step 7 of a method of fabricating a TFT substrate of the present invention.
  • Figure 15 is a schematic view showing the step 8 of the method of fabricating the TFT substrate of the present invention.
  • the present invention provides a method for fabricating low temperature polysilicon, comprising the following steps:
  • Step 1 Provide a substrate 1.
  • the substrate 1 is a general transparent substrate.
  • the substrate 1 is a glass substrate.
  • Step 2 As shown in FIG. 8, a buffer layer 2 is deposited on the substrate 1.
  • the buffer layer 2 may be a single layer SiNx layer, a single layer SiOx layer, a double layer SiNx layer, a double layer SiOx layer, or a combination of both the SiNx layer and the SiOx layer.
  • Step 3 As shown in FIG. 9, a metal mesh film 3 is plated on the buffer layer 2.
  • the material of the metal mesh film 3 is aluminum.
  • Step 4 As shown in FIG. 10, an amorphous silicon layer 4 is deposited on the metal mesh film 3.
  • the amorphous silicon layer 4, the metal mesh film 3, and the buffer layer 2 are laminated in this order from top to bottom.
  • Step 5 as shown in FIG. 11 and FIG. 12, the amorphous silicon layer 4 is subjected to Rapid Thermal Annealing (RTA) treatment, and the metal material in the metal mesh film 3 is combined with the silicon in the amorphous silicon layer 4.
  • RTA Rapid Thermal Annealing
  • the metal silicide induces crystallization of the amorphous silicon layer 4 and conversion into the polysilicon layer 5.
  • the step 5 utilizes a eutectic property of the interface between the metal and the silicon, and is heated at 600 ° C.
  • the amorphous silicon layer 4 can be crystallized and converted into the polysilicon layer 5, which effectively lowers the RTA temperature and shortens the RTA time, so that the amorphous silicon layer 4 is rapidly crystallized at a lower temperature.
  • the substrate 1 There is no special requirement for the substrate 1, and the ordinary substrate can withstand the temperature of 600 ° C, which reduces the manufacturing cost and can be used for making a large-area polycrystalline silicon film.
  • the metal material in the metal mesh film 3 is combined with the silicon in the amorphous silicon layer 4 to form a metal silicide to induce crystallization of the amorphous silicon layer 4, and the network structure of the metal mesh film 3 is advantageous for the metal.
  • the lateral crystallization is induced to make the crystallization more thorough, and the obtained polycrystalline silicon grains are larger and more uniform, and the crystallization effect is better.
  • the metal mesh film 3 having the metal silicide is moved up above the polysilicon layer 5.
  • the metal silicide-containing metal mesh film 3, the polysilicon layer 5, and the buffer layer 2 are laminated in this order from top to bottom.
  • Step 6 As shown in FIG. 13, the metal mesh film 3 having the metal silicide is removed.
  • the metal mesh film 3, the polysilicon layer 5, and the buffer layer 2 having the metal silicide are sequentially stacked from top to bottom, and the metal mesh film 3 having the metal silicide is located at the top, which is convenient in the step 6. Remove it.
  • the method for fabricating the low-temperature polysilicon of the present invention can be used to fabricate a top-gate TFT substrate, a bottom-gate TFT substrate, and an active OLED (AMOLED).
  • AMOLED active OLED
  • the present invention further provides a method for fabricating a TFT substrate using the method, wherein a top gate TFT substrate is taken as an example, and the TFT substrate is fabricated. Including the following steps:
  • Step 1 Provide a substrate 1.
  • the substrate 1 is a general transparent substrate.
  • the substrate 1 is a glass substrate.
  • Step 2 As shown in FIG. 8, a buffer layer 2 is deposited on the substrate 1.
  • the buffer layer 2 may be a single layer SiNx layer, a single layer SiOx layer, a double layer SiNx layer, a double layer SiOx layer, or a combination of both the SiNx layer and the SiOx layer.
  • Step 3 As shown in FIG. 9, a metal mesh film 3 is plated on the buffer layer 2.
  • the material of the metal mesh film 3 is aluminum.
  • Step 4 As shown in FIG. 10, an amorphous silicon layer 4 is deposited on the metal mesh film 3.
  • the amorphous silicon layer 4, the metal mesh film 3, and the buffer layer 2 are laminated in this order from top to bottom.
  • Step 5 as shown in FIG. 11 and FIG. 12, the amorphous silicon layer 4 is subjected to fast RTA treatment, and the metal material in the metal mesh film 3 and the silicon in the amorphous silicon layer 4 are combined into a metal silicide to induce amorphous silicon.
  • Layer 4 is crystallized and converted into polysilicon layer 5.
  • the eutectic property of the interface between the metal and the silicon is used, and the amorphous silicon layer 4 is crystallized and converted into the polysilicon layer 5 by the RTA treatment at a temperature of 600 ° C for 10 minutes, thereby effectively reducing the RTA temperature.
  • the RTA time is shortened, the amorphous silicon layer 4 is rapidly crystallized at a lower temperature, and there is no special requirement for the substrate 1.
  • the ordinary substrate can withstand the temperature of 600 ° C, which reduces the manufacturing cost and can be used for making large-area polysilicon. film.
  • the metal material in the metal mesh film 3 is combined with the silicon in the amorphous silicon layer 4 to form a metal silicide to induce crystallization of the amorphous silicon layer 4, and the network structure of the metal mesh film 3 is advantageous for the metal.
  • the lateral crystallization is induced to make the crystallization more thorough, and the obtained polycrystalline silicon grains are larger and more uniform, and the crystallization effect is better.
  • the metal mesh film 3 having the metal silicide is moved up above the polysilicon layer 5.
  • the metal silicide-containing metal mesh film 3, the polysilicon layer 5, and the buffer layer 2 are laminated in this order from top to bottom.
  • Step 6 As shown in FIG. 13, the metal mesh film 3 having the metal silicide is removed.
  • the metal mesh film 3, the polysilicon layer 5, and the buffer layer 2 having the metal silicide are sequentially stacked from top to bottom, and the metal mesh film 3 having the metal silicide is located at the top, which is convenient in the step 6. Remove it.
  • Step 7 As shown in FIG. 14, the polysilicon layer 5 is patterned by a photo or etch process to form a polysilicon semiconductor layer 55.
  • Step 8 as shown in FIG. 15, a gate insulating layer 6, a gate electrode 7, an interlayer insulating layer 8, a source/drain electrode 9, a source/drain electrode 9 and a polysilicon semiconductor layer are sequentially formed on the polysilicon semiconductor layer 55. 55 connections.
  • the fabrication of the top gate type TFT substrate is completed. Since the polycrystalline silicon crystal grains in the polysilicon layer 5 formed in the step 5 are larger and more uniform, and the metal mesh film 3 having the metal silicide is removed in the step 6, the electricity of the polycrystalline silicon semiconductor layer 55 formed in the step 7 can be made. The properties are better, thereby improving the electrical properties of the TFT.
  • the method for fabricating the low-temperature polysilicon of the present invention and the method for fabricating the TFT substrate by depositing an amorphous silicon layer on the metal mesh film, using a rapid thermal annealing treatment to make the metal material and the amorphous silicon in the metal mesh film
  • the silicon in the layer is combined into a metal silicide, which induces crystallization of the amorphous silicon layer, transformation into a polysilicon layer, and removal of the metal mesh film, so that the amorphous silicon layer is rapidly crystallized at a lower temperature, which can effectively reduce the crystallization process temperature.
  • the crystallization process time is shortened, the cost of preparing a polycrystalline silicon film in a large area is reduced, the crystallization effect is improved, the crystal grains are made larger and more uniform, and the electrical properties of the TFT are improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

一种低温多晶硅的制作方法及TFT基板的制作方法。所述低温多晶硅制作方法包括如下步骤：步骤1、提供一基板(1)；步骤2、在基板(1)上沉积缓冲层(2)；步骤3、在缓冲层(2)上镀一层金属网膜(3)；步骤4、在金属网膜(3)上沉积非晶硅层(4)；步骤5、对非晶硅层(4)进行快速热退火处理，非晶硅层(4)结晶、转变为多晶硅层(5)；步骤6、移除金属网膜(3)。该方法能够有效降低结晶制程温度、缩短结晶制程时间，降低大面积制备多晶硅薄膜的成本，并改善结晶效果，使晶粒更大更均匀。

Description

低温多晶硅的制作方法及TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅的制作方法及使用该方法的TFT基板的制作方法。
背景技术
随着平板显示的发展，高分辨率，低能耗的面板需求不断被提出。低温多晶硅(Low Temperature Poly-Silicon，LTPS)由于具有较高的电子迁移率，而在液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器Organic Light Emitting Diode，OLED)技术中得到了业界的重视，被视为实现低成本全彩平板显示的重要材料。对平板显示而言，采用低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点，而且低温多晶硅可在低温下制作，并可用于制作C-MOS电路，因而被广泛研究，用以达到面板高分辨率，低能耗的需求。
低温多晶硅是多晶硅(poly-Si)技术的一个分支。多晶硅的分子结构在一颗晶粒中的排列状态是整齐而有方向性的，因此电子迁移率比排列杂乱的非晶硅(a-Si)快了200-300倍，极大的提高了平板显示的反应速度。目前制作低温多晶硅主要有：化学气相沉积(Chemical Vapor Deposition，CVD)、固相结晶(Solid Phase Crystallization，SPC)、金属诱导结晶(Metal-Induced Crystallization，MIC)、金属诱导横向结晶(Metal-Induced Lateral Crystallization，MILC)、准分子激光退火(Excimer Laser Annealing，ELA)等多种结晶制程方法。
请参阅图1至图5，通常采用低温多晶硅的TFT基板的制作方法主要包括如下步骤：步骤1、提供一基板100；步骤2、在玻璃基板100上沉积缓冲层200；步骤3、在缓冲层200上沉积非晶硅层300；步骤4、采用现有的CVD、SPC、MIC、MILC、或ELA结晶制程方法使非晶硅层300转变为多晶硅层400；步骤5、通过黄光、蚀刻制程对多晶硅层400进行图案化处理，形成多晶硅半导体层450；步骤6、在多晶硅半导体层450上依次形成栅极绝缘层500、栅极600、层间绝缘层700、源/漏极800。
采用CVD结晶制程得到的多晶硅晶粒尺寸特别小，且沉积速率低；传统的SPC结晶制程需要高温且耗时长，导致基板易变形，成本较高；采用MIC或MILC结晶制程制得的多晶硅层金属残留较多，导致TFT电性变差； 采用ELA结晶制程制得的多晶硅缺隙态密度低，难以制备大面积多晶硅薄膜，且ELA设备昂贵。
发明内容
本发明的目的首先在于提供一种低温多晶硅的制作方法，能够有效降低结晶制程温度、缩短结晶制程时间，降低大面积制备多晶硅薄膜的成本，并改善结晶效果，使晶粒更大更均匀。
本发明的另一目的在于提供一种TFT基板的制作方法，能够降低结晶制程温度、缩短结晶制程时间，并改善结晶效果，使晶粒更大更均匀，提高TFT的电性。
为实现上述目的，本发明首先提供一种低温多晶硅制作方法，包括如下步骤：
步骤1、提供一基板；
步骤2、在基板上沉积缓冲层；
步骤3、在缓冲层上镀一层金属网膜；
步骤4、在金属网膜上沉积非晶硅层；
步骤5、对非晶硅层进行快速热退火处理，金属网膜中的金属材料与非晶硅层中的硅结合成金属硅化物，诱导非晶硅层结晶、转变为多晶硅层；
具有金属硅化物的金属网膜上移至多晶硅层上方；
步骤6、移除具有金属硅化物的金属网膜。
所述金属网膜的材料为铝。
所述步骤5中，快速热退火处理的温度为600℃，时间为10分钟。
所述缓冲层为单层SiNx层、单层SiOx层、双层SiNx层、双层SiOx层、或者SiNx层与SiOx层二者的组合。
本发明还提供一种使用该低温多晶硅制作方法的TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板；
步骤2、在基板上沉积缓冲层；
步骤3、在缓冲层上镀一层金属网膜；
步骤4、在金属网膜上沉积非晶硅层；
步骤5、对非晶硅层进行快速热退火处理，金属网膜中的金属材料与非晶硅层中的硅结合成金属硅化物，诱导非晶硅层结晶、转变为多晶硅层；
具有金属硅化物的金属网膜上移至多晶硅层上方；
步骤6、移除具有金属硅化物的金属网膜；
步骤7、对多晶硅层进行图案化处理，形成多晶硅半导体层；
步骤8、在多晶硅半导体层上依次形成栅极绝缘层、栅极、层间绝缘层、源/漏极，所述源/漏极与多晶硅半导体层连接。
所述金属网膜的材料为铝。
所述步骤5中，快速热退火处理的温度为600℃，时间为10分钟。
所述缓冲层为单层SiNx层、单层SiOx层、双层SiNx层、双层SiOx层、或者SiNx层与SiOx层二者的组合。
所述步骤7通过黄光、蚀刻制程对多晶硅层进行图案化处理。
本发明的有益效果：本发明的低温多晶硅的制作方法及TFT基板的制作方法，通过将非晶硅层沉积于金属网膜上，采用快速热退火处理使金属网膜中的金属材料与非晶硅层中的硅结合成金属硅化物，诱导非晶硅层结晶、转变为多晶硅层，再移除金属网膜，使得非晶硅层在较低的温度下快速晶化，能够有效降低结晶制程温度、缩短结晶制程时间，降低大面积制备多晶硅薄膜的成本，并改善结晶效果，使晶粒更大更均匀，从而提高TFT的电性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的采用低温多晶硅的TFT基板的制作方法的步骤2的示意图；
图2为现有的采用低温多晶硅的TFT基板的制作方法的步骤3的示意图；
图3为现有的采用低温多晶硅的TFT基板的制作方法的步骤4的示意图；
图4为现有的采用低温多晶硅的TFT基板的制作方法的步骤5的示意图；
图5为现有的采用低温多晶硅的TFT基板的制作方法的步骤6的示意图；
图6为本发明低温多晶硅的制作方法的流程图；
图7为本发明TFT基板的制作方法的流程图；
图8为本发明低温多晶硅的制作方法及TFT基板的制作方法的步骤2的示意图；
图9为本发明低温多晶硅的制作方法及TFT基板的制作方法的步骤3的示意图；
图10为本发明低温多晶硅的制作方法及TFT基板的制作方法的步骤4的示意图；
图11为本发明低温多晶硅的制作方法及TFT基板的制作方法的步骤5中进行快速热退火处理的示意图；
图12为本发明低温多晶硅的制作方法及TFT基板的制作方法的步骤5完成之后的示意图；
图13为本发明低温多晶硅的制作方法及TFT基板的制作方法的步骤6的示意图；
图14为本发明TFT基板的制作方法的步骤7的示意图；
图15为本发明TFT基板的制作方法的步骤8的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图6及图8至图13，本发明提供一种低温多晶硅的制作方法，包括如下步骤：
步骤1、提供一基板1。
所述基板1为普通的透明基板，优选的，所述基板1为玻璃基板。
步骤2、如图8所示，在基板1上沉积缓冲层2。
具体的，所述缓冲层2可为单层SiNx层、单层SiOx层、双层SiNx层、双层SiOx层、或者SiNx层与SiOx层二者的组合。
步骤3、如图9所示，在缓冲层2上镀一层金属网膜3。
具体的，所述金属网膜3的材料为铝。
步骤4、如图10所示，在在金属网膜3上沉积非晶硅层4。
完成该步骤4后，所述非晶硅层4、金属网膜3、缓冲层2由上至下依次层叠。
步骤5、如图11、图12所示，对非晶硅层4进行快速热退火(Rapid Thermal Annealing，RTA)处理，金属网膜3中的金属材料与非晶硅层4中的硅结合成金属硅化物，诱导非晶硅层4结晶、转变为多晶硅层5。
进一步的，所述步骤5利用金属与硅界面的低共熔点特性，在600℃温 度下用RTA处理10分钟即能够使非晶硅层4结晶、转变为多晶硅层5，有效降低了RTA温度，缩短了RTA时间，使得非晶硅层4在较低的温度下快速晶化，且对基板1没有特殊要求，普通基板即可耐受600℃温度，降低了制作成本，可用于制作大面积多晶硅薄膜。
在RTA处理过程中，金属网膜3中的金属材料与非晶硅层4中的硅结合成金属硅化物从而诱导非晶硅层4结晶，所述金属网膜3的网状结构有利于金属诱导侧向结晶，使得晶化更彻底，制得的多晶硅晶粒更大更均匀，结晶效果较好。
值得一提的是，完成该步骤5后，如图12所示，具有金属硅化物的金属网膜3上移至多晶硅层5上方。此时，所述具有金属硅化物的金属网膜3、多晶硅层5、缓冲层2由上至下依次层叠。
步骤6、如图13所示，移除具有金属硅化物的金属网膜3。
由于完成步骤5后，具有金属硅化物的金属网膜3、多晶硅层5、缓冲层2由上至下依次层叠，具有金属硅化物的金属网膜3位于最上方，在该步骤6中可方便的将其移除。
至此，完成低温多晶硅制作。
本发明的低温多晶硅的制作方法可用于制作顶栅型(Top-Gate)TFT基板、底栅型(Bottom-Gate)TFT基板以及主动型OLED(AMOLED)。
请参阅图7至图15，在上述低温多晶硅制作方法的基础上，本发明还提供一种使用该方法的TFT基板的制作方法，以顶栅型TFT基板为例，所述TFT基板的制作方法包括如下步骤：
步骤1、提供一基板1。
所述基板1为普通的透明基板，优选的，所述基板1为玻璃基板。
步骤2、如图8所示，在基板1上沉积缓冲层2。
具体的，所述缓冲层2可为单层SiNx层、单层SiOx层、双层SiNx层、双层SiOx层、或者SiNx层与SiOx层二者的组合。
步骤3、如图9所示，在缓冲层2上镀一层金属网膜3。
具体的，所述金属网膜3的材料为铝。
步骤4、如图10所示，在在金属网膜3上沉积非晶硅层4。
完成该步骤4后，所述非晶硅层4、金属网膜3、缓冲层2由上至下依次层叠。
步骤5、如图11、图12所示，对非晶硅层4进行快RTA处理，金属网膜3中的金属材料与非晶硅层4中的硅结合成金属硅化物，诱导非晶硅层4结晶、转变为多晶硅层5。
进一步的，所述步骤5利用金属与硅界面的低共熔点特性，在600℃温度下用RTA处理10分钟即能够使非晶硅层4结晶、转变为多晶硅层5，有效降低了RTA温度，缩短了RTA时间，使得非晶硅层4在较低的温度下快速晶化，且对基板1没有特殊要求，普通基板即可耐受600℃温度，降低了制作成本，可用于制作大面积多晶硅薄膜。
在RTA处理过程中，金属网膜3中的金属材料与非晶硅层4中的硅结合成金属硅化物从而诱导非晶硅层4结晶，所述金属网膜3的网状结构有利于金属诱导侧向结晶，使得晶化更彻底，制得的多晶硅晶粒更大更均匀，结晶效果较好。
值得一提的是，完成该步骤5后，如图12所示，具有金属硅化物的金属网膜3上移至多晶硅层5上方。此时，所述具有金属硅化物的金属网膜3、多晶硅层5、缓冲层2由上至下依次层叠。
步骤6、如图13所示，移除具有金属硅化物的金属网膜3。
由于完成步骤5后，具有金属硅化物的金属网膜3、多晶硅层5、缓冲层2由上至下依次层叠，具有金属硅化物的金属网膜3位于最上方，在该步骤6中可方便的将其移除。
步骤7、如图14所示，通过黄光(photo)、蚀刻(etch)制程对多晶硅层5进行图案化处理，形成多晶硅半导体层55。
步骤8、如图15所示，在多晶硅半导体层55上依次形成栅极绝缘层6、栅极7、层间绝缘层8、源/漏极9，所述源/漏极9与多晶硅半导体层55连接。
至此，完成该顶栅型TFT基板的制作。由于所述步骤5形成的多晶硅层5内的多晶硅晶粒更大更均匀，且步骤6中移除了具有金属硅化物的金属网膜3，能够使得步骤7中形成的多晶硅半导体层55的电性较好，从而改善TFT的电性。
综上所述，本发明的低温多晶硅的制作方法及TFT基板的制作方法，通过将非晶硅层沉积于金属网膜上，采用快速热退火处理使金属网膜中的金属材料与非晶硅层中的硅结合成金属硅化物，诱导非晶硅层结晶、转变为多晶硅层，再移除金属网膜，使得非晶硅层在较低的温度下快速晶化，能够有效降低结晶制程温度、缩短结晶制程时间，降低大面积制备多晶硅薄膜的成本，并改善结晶效果，使晶粒更大更均匀，并改善TFT的电性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种低温多晶硅的制作方法，包括如下步骤：
    步骤1、提供一基板；
    步骤2、在基板上沉积缓冲层；
    步骤3、在缓冲层上镀一层金属网膜；
    步骤4、在金属网膜上沉积非晶硅层；
    步骤5、对非晶硅层进行快速热退火处理，金属网膜中的金属材料与非晶硅层中的硅结合成金属硅化物，诱导非晶硅层结晶、转变为多晶硅层；
    具有金属硅化物的金属网膜上移至多晶硅层上方；
    步骤6、移除具有金属硅化物的金属网膜。
  2. 如权利要求1所述的低温多晶硅的制作方法，其中，所述金属网膜的材料为铝。
  3. 如权利要求1所述的低温多晶硅的制作方法，其中，所述步骤5中，快速热退火处理的温度为600℃，时间为10分钟。
  4. 如权利要求1所述的低温多晶硅的制作方法，其中，所述缓冲层为单层SiNx层、单层SiOx层、双层SiNx层、双层SiOx层、或者SiNx层与SiOx层二者的组合。
  5. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板；
    步骤2、在基板上沉积缓冲层；
    步骤3、在缓冲层上镀一层金属网膜；
    步骤4、在金属网膜上沉积非晶硅层；
    步骤5、对非晶硅层进行快速热退火处理，金属网膜中的金属材料与非晶硅层中的硅结合成金属硅化物，诱导非晶硅层结晶、转变为多晶硅层；
    具有金属硅化物的金属网膜上移至多晶硅层上方；
    步骤6、移除具有金属硅化物的金属网膜；
    步骤7、对多晶硅层进行图案化处理，形成多晶硅半导体层；
    步骤8、在多晶硅半导体层上依次形成栅极绝缘层、栅极、层间绝缘层、源/漏极，所述源/漏极与多晶硅半导体层连接。
  6. 如权利要求5所述的TFT基板的制作方法，其中，所述金属网膜的材料为铝。
  7. 如权利要求5所述的TFT基板的制作方法，其中，所述步骤5中， 快速热退火处理的温度为600℃，时间为10分钟。
  8. 如权利要求5所述的TFT基板的制作方法，其中，所述缓冲层为单层SiNx层、单层SiOx层、双层SiNx层、双层SiOx层、或者SiNx层与SiOx层二者的组合。
  9. 如权利要求5所述的TFT基板的制作方法，其中，所述步骤7通过黄光、蚀刻制程对多晶硅层进行图案化处理。
  10. 一种低温多晶硅的制作方法，包括如下步骤：
    步骤1、提供一基板；
    步骤2、在基板上沉积缓冲层；
    步骤3、在缓冲层上镀一层金属网膜；
    步骤4、在金属网膜上沉积非晶硅层；
    步骤5、对非晶硅层进行快速热退火处理，金属网膜中的金属材料与非晶硅层中的硅结合成金属硅化物，诱导非晶硅层结晶、转变为多晶硅层；
    具有金属硅化物的金属网膜上移至多晶硅层上方；
    步骤6、移除具有金属硅化物的金属网膜；
    其中，所述金属网膜的材料为铝；
    其中，所述步骤5中，快速热退火处理的温度为600℃，时间为10分钟；
    其中，所述缓冲层为单层SiNx层、单层SiOx层、双层SiNx层、双层SiOx层、或者SiNx层与SiOx层二者的组合。
PCT/CN2015/072349 2014-10-30 2015-02-06 低温多晶硅的制作方法及tft基板的制作方法 WO2016065768A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/423,124 US20160254294A1 (en) 2014-10-30 2015-02-06 Manufacture method of ltps and manufacture method of tft substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410605937.1 2014-10-30
CN201410605937.1A CN104465319B (zh) 2014-10-30 2014-10-30 低温多晶硅的制作方法及tft基板的制作方法

Publications (1)

Publication Number Publication Date
WO2016065768A1 true WO2016065768A1 (zh) 2016-05-06

Family

ID=52911194

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/072349 WO2016065768A1 (zh) 2014-10-30 2015-02-06 低温多晶硅的制作方法及tft基板的制作方法

Country Status (3)

Country Link
US (1) US20160254294A1 (zh)
CN (1) CN104465319B (zh)
WO (1) WO2016065768A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104992899A (zh) * 2015-06-09 2015-10-21 深圳市华星光电技术有限公司 多晶硅薄膜的制备方法及多晶硅tft结构
CN106783532B (zh) * 2016-11-18 2020-03-31 武汉华星光电技术有限公司 一种低温多晶硅薄膜的制备方法、薄膜晶体管、阵列基板以及液晶显示面板
JP7213726B2 (ja) * 2019-03-13 2023-01-27 東京エレクトロン株式会社 成膜方法及び熱処理装置
CN112563196A (zh) * 2020-11-24 2021-03-26 惠科股份有限公司 一种主动开关的制作方法和显示面板
CN113871526B (zh) * 2021-09-17 2023-07-25 Tcl华星光电技术有限公司 显示面板的制作方法及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047124A (zh) * 2006-03-28 2007-10-03 精工爱普生株式会社 半导体装置的制造方法
US20100102403A1 (en) * 2008-08-14 2010-04-29 Board Of Regents, The University Of Texas System Method and apparatus for fabricating piezoresistive polysilicon by low-temperature metal induced crystallization
US20100184276A1 (en) * 2007-07-31 2010-07-22 The Regents Of The University Of California Low-temperature formation of polycrystalline semiconductor films via enhanced metal-induced crystallization
CN101807545A (zh) * 2010-03-22 2010-08-18 中国科学院上海微系统与信息技术研究所 二极管及电阻转换存储器的制造方法
CN101834138A (zh) * 2010-02-09 2010-09-15 广东中显科技有限公司 一种晶化薄膜的晶体管器件的制备方法
CN102290335A (zh) * 2010-06-16 2011-12-21 三星移动显示器株式会社 使硅层结晶的方法和制造薄膜晶体管的方法
CN102770946A (zh) * 2010-02-26 2012-11-07 泰拉半导体株式会社 多晶硅层的制造方法及用于其的金属混合层形成装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1265430C (zh) * 2003-04-09 2006-07-19 友达光电股份有限公司 低温多晶硅薄膜晶体管及其多晶硅层的制造方法
CN100555587C (zh) * 2003-04-25 2009-10-28 友达光电股份有限公司 低温多晶硅薄膜晶体管及其制造方法
CN1285107C (zh) * 2003-06-12 2006-11-15 统宝光电股份有限公司 低温多晶硅薄膜晶体管的制造方法
US7115449B2 (en) * 2003-06-24 2006-10-03 National Chiao Tung University Method for fabrication of polycrystalline silicon thin film transistors
CN102891107B (zh) * 2012-10-19 2015-03-25 京东方科技集团股份有限公司 低温多晶硅基板及其制作方法
CN103199151A (zh) * 2013-03-07 2013-07-10 宁波大学 一种基于金属诱导的多晶硅薄膜的制备方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047124A (zh) * 2006-03-28 2007-10-03 精工爱普生株式会社 半导体装置的制造方法
US20100184276A1 (en) * 2007-07-31 2010-07-22 The Regents Of The University Of California Low-temperature formation of polycrystalline semiconductor films via enhanced metal-induced crystallization
US20100102403A1 (en) * 2008-08-14 2010-04-29 Board Of Regents, The University Of Texas System Method and apparatus for fabricating piezoresistive polysilicon by low-temperature metal induced crystallization
CN101834138A (zh) * 2010-02-09 2010-09-15 广东中显科技有限公司 一种晶化薄膜的晶体管器件的制备方法
CN102770946A (zh) * 2010-02-26 2012-11-07 泰拉半导体株式会社 多晶硅层的制造方法及用于其的金属混合层形成装置
CN101807545A (zh) * 2010-03-22 2010-08-18 中国科学院上海微系统与信息技术研究所 二极管及电阻转换存储器的制造方法
CN102290335A (zh) * 2010-06-16 2011-12-21 三星移动显示器株式会社 使硅层结晶的方法和制造薄膜晶体管的方法

Also Published As

Publication number Publication date
CN104465319A (zh) 2015-03-25
US20160254294A1 (en) 2016-09-01
CN104465319B (zh) 2017-07-28

Similar Documents

Publication Publication Date Title
WO2016101392A1 (zh) Amoled背板的制作方法及其结构
CN103681776B (zh) 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置
WO2016065768A1 (zh) 低温多晶硅的制作方法及tft基板的制作方法
WO2016070505A1 (zh) Amoled背板的制作方法
WO2017008368A1 (zh) Tft基板的制作方法及制得的tft基板
WO2019000493A1 (zh) 薄膜晶体管阵列基板及其制备方法、oled显示装置
WO2015165164A1 (zh) 低温多晶硅薄膜晶体管及其制作方法、阵列基板和显示装置
WO2016004665A1 (zh) 低温多晶硅的制作方法及使用该方法的tft基板的制作方法与tft基板结构
WO2016101400A1 (zh) 低温多晶硅tft基板的制作方法及其结构
WO2015180450A1 (zh) 低温多晶硅薄膜晶体管及其制备方法和显示器件
WO2016101401A1 (zh) 低温多晶硅tft基板的制作方法及其结构
WO2017107274A1 (zh) 一种低温多晶硅薄膜晶体管及其制备方法
JP2005117001A (ja) ポリシリコン薄膜トランジスタの製造方法
WO2016201725A1 (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
US10699905B2 (en) Low-temperature polysilicon (LTPS), thin film transistor (TFT), and manufacturing method of array substrate
US9520421B1 (en) Method for manufacturing LTPS TFT substrate and LTPS TFT substrate
JP2010206201A (ja) 多結晶シリコン層の製造方法
WO2016206151A1 (zh) 低温多晶硅tft基板结构的制作方法及低温多晶硅tft基板结构
WO2016155055A1 (zh) 低温多晶硅tft基板结构及其制作方法
WO2014000367A1 (zh) 薄膜晶体管、阵列基板及其制造方法
US9887213B2 (en) Method for manufacturing thin film transistor and related active layer for thin film transistor, thin film transistor, array substrate, and display apparatus
WO2019000508A1 (zh) 薄膜晶体管阵列基板及其制备方法、显示装置
CN106784412B (zh) 柔性有机发光二极管显示器及其制作方法
WO2015192558A1 (zh) 低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置
CN109638174B (zh) Oled显示面板及其制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14423124

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15855474

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15855474

Country of ref document: EP

Kind code of ref document: A1