WO2016004665A1 - 低温多晶硅的制作方法及使用该方法的tft基板的制作方法与tft基板结构 - Google Patents

低温多晶硅的制作方法及使用该方法的tft基板的制作方法与tft基板结构 Download PDF

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WO2016004665A1
WO2016004665A1 PCT/CN2014/084443 CN2014084443W WO2016004665A1 WO 2016004665 A1 WO2016004665 A1 WO 2016004665A1 CN 2014084443 W CN2014084443 W CN 2014084443W WO 2016004665 A1 WO2016004665 A1 WO 2016004665A1
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layer
amorphous silicon
polysilicon
convex portion
silicon layer
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PCT/CN2014/084443
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French (fr)
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张晓星
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深圳市华星光电技术有限公司
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Publication of WO2016004665A1 publication Critical patent/WO2016004665A1/zh

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    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
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    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating low-temperature polysilicon, a method for fabricating a TFT substrate using the same, and a TFT substrate structure.
  • Low Temperature Poly-Silicon has received industry attention in liquid crystal display (LCD) and Organic Light Emitting Diode (OLED) technology due to its high electron mobility.
  • LCD liquid crystal display
  • OLED Organic Light Emitting Diode
  • low temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, low energy consumption, etc.
  • C-MOS Complementary Metal
  • Oxide Semiconductor a complementary metal oxide semiconductor circuit, has been extensively studied to meet the high resolution and low power requirements of panels.
  • Low temperature polysilicon is a branch of polysilicon technology.
  • the molecular structure of polycrystalline silicon is neat and directional in a grain, so the electron mobility is 200-300 times faster than the disordered amorphous silicon (a-Si), which greatly improves the plate. The speed of the reaction shown.
  • high temperature poly-Silicon HTPS
  • HTPS High Temperature Oxidation Process
  • low-temperature polysilicon Compared with traditional high-temperature polysilicon, low-temperature polysilicon requires laser irradiation, but it uses an excimer laser as a heat source. After the laser passes through the transmission system, it generates a laser beam with energy distribution and is projected onto the amorphous silicon structure. On the glass substrate, when the glass substrate of the amorphous silicon structure absorbs the energy of the excimer laser, it is converted into a polysilicon structure. Since the entire process is basically completed below 600 degrees Celsius, ordinary glass substrates can be tolerated, which greatly reduces manufacturing costs. In addition to lower manufacturing costs, the advantages of low-temperature polysilicon are: electron migration rate is faster and stability is higher.
  • the main methods for producing low-temperature polycrystalline silicon are: Solid Phase Crystallization (SPC), Metal-Induced Crystallization (MIC), Various methods such as Excimer Laser Annealing (EL A).
  • SPC Solid Phase Crystallization
  • MIC Metal-Induced Crystallization
  • EL A Excimer Laser Annealing
  • ELA is currently the most widely used and relatively mature method for producing low-temperature polysilicon, which uses a laser pulse to irradiate the surface of amorphous silicon to melt and recrystallize amorphous silicon.
  • the simple ELA crystallization technique cannot effectively control the crystal lattice uniformity and the crystal lattice direction, so the crystallization condition is unevenly distributed on the entire substrate, resulting in uneven display effect.
  • the conventional low-temperature polysilicon and TFT substrate manufacturing method mainly includes the following steps: Step 1. Providing a glass substrate 100; Step 2, depositing a buffer layer 200 on the glass substrate 100, the buffer The thickness of the layer 200 is uniformly hooked; Step 3, depositing an amorphous silicon layer 300 on the buffer layer 200; Step 4, performing an excimer laser annealing pretreatment on the amorphous silicon layer 300; Step 5, treating the amorphous silicon layer 300 The excimer laser annealing process is performed, and the entire surface of the amorphous silicon layer 300 is scanned by a laser beam (Laser), and the amorphous silicon layer 300 is melted and recrystallized to form a polysilicon layer 400.
  • Step 1 Providing a glass substrate 100; Step 2, depositing a buffer layer 200 on the glass substrate 100, the buffer The thickness of the layer 200 is uniformly hooked; Step 3, depositing an amorphous silicon layer 300 on the buffer layer 200; Step 4, performing an excimer laser annealing pretreatment on the
  • Step 6 Forming the polysilicon layer 400 Processing, forming a polysilicon semiconductor layer 450; step 7, sequentially forming a gate insulating layer 500, a gate 600, an insulating layer 700, a source/drain 800, the source/drain 800 and a polysilicon semiconductor layer on the polysilicon semiconductor layer 450 450 connections.
  • the amorphous silicon layer In the process of recrystallization of the amorphous silicon layer, it will crystallize according to low energy to high energy direction and low temperature to high temperature direction, and the above low temperature polysilicon and TFT substrate manufacturing method directly forms the amorphous silicon layer in the thickness uniformity
  • the heating condition of each region of the amorphous silicon layer tends to be uniform, and there is no temperature gradient, so the starting point of recrystallization and the crystallographic direction of the crystal lattice are messy, resulting in recrystallization.
  • the polycrystalline silicon layer has a small lattice size and a large number of intergranular grain boundaries. The crystallization condition is unevenly distributed over the entire substrate, affecting the electron mobility and causing uneven display effects.
  • An object of the present invention is to provide a method for fabricating low-temperature polycrystalline silicon, which can effectively control the crystal position and crystal orientation of an amorphous silicon layer when recrystallized to form a polycrystalline silicon layer, reduce the number of grain boundaries, and distribute the crystal state on the entire substrate. More uniform.
  • Another object of the present invention is to provide a method for fabricating a TF T substrate using the method for fabricating the low-temperature polysilicon, which can effectively control the crystal position and crystal orientation of the amorphous silicon layer when recrystallized to form a polysilicon layer, and reduce the channel.
  • the number of grain boundaries in the region, making the crystallization state throughout the substrate The distribution on the top is relatively uniform, improving the performance of the TFT substrate.
  • Another object of the present invention is to provide a TFT substrate structure which can improve electron mobility, improve performance of a TFT substrate, and improve display performance.
  • the present invention provides a method for fabricating low temperature polysilicon, comprising the steps of:
  • Step 1 providing a substrate
  • Step 2 depositing a buffer layer on the substrate
  • Step 3 patterning the buffer layer to form protrusions and depressions having different thicknesses
  • Step 4 depositing an amorphous silicon layer on the buffer layer having the convex portion and the depressed portion;
  • Step 5 performing an excimer laser annealing pretreatment on the amorphous silicon layer;
  • Step 6 Perform an excimer laser annealing process on the amorphous silicon layer, and scan the entire surface of the amorphous silicon layer with a laser beam to melt and recrystallize the amorphous silicon layer to form a polysilicon layer.
  • the material of the buffer layer is SiNx, SiOx, or a combination of SiNx and SiOx.
  • the arrangement direction of the convex portion and the concave portion in the step 3 is the same as the alignment direction of the laser beam in the step 6 and perpendicular to the scanning direction of the laser beam; the arrangement direction of the convex portion and the concave portion in the step 3 Corresponding to the channel length direction of the polysilicon semiconductor layer to be formed.
  • the thickness difference between the convex portion and the concave portion is greater than 500A; in the step 6, the amorphous silicon layer is melted and recrystallized to form a polysilicon layer, and the amorphous silicon located in the depressed portion is first crystallized, and then bulged along the depressed portion. The direction of the part is crystallized.
  • the present invention also provides a method of fabricating a TFT substrate using the method for fabricating the low-temperature polysilicon, comprising the steps of:
  • Step 1 providing a substrate
  • Step 2 depositing a buffer layer on the substrate
  • Step 3 patterning the buffer layer to form protrusions and depressions having different thicknesses
  • Step 4 depositing an amorphous silicon layer on the buffer layer having the convex portion and the depressed portion;
  • Step 5 performing an excimer laser annealing pretreatment on the amorphous silicon layer;
  • Step 6 performing an excimer laser annealing process on the amorphous silicon layer, scanning the entire surface of the amorphous silicon layer with a laser beam, and melting and recrystallizing the amorphous silicon layer to form a polysilicon layer;
  • Step 7 forming a polysilicon layer to form a polysilicon semiconductor layer
  • Step 8 Form a gate insulating layer, a gate electrode, an insulating layer, and a source/drain sequentially on the polysilicon semiconductor layer, and the source/drain is connected to the polysilicon semiconductor layer.
  • the material of the buffer layer is SiNx, SiOx, or a combination of SiNx and SiOx.
  • the arrangement direction of the convex portion and the concave portion in the step 3 is the same as the alignment direction of the laser beam in the step 6 and perpendicular to the scanning direction of the laser beam; the arrangement direction of the convex portion and the concave portion in the step 3 Corresponding to the channel length direction of the polycrystalline silicon semiconductor layer formed in step 7.
  • the thickness difference between the convex portion and the concave portion is greater than 500A; in the step 6, the amorphous silicon layer is melted and recrystallized to form a polysilicon layer, and the amorphous silicon located in the depressed portion is first crystallized, and then bulged along the depressed portion. The direction of the part is crystallized.
  • the present invention also provides a TFT substrate structure fabricated by the method for fabricating the TFT substrate, comprising: a substrate, a buffer layer on the substrate, a polysilicon semiconductor layer on the buffer layer, and a polysilicon semiconductor layer a gate insulating layer on the layer and the buffer layer, a gate on the gate insulating layer, an insulating layer on the gate and the gate insulating layer, and a source/drain on the insulating layer, the source/ The drain is connected to the polysilicon semiconductor layer, and the buffer layer has convex portions and depressed portions having different thicknesses.
  • the direction in which the protrusions and the recesses are arranged corresponds to the channel length direction of the polysilicon semiconductor layer, the difference in thickness between the protrusions and the recesses is greater than 500 A, and the material of the buffer layer is SiNx, SiOx, or A combination of SiNx and SiOx.
  • the method for fabricating low-temperature polysilicon of the present invention by patterning a buffer layer, forming protrusions and depressions having different thicknesses, so that during laser excimer annealing, the protrusions
  • the heat preservation effect is better than the heat preservation effect of the depressed portion, thereby forming a temperature gradient, thereby effectively controlling the crystallization position and the crystal direction when the amorphous silicon layer is recrystallized to form the polycrystalline silicon layer, reducing the number of grain boundaries, and making the crystallization state on the entire substrate.
  • the distribution is relatively uniform, and the method is simple and easy to work.
  • the buffer layer is patterned to form protrusions and depressions having different thicknesses, so that during laser excimer annealing, the protrusions
  • the thermal insulation effect of the part is better than that of the concave part, thus forming a temperature gradient, which effectively controls the crystal position and crystal direction of the polycrystalline silicon layer when the amorphous silicon layer is recrystallized, reduces the number of grain boundaries in the channel region, and causes crystallization.
  • the condition is evenly distributed over the entire substrate, improving the performance of the TFT substrate.
  • the buffer layer has convex portions and recess portions having different thicknesses, so that the polycrystalline silicon semiconductor layer on the buffer layer is crystallized during formation.
  • the position and crystal orientation are effectively controlled, and the number of grain boundaries in the channel region is reduced, thereby having a high electron mobility, which can improve the performance of the TFT substrate and improve the display effect.
  • FIG. 1 is a schematic cross-sectional view showing a step 2 of a conventional method for fabricating a low temperature polysilicon and a TFT substrate;
  • FIG. 2 is a schematic cross-sectional view showing a step 3 of a conventional method for fabricating a low temperature polysilicon and a TFT substrate;
  • FIG. 3 is a schematic cross-sectional view showing a step 5 of a conventional method for fabricating a low temperature polysilicon and a TFT substrate;
  • FIG. 4 is a schematic cross-sectional view showing a step 6 of a conventional method for fabricating a low temperature polysilicon and a TFT substrate;
  • FIG. 5 is a schematic cross-sectional view showing a step 7 of a conventional method for fabricating a low temperature polysilicon and a TFT substrate;
  • FIG. 6 is a flow chart of a method for fabricating low temperature polysilicon according to the present invention.
  • FIG. 7 is a flow chart showing a method of fabricating a TFT substrate using the low temperature polysilicon manufacturing method of the present invention.
  • FIG. 8 is a schematic cross-sectional view showing a step 2 of a method for fabricating a low temperature polycrystalline silicon according to the present invention and a method for fabricating a TFT substrate using the same;
  • FIG. 9 is a schematic cross-sectional view showing a step 3 of a method for fabricating a low temperature polycrystalline silicon according to the present invention and a method for fabricating a TFT substrate using the same;
  • FIG. 10 is a top plan view showing a step 3 of a method for fabricating a low temperature polycrystalline silicon according to the present invention and a method for fabricating a TFT substrate using the same;
  • FIG. 11 is a cross-sectional view showing a step 4 of a method for fabricating a low temperature polycrystalline silicon according to the present invention and a method for fabricating a TFT substrate using the same;
  • FIG. 12 is a schematic cross-sectional view showing a step 6 of a method for fabricating a low temperature polycrystalline silicon according to the present invention and a method for fabricating a TFT substrate using the same;
  • FIG. 13 is a top plan view showing a step 6 of a method for fabricating a low temperature polycrystalline silicon according to the present invention and a method for fabricating a TFT substrate using the same;
  • FIG. 14 is a cross-sectional view showing a step 7 of a method for fabricating a TFT substrate using the method for fabricating the low-temperature polysilicon;
  • 15 is a top plan view showing a step 7 of a method for fabricating a TFT substrate using the method for fabricating the low-temperature polysilicon;
  • 16 is a cross-sectional view showing a step 8 of a method for fabricating a TFT substrate using the method for fabricating the low-temperature polysilicon, and a cross-sectional view showing the structure of the TFT substrate of the present invention.
  • the present invention provides a method for fabricating low temperature polysilicon, including the following steps:
  • Step 1 Provide a substrate 1.
  • the substrate 1 is a transparent substrate.
  • the substrate 1 is a glass substrate.
  • Step 2 Deposit a buffer layer 2 on the substrate 1.
  • the thickness of the buffer layer 2 formed by deposition in this step 2 is uniformly hooked.
  • the material of the buffer layer 2 is SiNx, SiOx, or a combination of SiNx and SiOx.
  • Step 3 The buffer layer 2 is patterned to form the convex portion 21 and the depressed portion 23 having different thicknesses.
  • the thickness difference is more than 500A.
  • the arrangement direction of the convex portion 21 and the concave portion 23 is the same as the alignment direction of the laser beam in the subsequent step 6, and is perpendicular to the scanning direction of the laser beam, and the groove of the polysilicon semiconductor layer to be formed.
  • the length of the track corresponds to the direction.
  • Step 4 Depositing an amorphous silicon layer on the buffer layer 2 having the convex portion 21 and the depressed portion 23
  • the thickness of the amorphous silicon layer 3 located at the convex portion 21 coincides with the thickness of the amorphous silicon layer 3 located at the depressed portion 23.
  • Step 5 Perform an excimer laser annealing pretreatment on the amorphous silicon layer 3.
  • Step 6 Perform an excimer laser annealing process on the amorphous silicon layer 3, and scan the entire surface of the amorphous silicon layer 3 with a laser beam to melt and recrystallize the amorphous silicon layer 3 to form a polysilicon layer 4.
  • this step 6 performs an excimer laser annealing process on the amorphous silicon layer 3, and scans the entire surface of the amorphous silicon layer 3 using a laser beam.
  • the arrangement direction of the laser beam coincides with the channel length direction of the polysilicon semiconductor layer to be formed, and the scanning direction of the laser beam is perpendicular to the channel length direction of the polysilicon semiconductor layer to be formed.
  • the amorphous silicon layer 3 absorbs the energy of the laser beam and then the temperature rises to a molten state and undergoes recrystallization.
  • the convex portion 21 is thicker, the heat insulating effect is better, and the amorphous silicon layer 3 located in the convex portion 21 has a higher temperature and is more completely melted; the depressed portion 23 is thinner and has a poor heat preservation effect.
  • the temperature of the amorphous silicon layer 3 of the depressed portion 23 is relatively low, the melting is relatively incomplete, and a temperature gradient is formed between the convex portion 21 and the depressed portion 23. Since the amorphous silicon crystallizes in the process of recrystallization from low energy to high energy direction and low temperature to high temperature, the amorphous silicon located in the depressed portion 23 having a relatively low temperature is first crystallized, and then follows the direction from low to high.
  • Crystallization that is, crystallization along the direction from the depressed portion 23 toward the convex portion 21, and finally the lattice is in the channel
  • the middle portions in the longitudinal direction meet, thereby effectively controlling the crystal position and the crystal orientation of the amorphous silicon layer 3 when recrystallized to form the polysilicon layer 4, reducing the number of grain boundaries, and uniformly distributing the crystal state on the entire substrate. .
  • the present invention further provides a method for fabricating a TFT substrate using the method, including the following steps:
  • Step 1 Provide a substrate 1.
  • the substrate 1 is a transparent substrate.
  • the substrate 1 is a glass substrate.
  • Step 2 Deposit a buffer layer 2 on the substrate 1.
  • the thickness of the buffer layer 2 formed by deposition in this step 2 is uniformly hooked.
  • the material of the buffer layer 2 is SiNx, SiOx, or a combination of SiNx and SiOx.
  • Step 3 The buffer layer 2 is patterned to form the convex portion 21 and the depressed portion 23 having different thicknesses.
  • the thickness difference is more than 500A.
  • the arrangement direction of the convex portion 21 and the concave portion 23 is the same as the alignment direction of the laser beam in the subsequent step 6, but perpendicular to the scanning direction of the laser beam, and the polysilicon semiconductor formed in the subsequent step 7.
  • the channel 45 has a channel length direction corresponding thereto.
  • Step 4 Depositing an amorphous silicon layer on the buffer layer 2 having the convex portion 21 and the depressed portion 23
  • the thickness of the amorphous silicon layer 3 located at the convex portion 21 is the same as the thickness of the amorphous silicon layer 3 located at the depressed portion 23.
  • Step 5 Perform an excimer laser annealing pretreatment on the amorphous silicon layer 3.
  • Step 6 Perform an excimer laser annealing process on the amorphous silicon layer 3, and scan the entire surface of the amorphous silicon layer 3 with a laser beam to melt and recrystallize the amorphous silicon layer 3 to form a polysilicon layer 4.
  • this step 6 performs an excimer laser annealing process on the amorphous silicon layer 3, and scans the entire surface of the amorphous silicon layer 3 using a laser beam.
  • the arrangement direction of the laser beam coincides with the channel length direction of the polycrystalline silicon semiconductor layer 45 formed in the subsequent step 7, and the scanning direction of the laser beam is perpendicular to the channel length direction of the polycrystalline silicon semiconductor layer 45 formed in the subsequent step 7.
  • the amorphous silicon layer 3 absorbs the energy of the laser beam and then the temperature rises to a molten state and is recrystallized.
  • the convex portion 21 is thicker, the heat insulating effect is better, and the amorphous silicon layer 3 located in the convex portion 21 has a higher temperature and is more completely melted; the depressed portion 23 is thinner, and the heat insulating effect is poor.
  • the temperature of the amorphous silicon layer 3 of the depressed portion 23 is relatively low, the melting is relatively incomplete, and a temperature gradient is formed between the convex portion 21 and the depressed portion 23. Since the amorphous silicon is crystallized in a high energy direction and a low temperature toward a high temperature in the process of recrystallization, the amorphous silicon located in the depressed portion 23 having a relatively low temperature is first crystallized.
  • the crystal is crystallized in a direction from low to high, that is, crystallized in a direction from the depressed portion 23 toward the convex portion 21, and finally the crystal lattice meets in the middle portion in the channel length direction, thereby being heavy on the amorphous silicon layer 3
  • the crystal position and crystal orientation of the polycrystalline silicon layer 4 are effectively controlled, and the number of grain boundaries in the channel region is reduced, so that the distribution of the crystal state on the entire substrate is relatively uniform.
  • Step 7 As shown in Figs. 14 and 15, the polysilicon layer 4 is subjected to a forming process to form a polycrystalline silicon semiconductor layer 45.
  • Step 8 as shown in FIG. 16, a gate insulating layer 5, a gate electrode 6, an insulating layer 7, and a source/drain 8 are sequentially formed on the polysilicon semiconductor layer 45.
  • the source/drain electrodes 8 are connected to the polysilicon semiconductor layer 45. .
  • the present invention also provides a TFT substrate structure fabricated by the method of fabricating the TFT substrate.
  • the TFT substrate structure includes: a substrate 1, a buffer layer 2 on the substrate 1, and a buffer layer.
  • the polycrystalline silicon semiconductor layer 45 on the second, the buffer layer 2 has convex portions 21 and depressed portions 23 having different thicknesses.
  • the buffer layer 2 Since the buffer layer 2 has the protrusions 21 and the recesses 23 having different thicknesses, the crystallization position and the crystal orientation of the polysilicon semiconductor layer 45 located on the buffer layer 2 are effectively controlled, and the channel region is obtained. The number of grain boundaries is reduced, thereby having a high electron mobility, which can improve the performance of the TFT substrate and improve the display effect.
  • the TFT substrate structure further includes a gate insulating layer 5 on the polysilicon peninsula body layer 45 and the buffer layer 2, a gate electrode 6 on the gate insulating layer 5, and a gate electrode 6 and a gate insulating layer 5.
  • the insulating layer 7 and the source/drain electrodes 8 on the insulating layer 7 are connected to the polysilicon semiconductor layer 45.
  • the arrangement direction of the convex portion 21 and the concave portion 23 corresponds to the channel length direction of the polycrystalline silicon semiconductor layer 45.
  • the difference in thickness between the raised portion 21 and the recessed portion 23 is greater than 500A.
  • the material of the buffer layer 2 is SiNx, SiOx, or a combination of SiNx and SiOx.
  • the method for fabricating the low-temperature polysilicon of the present invention forms a convex portion and a depressed portion having different thicknesses by patterning the buffer layer, so that the thermal insulation of the convex portion during the laser excimer annealing process The effect is better than the heat preservation effect of the depressed portion, thereby forming a temperature gradient, thereby effectively controlling the crystal position and the crystal direction when the amorphous silicon layer is recrystallized to form the polycrystalline silicon layer, reducing the number of grain boundaries, and distributing the crystal state on the entire substrate. More uniform, and the method is simple and easy to work.
  • the buffer layer is patterned to form protrusions and depressions having different thicknesses, so that during laser excimer annealing, the protrusions
  • the thermal insulation effect of the part is better than that of the concave part, thus forming a temperature gradient, which effectively controls the crystal position and crystal direction of the polycrystalline silicon layer when the amorphous silicon layer is recrystallized, reduces the number of grain boundaries in the channel region, and causes crystallization.
  • the situation is The distribution on the entire substrate is relatively uniform, improving the performance of the TFT substrate.
  • the buffer layer has convex portions and recess portions having different thicknesses, so that the polycrystalline silicon semiconductor layer on the buffer layer is crystallized during formation.
  • the position and crystal orientation are effectively controlled, and the number of grain boundaries in the channel region is reduced, thereby having a high electron mobility, which can improve the performance of the TFT substrate and improve the display effect.

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Abstract

一种低温多晶硅的制作方法及使用该方法的TFT基板的制作方法与TFT基板结构，该低温多晶硅的制作方法包括如下步骤：步骤1、提供一基板（1）；步骤2、在基板（1）上沉积形成缓冲层（2）；步骤3、对缓冲层（2）进行图案化处理，形成具有不同厚度的凸起部（21）与凹陷部（23）；步骤4、在具有凸起部（21）与凹陷部（23）的缓冲层（2）上沉积形成非晶硅层（3）；步骤5、对非晶硅层（3）进行准分子激光退火预处理；步骤6、对非晶硅层（3）进行准分子激光退火制程，使用激光束对非晶硅层（3）整面进行扫描，使非晶硅层（3）熔融并重结晶形成多晶硅层（4）。该方法能够对非晶硅层重结晶时的结晶位置和结晶方向进行有效控制。

Description

低温多晶硅的制作方法及使用该方法的 TFT基板的制作方法与
TFT基板结构
技术领域
本发明涉及显示技术领域， 尤其涉及一种低温多晶硅的制作方法及使 用该方法的 TFT基板的制作方法与 TFT基板结构。 背景技术
随着平板显示的发展， 高分辨率， 低能耗的面板需求不断被提出。 低 温多晶硅 （Low Temperature Poly-Silicon, LTPS) 由于具有较高的电子迁移 率， 而在液晶显示器 （Liquid Crystal Display, LCD) 与有机发光二极管显 示器 Organic Light Emitting Diode, OLED) 技术中得到了业界的重视， 被 视为实现低成本全彩平板显示的重要材料。 对平板显示而言， 采用低温多 晶硅材料具有高分辨率、 反应速度快、 高亮度、 高开口率、 低能耗等优点， 而且低温多晶硅可在低温下制作， 并可用于制作 C-MOS (Complementary Metal Oxide Semiconductor, 互补金属氧化物半导体） 电路， 因而被广泛研 究， 用以达到面板高分辨率， 低能耗的需求。
低温多晶硅是多晶硅技术的一个分支。 多晶硅的分子结构在一颗晶粒 中的排列状态是整齐而有方向性的， 因此电子迁移率比排列杂乱的非晶硅 (a-Si) 快了 200-300倍， 极大的提高了平板显示的反应速度。 在多晶硅技 术发展的初期， 为了将玻璃基板从非晶硅结构转变为多晶硅结构， 就必须 借助一道激光退火（Laser Anneal)的高温氧化工序， 制得高温多晶硅（High Temperature Poly-Silicon, HTPS) ,此时玻璃基板的温度将超过摄氏 1000度。 与传统的高温多晶硅相比， 低温多晶硅虽然也需要激光照射， 但它采用的 是准分子激光作为热源， 激光经过透射系统后， 会产生能量均勾分布的激 光束并被投射于非晶硅结构的玻璃基板上， 当非晶硅结构的玻璃基板吸收 准分子激光的能量后， 就会转变成为多晶硅结构。 由于整个处理过程基本 是在摄氏 600 度以下完成， 一般普通的玻璃基板均可承受， 这就大大降低 了制造成本。 而除了制造成本降低外， 低温多晶硅的优点还体现在： 电子 迁移速率更快、 稳定性更高。
目前制作低温多晶硅的方法主要有： 固相结晶 （ Solid Phase Crystallization, SPC)、 金属诱导结晶 （Metal-Induced Crystallization, MIC) , 与准分子激光退火 （Excimer Laser Annealing, EL A) 等多种制作方法。 其 中， ELA是目前使用最为广泛、 相对成熟的制作低温多晶硅的方法， 其利 用激光的瞬间脉冲照射到非晶硅表面， 使非晶硅熔化并重新结晶。 但是单 纯的 ELA结晶技术对于晶格的均一性和晶格结晶方向不能做到有效控制， 所以结晶状况在整个基板的分布上很不均勾， 造成显示效果的不均一。
如图 1-5所示， 传统的低温多晶硅及 TFT基板的制作方法主要包括如 下步骤： 步骤 1、 提供一玻璃基板 100 ; 步骤 2、 在玻璃基板 100上沉积形 成緩冲层 200， 该緩冲层 200的厚度均勾； 步骤 3、 在緩冲层 200上沉积形 成非晶硅层 300 ; 步骤 4、 对非晶硅层 300进行准分子激光退火预处理； 步 骤 5、 对非晶硅层 300进行准分子激光退火制程， 使用激光束 （Laser) 对 非晶硅层 300整面进行扫描 （Scan) , 使非晶硅层 300熔融并重结晶形成多 晶硅层 400 ; 步骤 6、 对多晶硅层 400进行成形处理， 形成多晶硅半导体层 450 ;步骤 7、在多晶硅半导体层 450上依次形成栅极绝缘层 500、栅极 600、 绝缘层 700、 源 /漏极 800， 所述源 /漏极 800与多晶硅半导体层 450连接。
由于在非晶硅层重结晶的过程中， 会按照低能量向高能量方向、 低温 向高温方向结晶， 而上述低温多晶硅及 TFT基板的制作方法将非晶硅层直 接形成于厚度均勾的緩冲层上， 在准分子激光退火的过程中， 非晶硅层各 个区域的受热情况趋于一致， 不存在温度梯度， 所以重结晶的起点与晶格 的结晶方向是凌乱的， 导致重结晶后的多晶硅层晶格尺寸偏小， 晶格间晶 界偏多， 结晶状况在整个基板的分布上很不均勾， 影响电子迁移率， 造成 显示效果的不均一。
为了获取更好的多晶硅， 诞生了一些侧向结晶技术， 以期可以更好的 控制晶格和晶向的均一性，比如， SLS方式的结晶技术，或者 mask shield 方 式的结晶技术， 还有部分定点对非晶硅加厚的方式后做 ELA晶化。 但是这 些方式都需要额外的技术和工艺， 而且对 mask的精度要求十分严苛， 导致 量产困难。 发明内容
本发明的目的在于提供一种低温多晶硅的制作方法， 能够对非晶硅层 重结晶形成多晶硅层时的结晶位置和结晶方向进行有效控制， 减少晶界数 量， 使结晶状况在整个基板上的分布较均匀。
本发明的另一目的在于提供一种使用该低温多晶硅的制作方法的 TF T 基板的制作方法， 能够对非晶硅层重结晶形成多晶硅层时的结晶位置和结 晶方向进行有效控制， 减少沟道区域的晶界数量， 使结晶状况在整个基板 上的分布较均匀， 提高 TFT基板的性能。
本发明的目的还在于提供一种 TFT基板结构， 能够提高电子迁移率， 提高 TFT基板的性能， 改善显示效果。
为实现上述目的， 本发明提供一种低温多晶硅的制作方法， 包括如下 步骤：
步骤 1、 提供一基板；
步骤 2、 在基板上沉积形成緩冲层；
步骤 3、 对緩冲层进行图案化处理， 形成具有不同厚度的凸起部与凹陷 部；
步骤 4、 在具有凸起部与凹陷部的緩冲层上沉积形成非晶硅层； 步骤 5、 对非晶硅层进行准分子激光退火预处理；
步骤 6、 对非晶硅层进行准分子激光退火制程， 使用激光束对非晶硅层 整面进行扫描， 使非晶硅层熔融并重结晶形成多晶硅层。
所述緩冲层的材料为 SiNx 、 SiOx、 或者 SiNx与 SiOx的组合。
所述步骤 3 中的凸起部与凹陷部的排列方向与步骤 6 中激光束的排列 方向一致， 而与激光束的扫描方向垂直； 所述步骤 3 中的凸起部与凹陷部 的排列方向与欲形成的多晶硅半导体层的沟道长度方向相对应。
所述凸起部与凹陷部的厚度差大于 500A; 所述步骤 6中非晶硅层熔融 并重结晶形成多晶硅层， 位于凹陷部的非晶硅先进行结晶， 之后沿着由凹 陷部向凸起部的方向结晶。
本发明还提供一种使用该低温多晶硅的制作方法的 TFT基板的制作方 法， 包括如下步骤：
步骤 1、 提供一基板；
步骤 2、 在基板上沉积形成緩冲层；
步骤 3、 对緩冲层进行图案化处理， 形成具有不同厚度的凸起部与凹陷 部；
步骤 4、 在具有凸起部与凹陷部的緩冲层上沉积形成非晶硅层； 步骤 5、 对非晶硅层进行准分子激光退火预处理；
步骤 6、 对非晶硅层进行准分子激光退火制程， 使用激光束对非晶硅层 整面进行扫描， 使非晶硅层熔融并重结晶形成多晶硅层；
步骤 7、 对多晶硅层进行成形处理， 形成多晶硅半导体层；
步骤 8、 在多晶硅半导体层上依次形成栅极绝缘层、 栅极、 绝缘层、 源 /漏极， 所述源 /漏极与多晶硅半导体层连接。
所述緩冲层的材料为 SiNx 、 SiOx、 或者 SiNx与 SiOx的组合。 所述步骤 3 中的凸起部与凹陷部的排列方向与步骤 6 中激光束的排列 方向一致， 而与激光束的扫描方向垂直； 所述步骤 3 中的凸起部与凹陷部 的排列方向与步骤 7形成的多晶硅半导体层的沟道长度方向相对应。
所述凸起部与凹陷部的厚度差大于 500A; 所述步骤 6中非晶硅层熔融 并重结晶形成多晶硅层， 位于凹陷部的非晶硅先进行结晶， 之后沿着由凹 陷部向凸起部的方向结晶。
本发明还提供一种由该 TFT 基板的制作方法制作而成的 TFT 基板结 构， 包括： 包括一基板、 位于基板上的緩冲层、 位于緩冲层上的多晶硅半 导体层、 位于多晶硅半 ^体层与緩冲层上的栅极绝缘层、 位于栅极绝缘层 上的栅极、位于栅极与栅极绝缘层上的绝缘层， 及位于绝缘层上的源 /漏极， 所述源 /漏极与所述多晶硅半导体层连接， 所述緩冲层具有厚度不同的凸起 部与凹陷部。
所述凸起部与凹陷部的排列方向与多晶硅半导体层的沟道长度方向相 对应， 所述凸起部与凹陷部的厚度差大于 500A, 所述緩冲层的材料为 SiNx 、 SiOx、 或者 SiNx与 SiOx的组合。
本发明的有益效果： 本发明的低温多晶硅的制作方法， 通过对緩冲层 进行图案化处理， 形成具有不同厚度的凸起部与凹陷部， 使得在激光准分 子退火过程中， 凸起部的保温效果优于凹陷部的保温效果， 从而构成温度 梯度， 实现对非晶硅层重结晶形成多晶硅层时的结晶位置和结晶方向进行 有效控制， 减少晶界数量， 使结晶状况在整个基板上的分布较均勾， 且该 方法简便、 易于搡作。 本发明的使用该低温多晶硅的制作方法的 TFT基板 的制作方法， 通过对緩冲层进行图案化处理， 形成具有不同厚度的凸起部 与凹陷部， 使得在激光准分子退火过程中， 凸起部的保温效果优于凹陷部 的保温效果， 从而构成温度梯度， 实现对非晶硅层重结晶形成多晶硅层时 的结晶位置和结晶方向进行有效控制， 减少沟道区域的晶界数量， 使结晶 状况在整个基板上的分布较均匀，提高 TFT基板的性能。本发明的由该 TFT 基板的制作方法制作而成的 TFT基板结构， 其緩冲层具有厚度不同的凸起 部与凹陷部， 使得位于该緩冲层上的多晶硅半导体层在形成过程中的结晶 位置和结晶方向得到有效控制， 沟道区域的晶界数量得以减少， 从而具有 较高的电子迁移率， 能够提高 TFT基板的性能， 改善显示效果。 附图说明
为了能更进一步了解本发明的特征以及技术内容， 请参阅以下有关本 发明的详细说明与附图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。
附图中，
图 1为传统的低温多晶硅及 TFT基板的制作方法的步骤 2的剖面示意 图；
图 2为传统的低温多晶硅及 TFT基板的制作方法的步骤 3的剖面示意 图；
图 3为传统的低温多晶硅及 TFT基板的制作方法的步骤 5的剖面示意 图；
图 4为传统的低温多晶硅及 TFT基板的制作方法的步骤 6的剖面示意 图；
图 5为传统的低温多晶硅及 TFT基板的制作方法的步骤 7的剖面示意 图；
图 6为本发明低温多晶硅的制作方法的流程图；
图 7为本发明使用该低温多晶硅的制作方法的 TFT基板的制作方法的 流程图；
图 8为本发明低温多晶硅的制作方法及使用该方法的 TFT基板的制作 方法的步骤 2的剖面示意图；
图 9为本发明低温多晶硅的制作方法及使用该方法的 TFT基板的制作 方法的步骤 3的剖面示意图；
图 10为本发明低温多晶硅的制作方法及使用该方法的 TFT基板的制作 方法的步骤 3的俯视示意图；
图 11为本发明低温多晶硅的制作方法及使用该方法的 TFT基板的制作 方法的步骤 4的剖面示意图；
图 12为本发明低温多晶硅的制作方法及使用该方法的 TFT基板的制作 方法的的步骤 6的剖面示意图；
图 13为本发明低温多晶硅的制作方法及使用该方法的 TFT基板的制作 方法的的步骤 6的俯视示意图；
图 14为本发明使用该低温多晶硅的制作方法的 TFT基板的制作方法的 步骤 7的剖面示意图；
图 15为本发明使用该低温多晶硅的制作方法的 TFT基板的制作方法的 步骤 7的俯视示意图；
图 16为本发明使用该低温多晶硅的制作方法的 TFT基板的制作方法的 步骤 8的剖面示意图暨本发明 TFT基板结构的剖面示意图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果， 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 6及图 8至图 13， 本发明提供一种低温多晶硅的制作方法， 包括如下步骤：
步骤 1、 提供一基板 1。
所述基板 1为透明基板， 优选的， 所述基板 1为玻璃基板。
步骤 2、 在基板 1上沉积形成緩冲层 2。
如图 8所示， 在该步骤 2 中沉积形成的緩冲层 2的厚度是均勾的。 所 述緩冲层 2的材料为 SiNx 、 SiOx、 或者 SiNx与 SiOx的组合。
步骤 3、 对緩冲层 2进行图案化处理， 形成具有不同厚度的凸起部 21 与凹陷部 23。
如图 9、 图 10所示， 所述凸起部 21与凹陷部 23之间存在厚度差， 具 体的， 该厚度差大于 500A。 特别需要说明的是， 所述凸起部 21 与凹陷部 23的排列方向与后续步骤 6中激光束的排列方向一致， 而与激光束的扫描 方向垂直， 且与欲形成的多晶硅半导体层的沟道长度方向相对应。
步骤 4、在具有凸起部 21与凹陷部 23的緩冲层 2上沉积形成非晶硅层
3 o
如图 11所示， 在该步骤 4 中， 位于所述凸起部 21 的非晶硅层 3与位 于所述凹陷部 23的非晶硅层 3的厚度是一致的。
步骤 5、 对非晶硅层 3进行准分子激光退火预处理。
步骤 6、 对非晶硅层 3进行准分子激光退火制程， 使用激光束对非晶硅 层 3整面进行扫描， 使非晶硅层 3熔融并重结晶形成多晶硅层 4。
如图 12、图 13所示，该步骤 6对非晶硅层 3进行准分子激光退火制程， 使用激光束对非晶硅层 3 整面进行扫描。 激光束的排列方向与欲形成的多 晶硅半导体层的沟道长度方向一致， 激光束的扫描方向与欲形成的多晶硅 半导体层的沟道长度方向垂直。 所述非晶硅层 3 吸收激光束的能量后温度 升高直至熔融状态并进行重结晶。 由于所述凸起部 21处较厚， 保温效果较 好， 位于凸起部 21 的非晶硅层 3 温度较高， 熔化较完全； 所述凹陷部 23 处较薄， 保温效果较差， 位于凹陷部 23的非晶硅层 3温度相对较低， 熔化 相对不完全， 所述凸起部 21 与凹陷部 23之间形成了温度梯度。 由于非晶 硅重结晶过程中会按照低能量向高能量方向、 低温向高温方向结晶， 位于 温度相对较低的凹陷部 23的非晶硅先进行结晶， 之后沿着温度由低到高的 方向结晶， 即沿着由凹陷部 23 向凸起部 21 的方向结晶， 最终晶格在沟道 长度方向的中部相遇， 从而对所述非晶硅层 3重结晶形成多晶硅层 4时的 结晶位置和结晶方向进行了有效控制， 减少了晶界数量， 使结晶状况在整 个基板上的分布较均匀。
请参阅图 7至图 16， 在上述低温多晶硅的制作方法的基础上， 本发明 还提供一种使用该方法的 TFT基板的制作方法， 包括如下步骤：
步骤 1、 提供一基板 1。
所述基板 1为透明基板， 优选的， 所述基板 1为玻璃基板。
步骤 2、 在基板 1上沉积形成緩冲层 2。
如图 8所示， 在该步骤 2中沉积形成的緩冲层 2的厚度是均勾的。 所 述緩冲层 2的材料为 SiNx 、 SiOx、 或者 SiNx与 SiOx的组合。
步骤 3、 对緩冲层 2进行图案化处理， 形成具有不同厚度的凸起部 21 与凹陷部 23。
如图 9、 图 10所示， 所述凸起部 21与凹陷部 23之间存在厚度差， 具 体的， 该厚度差大于 500A。 特别需要说明的是， 所述凸起部 21 与凹陷部 23的排列方向与后续步骤 6中激光束的排列方向一致， 而与激光束的扫描 方向垂直， 且与后续步骤 7中形成的多晶硅半导体层 45的沟道长度方向相 对应。
步骤 4、在具有凸起部 21与凹陷部 23的緩冲层 2上沉积形成非晶硅层
3 o
如图 11所示， 在该步骤 4中， 位于所述凸起部 21的非晶硅层 3与位 于所述凹陷部 23的非晶硅层 3的厚度是一致的。
步骤 5、 对非晶硅层 3进行准分子激光退火预处理。
步骤 6、对非晶硅层 3进行准分子激光退火制程， 使用激光束对非晶硅 层 3整面进行扫描， 使非晶硅层 3熔融并重结晶形成多晶硅层 4。
如图 12、图 13所示，该步骤 6对非晶硅层 3进行准分子激光退火制程， 使用激光束对非晶硅层 3 整面进行扫描。 激光束的排列方向与后续步骤 7 中形成的多晶硅半导体层 45的沟道长度方向一致， 激光束的扫描方向与后 续步骤 7中形成的多晶硅半导体层 45的沟道长度方向垂直。 所述非晶硅层 3吸收激光束的能量后温度升高直至熔融状态并进行重结晶。由于所述凸起 部 21处较厚， 保温效果较好， 位于凸起部 21的非晶硅层 3温度较高， 熔 化较完全； 所述凹陷部 23处较薄， 保温效果较差， 位于凹陷部 23的非晶 硅层 3温度相对较低， 熔化相对不完全， 所述凸起部 21与凹陷部 23之间 形成了温度梯度。 由于非晶硅重结晶过程中会按照低能量向高能量方向、 低温向高温方向结晶，位于温度相对较低的凹陷部 23的非晶硅先进行结晶， 之后沿着温度由低到高的方向结晶， 即沿着由凹陷部 23 向凸起部 21 的方 向结晶， 最终晶格在沟道长度方向的中部相遇， 从而对所述非晶硅层 3 重 结晶形成多晶硅层 4 时的结晶位置和结晶方向进行了有效控制， 减少了沟 道区域的晶界数量， 使结晶状况在整个基板上的分布较均匀。
步骤 7、 如图 14、 图 15所示， 对多晶硅层 4进行成形处理， 形成多晶 硅半导体层 45。
步骤 8、如图 16所示，在多晶硅半导体层 45上依次形成栅极绝缘层 5、 栅极 6、 绝缘层 7、 源 /漏极 8， 所述源 /漏极 8与多晶硅半导体层 45连接。
本发明还提供一种由该 TFT 基板的制作方法制作而成的 TFT 基板结 构， 请参阅图 16， 该 TFT基板结构包括： 一基板 1、 位于基板 1上的緩冲 层 2、 位于緩冲层 2上的多晶硅半导体层 45， 所述緩冲层 2具有厚度不同 的凸起部 21与凹陷部 23。
由于所述緩冲层 2具有厚度不同的凸起部 21与凹陷部 23，使得位于该 緩冲层 2上的多晶硅半导体层 45在形成过程中的结晶位置和结晶方向得到 有效控制， 沟道区域的晶界数量得以减少， 从而具有较高的电子迁移率， 能够提高 TFT基板的性能， 改善显示效果。
所述 TFT基板结构，还包括位于多晶硅半岛体层 45与緩冲层 2上的栅 极绝缘层 5、 位于栅极绝缘层 5上的栅极 6、 位于栅极 6与栅极绝缘层 5上 的绝缘层 7， 及位于绝缘层 7上的源 /漏极 8， 所述源 /漏极 8与所述多晶硅 半导体层 45连接。
所述凸起部 21与凹陷部 23的排列方向与多晶硅半导体层 45的沟道长 度方向相对应。
所述凸起部 21与凹陷部 23的厚度差大于 500A。
所述緩冲层 2的材料为 SiNx 、 SiOx、 或者 SiNx与 SiOx的组合。 综上所述， 本发明的低温多晶硅的制作方法， 通过对緩冲层进行图案 化处理， 形成具有不同厚度的凸起部与凹陷部， 使得在激光准分子退火过 程中， 凸起部的保温效果优于凹陷部的保温效果， 从而构成温度梯度， 实 现对非晶硅层重结晶形成多晶硅层时的结晶位置和结晶方向进行有效控 制， 减少晶界数量， 使结晶状况在整个基板上的分布较均勾， 且该方法简 便、 易于搡作。 本发明的使用该低温多晶硅的制作方法的 TFT基板的制作 方法， 通过对緩冲层进行图案化处理， 形成具有不同厚度的凸起部与凹陷 部， 使得在激光准分子退火过程中， 凸起部的保温效果优于凹陷部的保温 效果， 从而构成温度梯度， 实现对非晶硅层重结晶形成多晶硅层时的结晶 位置和结晶方向进行有效控制， 减少沟道区域的晶界数量， 使结晶状况在 整个基板上的分布较均勾， 提高 TFT基板的性能。 本发明的由该 TFT基板 的制作方法制作而成的 TFT基板结构， 其緩冲层具有厚度不同的凸起部与 凹陷部， 使得位于该緩冲层上的多晶硅半导体层在形成过程中的结晶位置 和结晶方向得到有效控制， 沟道区域的晶界数量得以减少， 从而具有较高 的电子迁移率， 能够提高 TFT基板的性能， 改善显示效果。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明后附的权利要求的保护范围。

Claims

权 利 要 求
1、 一种低温多晶硅的制作方法， 包括如下步骤：
步骤 1、 提供一基板；
步骤 2、 在基板上沉积形成緩冲层；
步骤 3、 对緩冲层进行图案化处理， 形成具有不同厚度的凸起部与凹陷 部；
步骤 4、 在具有凸起部与凹陷部的緩冲层上沉积形成非晶硅层； 步骤 5、 对非晶硅层进行准分子激光退火预处理；
步骤 6、 对非晶硅层进行准分子激光退火制程， 使用激光束对非晶硅层 整面进行扫描， 使非晶硅层熔融并重结晶形成多晶硅层。
2、 如权利要求 1所述的低温多晶硅的制作方法， 其中， 所述緩冲层的 材料为 SiNx 、 SiOx、 或者 SiNx与 SiOx的组合。
3、 如权利要求 1所述的低温多晶硅的制作方法， 其中， 所述步骤 3中 的凸起部与凹陷部的排列方向与步骤 6 中激光束的排列方向一致， 而与激 光束的扫描方向垂直； 所述步骤 3 中的凸起部与凹陷部的排列方向与欲形 成的多晶硅半导体层的沟道长度方向相对应。
4、 如权利要求 1所述的低温多晶硅的制作方法， 其中， 所述凸起部与 凹陷部的厚度差大于 500A ; 所述步骤 6中非晶硅层熔融并重结晶形成多晶 硅层， 位于凹陷部的非晶硅先进行结晶， 之后沿着由凹陷部向凸起部的方 向结晶。
5、 一种 TFT基板的制作方法， 包括如下步骤：
步骤 1、 提供一基板；
步骤 2、 在基板上沉积形成緩冲层；
步骤 3、 对緩冲层进行图案化处理， 形成具有不同厚度的凸起部与凹陷 部；
步骤 4、 在具有凸起部与凹陷部的緩冲层上沉积形成非晶硅层； 步骤 5、 对非晶硅层进行准分子激光退火预处理；
步骤 6、 对非晶硅层进行准分子激光退火制程， 使用激光束对非晶硅层 整面进行扫描， 使非晶硅层熔融并重结晶形成多晶硅层；
步骤 7、 对多晶硅层进行成形处理， 形成多晶硅半导体层；
步骤 8、 在多晶硅半导体层上依次形成栅极绝缘层、 栅极、 绝缘层、 源 /漏极， 所述源 /漏极与多晶硅半导体层连接。
6、 如权利要求 5所述的 TFT基板的制作方法， 其中， 所述緩冲层的材 料为 SiNx 、 SiOx、 或者 SiNx与 SiOx的组合。
7、 如权利要求 5所述的 TFT基板的制作方法， 其中， 所述步骤 3中的 凸起部与凹陷部的排列方向与步骤 6 中激光束的排列方向一致， 而与激光 束的扫描方向垂直； 所述步骤 3 中的凸起部与凹陷部的排列方向与步骤 7 形成的多晶硅半导体层的沟道长度方向相对应。
8、 如权利要求 5所述的 TFT基板的制作方法， 其中， 所述凸起部与凹 陷部的厚度差大于 500A; 所述步骤 6中非晶硅层熔融并重结晶形成多晶硅 层， 位于凹陷部的非晶硅先进行结晶， 之后沿着由凹陷部向凸起部的方向 结晶。
9、 一种 TFT基板结构， 包括一基板、 位于基板上的緩冲层、 位于緩冲 层上的多晶硅半导体层、 位于多晶硅半岛体层与緩冲层上的栅极绝缘层、 位于栅极绝缘层上的栅极、 位于栅极与栅极绝缘层上的绝缘层， 及位于绝 缘层上的源 /漏极， 所述源 /漏极与所述多晶硅半导体层连接， 其特征在于， 所述緩冲层具有厚度不同的凸起部与凹陷部。
10、 如权利要求 9所述的 TFT基板结构， 其中， 所述凸起部与凹陷部 的排列方向与多晶硅半导体层的沟道长度方向相对应， 所述凸起部与凹陷 部的厚度差大于 500A, 所述緩冲层的材料为 SiNx 、 SiOx、 或者 SiNx 与 SiOx的组合。
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