WO2019037210A1 - 低温多晶硅阵列基板及制作方法、显示面板 - Google Patents

低温多晶硅阵列基板及制作方法、显示面板 Download PDF

Info

Publication number
WO2019037210A1
WO2019037210A1 PCT/CN2017/105962 CN2017105962W WO2019037210A1 WO 2019037210 A1 WO2019037210 A1 WO 2019037210A1 CN 2017105962 W CN2017105962 W CN 2017105962W WO 2019037210 A1 WO2019037210 A1 WO 2019037210A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
recess
substrate
low temperature
groove
Prior art date
Application number
PCT/CN2017/105962
Other languages
English (en)
French (fr)
Inventor
王涛
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/578,562 priority Critical patent/US10355034B2/en
Publication of WO2019037210A1 publication Critical patent/WO2019037210A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the invention relates to a display panel technology, in particular to a low temperature polysilicon array substrate, a manufacturing method thereof and a display panel.
  • display panels have been widely used in various electronic products as display components of electronic devices, and backlight modules are an important component in liquid crystal display devices.
  • array substrates typically use LTPS (low temperature polysilicon) to form control TFTs (thin film transistors).
  • LTPS low temperature polysilicon
  • the commonly used low-temperature polysilicon fabrication method is formed by melting and recrystallizing amorphous silicon deposited on a substrate by excimer laser annealing (ELA), and polycrystalline silicon formed by ELA recrystallization has a large number of grain boundaries, as shown in FIG. In the surface topography shown, a large number of grain boundaries are disorderly distributed in the channel of the finally formed thin film transistor, and these grain boundaries form a defect state center, which affects the output characteristics of the TFT.
  • the present invention provides a low temperature polysilicon array substrate, a manufacturing method thereof, and a display panel, which are prepared by preparing a polysilicon active layer on a flat surface and reducing a polysilicon active layer on a channel position of the thin film transistor.
  • the number of grain boundaries increases the operational stability of the thin film transistor device and enhances the real-life effect.
  • the invention provides a low temperature polysilicon array substrate, comprising a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polysilicon active layer disposed on the buffer layer, wherein the groove is located in a trench of the thin film transistor At the track, the buffer layer covers the surface of the groove to form an air layer in the groove.
  • the depth of the groove is equal to the thickness of the active layer of the polysilicon.
  • the invention also provides a method for manufacturing a low temperature polysilicon array substrate, comprising the following steps:
  • the amorphous silicon layer is subjected to excimer laser annealing to form an amorphous silicon layer to form a polysilicon active layer.
  • the recess is formed on the substrate at the channel of the thin film transistor, in particular, the recess is formed on the substrate by a photolithography process and an etching process.
  • the photolithography process employs a single photolithography process.
  • a metal sacrificial layer for filling the recess is provided in the recess, specifically depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the recess by an etching process.
  • the depth of the groove is equal to the thickness of the active layer of the polysilicon.
  • removing the metal sacrificial layer in the recess uses an etchant to etch away the sacrificial layer of metal in the recess.
  • the invention also provides a display panel comprising the low temperature polysilicon array substrate.
  • the present invention provides a groove in the channel position of the thin film transistor on the substrate to form an air layer in the groove, and a laser annealing process on the amorphous silicon layer, due to the channel position of the thin film transistor
  • the heat dissipation is poor, and the heat dissipation in the source and drain regions of the thin film transistor is better, so that the amorphous silicon layer located in the source and drain regions of the thin film transistor is first solidified and crystallized, so that the molten silicon starts to crystallize from the source drain edge and The inside of the channel grows, and the final grain size is large, which reduces the number of grain boundaries of the active layer of the polysilicon in the channel, thereby improving the stability of the operation of the thin film transistor device.
  • FIG. 2 is a schematic view showing a groove formed on a substrate
  • FIG. 3 is a schematic view showing formation of a metal sacrificial layer, a buffer layer, and an amorphous silicon layer on a substrate;
  • FIG. 4 is a schematic view of removing a sacrificial layer of metal
  • Fig. 5 is a view showing the state of crystallization of an active layer of polysilicon in a channel after performing an ELA process on an amorphous silicon layer.
  • the low temperature polysilicon array substrate of the present invention comprises a substrate 1, a groove 2 disposed on the substrate 1, a buffer layer 3 disposed on the substrate 1, and a polysilicon active layer 4 disposed on the buffer layer 3.
  • the groove 2 is located at the channel of the thin film transistor, and the buffer layer 3 covers the groove 2, so that an air layer is formed in the groove 2, and the air layer has an insulating effect.
  • the fabrication of other thin film transistor devices is performed on the polysilicon active layer 5 after the excimer laser annealing is performed.
  • the thin film transistor device further includes forming a gate insulating layer, a gate electrode, and an interlayer insulating layer over the polysilicon active layer 5. And a source electrode and a drain electrode; the source electrode and the drain electrode are respectively connected to both ends of the active layer through an insulating layer via hole, and the thin film transistor device is fabricated and structured according to the prior art thin film transistor array substrate The structure is the same and will not be described here.
  • the depth of the groove 2 is equal to the thickness of the polysilicon active layer 4, thereby further ensuring the effect of heat insulation.
  • the method for fabricating the low temperature polysilicon array substrate of the present invention comprises the following steps:
  • a groove 2 is formed on the substrate 1 at a channel of the thin film transistor; specifically, a groove 2 corresponding to a channel position of the thin film transistor device is formed on the substrate 1 by a single photolithography process and an etching process, the groove 2
  • the depth is equal to the thickness of the polysilicon active layer 4, and the depth of the groove 2 is adjusted correspondingly by the thickness of the polysilicon active layer 4;
  • a metal sacrificial layer 5 is deposited on the substrate 1, and the metal sacrificial layer 5 except the recess 2 is etched by an etching process to fill the metal sacrificial layer 5 in the recess 2.
  • the metal sacrificial layer 5 can be, for example, Is Mg (magnesium), Al (aluminum), Zn (zinc), Mo (molybdenum), Ti (titanium) or alloys thereof;
  • a buffer layer 3 and an amorphous silicon layer are sequentially formed on the substrate 1 , specifically, the buffer layer 3 is first deposited. Re-depositing the amorphous silicon layer; here, the buffer layer 3 may be deposited by a prior art method such as plasma enhanced chemical vapor deposition (PECVD); the deposition of the amorphous silicon layer is obtained by chemical vapor deposition;
  • PECVD plasma enhanced chemical vapor deposition
  • the etching solution may be selected from any one or more of hydrochloric acid, dilute sulfuric acid, and phosphoric acid.
  • the etching liquid easily reacts with the metal sacrificial layer 5, while the other material layers are insoluble or difficult to accommodate the etching liquid.
  • the material of the metal sacrificial layer 5 and the material of the etching liquid can also be changed;
  • the amorphous silicon layer is subjected to excimer laser annealing to form the polysilicon active layer 4, specifically, the amorphous silicon layer is subjected to excimer laser annealing, and the laser beam is positioned above the substrate 1, thereby obtaining a polysilicon film.
  • the excimer laser used for excimer laser annealing is any one of excimer lasers such as ruthenium chloride, ruthenium fluoride and argon fluoride.
  • an air layer is disposed under the channel corresponding position of the thin film transistor device, so that in the excimer laser annealing process, the channel position has an air layer, and the air layer blocks heat conduction through the substrate. Dissipated, so the heat dissipation is poor, and the source and drain regions 6 of the corresponding thin film transistor devices on both sides of the channel 7 radiate better (shown in FIG. 5), and the first solidification crystallization is performed, so that the molten silicon is not from the source and drain regions.
  • the edge of the crystalline silicon begins to crystallize and grows into the interior of the channel, eventually forming a crystallization effect with a fixed grain boundary direction as shown in FIG. 5.
  • the final grain size is large, and the polysilicon in the channel can be greatly reduced.
  • the number of grain boundaries in addition, since the air layer is formed in the groove, the molten silicon during the excimer laser annealing is on the flat horizontal buffer layer, and the excimer laser annealing is performed on the existing buffer layer having the pattern protrusion. Process, the final polycrystalline silicon crystallization effect can be further improved, can solve the low mobility of low-temperature polysilicon display backplane, thin film transistor Current is large, the mobility and the threshold voltage of the non-uniformity problem.
  • the remaining thin film transistor devices may be prepared, which may include forming a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source electrode over the active layer.
  • the drain electrode specifically:
  • a source/drain metal film is formed over the interlayer insulating layer, and patterned to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively connected to the ohmic contact regions at both ends of the polysilicon active layer 4 through the insulating layer via holes.
  • the present invention can be applied to a liquid crystal display panel or an organic light emitting diode display panel, and by providing a groove, the crystal grain size corresponding to the channel of the thin film transistor is increased after the amorphous silicon crystallization by excimer laser annealing (shown in FIG. 5) The grain boundary defect state is lowered, and the grain boundary direction is controllable parallel to the channel direction, which effectively improves the yield of the thin film transistor device and effectively improves the output capability.
  • a display panel of the present invention is obtained by the above-described low temperature polysilicon array substrate and a manufacturing method thereof, and details are not described herein again.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

提供一种低温多晶硅阵列基板，包括基板（1）、设于基板上的凹槽（2）、设于基板上的缓冲层（3）、设于缓冲层上的多晶硅有源层（4），凹槽位于薄膜晶体管的沟道处，缓冲层覆盖凹槽，使凹槽内形成空气层。还提供一种低温多晶硅阵列基板的制作方法，主要包括如下步骤：在基板上位于薄膜晶体管的沟道处制作凹槽；在基板上沉积金属牺牲层（5），并通过蚀刻工艺蚀刻除凹槽以外的金属牺牲层；在基板上依次形成缓冲层以及非晶硅层；去除凹槽内的金属牺牲层，使凹槽内形成空气层。进一步提供一种显示面板，包括低温多晶硅阵列基板。与现有技术相比，降低了沟道内多晶硅有源层的晶界数量，从而提升薄膜晶体管器件工作的稳定性。

Description

低温多晶硅阵列基板及制作方法、显示面板 技术领域
本发明涉及一种显示面板技术，特别是一种低温多晶硅阵列基板及制作方法、显示面板。
背景技术
目前，显示面板作为电子设备的显示部件已经广泛的应用于各种电子产品中，而背光模组则是液晶显示装置中的一个重要部件。
对于高端的显示面板而言(LCD或OLED)，阵列基板通常会采用LTPS(低温多晶硅)来形成控制TFT(薄膜晶体管)。常用的低温多晶硅制作方法是采用将沉积在衬底的非晶硅经过准分子激光退火(ELA)融化再结晶后形成，而采用ELA重结晶的方式形成的多晶硅具有大量的晶界，如图1所示的表面形貌，大量的晶界会无序的分布于最后形成的薄膜晶体管的沟道内，这些晶界会形成缺陷态中心，影响TFT的输出特性。
发明内容
为克服现有技术的不足，本发明提供一种低温多晶硅阵列基板及制作方法、显示面板，使多晶硅有源层制备于平整的平面上，降低薄膜晶体管的沟道位置上的多晶硅有源层的晶界数量，提升薄膜晶体管器件的工作稳定性，增强现实效果。
本发明提供了一种低温多晶硅阵列基板，包括基板、设于基板上的凹槽、设于基板上的缓冲层、设于缓冲层上的多晶硅有源层，所述凹槽位于薄膜晶体管的沟道处，所述缓冲层覆盖凹槽的表面使凹槽内形成空气层。
进一步地，所述凹槽的深度与多晶硅有源层的厚度相等。
本发明还提供了一种低温多晶硅阵列基板的制作方法，包括如下步骤：
提供一基板；
在基板上位于薄膜晶体管的沟道处制作凹槽；
在凹槽内设有用于填充凹槽的金属牺牲层；
在基板上依次形成缓冲层以及非晶硅层；
去除凹槽内的金属牺牲层，使凹槽内形成空气层；
对非晶硅层进行准分子激光退火，使非晶硅层形成多晶硅有源层。
进一步地，在基板上位于薄膜晶体管的沟道处制作凹槽具体为通过光刻工艺以及蚀刻工艺在基板上制作凹槽。
进一步地，所述光刻工艺采用一次光刻工艺。
进一步地，在凹槽内设有用于填充凹槽的金属牺牲层具体为在基板上沉积金属牺牲层，并通过蚀刻工艺蚀刻除凹槽以外的金属牺牲层。
进一步地，所述凹槽的深度与多晶硅有源层的厚度相等。
进一步地，去除凹槽内的金属牺牲层采用蚀刻液，将凹槽中的金属牺牲层蚀刻掉。
本发明还提供了一种显示面板，包括所述的低温多晶硅阵列基板。
本发明与现有技术相比，通过在基板上位于薄膜晶体管的沟道位置设置凹槽，在凹槽内形成空气层，对非晶硅层进行激光退火工艺时，由于薄膜晶体管的沟道位置的散热较差，而位于薄膜晶体管的源漏极区域的散热较好，导致位于薄膜晶体管的源漏极区域的非晶硅层会率先固化结晶，使熔融硅从源漏极边缘开始结晶并向沟道内部生长，最终晶粒尺寸大，降低了沟道内多晶硅有源层的晶界数量，从而提升薄膜晶体管器件工作的稳定性。
附图说明
图1是现有技术中通过ELA工艺重结晶形成的多晶硅有源层的扫描电镜图；
图2是在基板上形成凹槽的示意图；
图3是在基板上形成金属牺牲层、缓冲层及非晶硅层的示意图；
图4是去除金属牺牲层的示意图；
图5是对非晶硅层进行ELA工艺后在沟道内多晶硅有源层的结晶状况图。
具体实施方式
下面结合附图和实施例对本发明作进一步详细说明。
如图4所示，本发明的低温多晶硅阵列基板包括一基板1、设于基板1上的凹槽2、设于基板1上的缓冲层3、设于缓冲层3上的多晶硅有源层4，所述凹槽2位于薄膜晶体管的沟道处，所述缓冲层3覆盖凹槽2，使凹槽2内形成空气层，该空气层具有隔热的作用。
在进行准分子激光退火制成后在多晶硅有源层5上进行其他薄膜晶体管器件的制作，其中薄膜晶体管器件还包括在多晶硅有源层5的上方形成栅绝缘层、栅电极、层间绝缘层、以及源电极和漏电极等；所述源电极和漏电极分别通过绝缘层过孔与所述有源层的两端相连，由于薄膜晶体管器件的制作以及结构与现有技术中薄膜晶体管阵列基板的结构相同，在此不再赘述。
本发明中，凹槽2的深度与多晶硅有源层4的厚度相等，从而进一步保证隔热的效果。
本发明的低温多晶硅阵列基板的制作方法，包括如下步骤：
提供一基板1；
在基板1上位于薄膜晶体管的沟道处制作凹槽2；具体地，通过一次光刻工艺以及蚀刻工艺在基板1上制作出对应于薄膜晶体管器件的沟道位置的凹槽2，凹槽2的深度与多晶硅有源层4的厚度相等，通过多晶硅有源层4的厚度对凹槽2的深度进行相应的调整；
在基板1上沉积一层金属牺牲层5，并通过蚀刻工艺蚀刻除凹槽2以外的金属牺牲层5，使金属牺牲层5填补在凹槽2内；本发明中，金属牺牲层5可例如为Mg(镁)、Al(铝)、Zn(锌)、Mo(钼)、Ti(钛)或它们的合金；
在基板1上依次形成缓冲层3以及非晶硅层，具体为首先沉积缓冲层3， 再沉积非晶硅层；此处沉积缓冲层3可采用现有技术中如等离子体增强化学气相沉积(PECVD)方法沉积缓冲层3；非晶硅层的沉积采用化学气相沉积的方式获得；
去除凹槽2内的金属牺牲层5，使凹槽2内形成空气层；具体地，采用蚀刻液，将凹槽2中的金属牺牲层5蚀刻掉，使得凹槽内形成一隔热的空气层，从而使该区域的导热效果低于其余区域；相应地，蚀刻液可选择为盐酸、稀硫酸、磷酸任意一种或多种。该蚀刻液容易与该金属牺牲层5发生化学反应，而其他材料层均不溶或难容于蚀刻液。当然，本领域技术人员可知，根据这一原则，金属牺牲层5的材料以及蚀刻液的材质还可以作出改变；；
对非晶硅层进行准分子激光退火，使非晶硅层形成多晶硅有源层4，具体为，对非晶硅层进行准分子激光退火，激光束位于基板1上方，从而得到多晶硅薄膜。准分子激光退火采用的准分子激光器为氯化氙、氟化氪和氟化氩中任一种准分子激光器。
在低温多晶硅阵列基板制作中，在薄膜晶体管器件的沟道对应位置下方设置一空气层，这样使得在准分子激光退火制程时，沟道位置由于具有空气层，该空气层隔断了热量经基板传导散发，所以散热较差，而沟道7两侧对应的薄膜晶体管器件的源漏极区域6散热较好(图5所示)，会率先固化结晶，使得熔融的硅从源漏极区域的非晶硅边缘开始结晶并向沟道内部生长，最终形成如图5所示具有固定晶界方向的结晶效果，同时由于沟道区保温效果好，最终晶粒尺寸大，能大大降低沟道内多晶硅的晶界数量；另外由于空气层形成于凹槽中，准分子激光退火时熔融的硅是在平整的水平缓冲层上，相对于现有的在有图形凸起的缓冲层上进行准分子激光退火制程，最终多晶硅结晶效果也能得到更大的提升，能够解决低温多晶硅显示器背板中迁移率较低、薄膜晶体管的漏电流较大、迁移率及阈值电压不均匀性的问题。
在上述多晶硅有源层4的制作完成后，可对其余的薄膜晶体管器件进行制备，其中可包括：在所述有源层的上方形成栅绝缘层、栅电极、层间绝缘层、以及源电极和漏电极，具体为：
在多晶硅有源层4的上方沉积栅绝缘层；
利用掩模工艺对所述有源层两端的区域进行掺杂处理，从而在多晶硅有源层4的两端形成欧姆接触区域；
在栅绝缘层上方通过物理气相沉积(PVD)形成栅金属薄膜，并图形化形成栅电极；
在栅电极上方沉积层间绝缘层，并制作贯穿栅绝缘层和层间绝缘层的绝缘层过孔，从而露出多晶硅有源层4两端的欧姆接触区域；
在层间绝缘层上方形成源漏金属薄膜，并图形化形成源电极和漏电极，所述源电极和漏电极分别通过绝缘层过孔与多晶硅有源层4两端的欧姆接触区域相连。
值得注意的是，上述仅对除薄膜晶体管器件的多晶硅有源层4以外的其余器件进行的示例性叙述，但薄膜晶体管器件的制作不限于此。
本发明可应用于液晶显示面板或有机发光二极管显示面板，通过设置凹槽，使得通过准分子激光退火的非晶硅结晶后对应于薄膜晶体管的沟道的晶粒尺寸增加(图5所示)，晶界缺陷态降低，且晶界方向可控平行于沟道方向，有效改善薄膜晶体管器件的良率，有效提高输出能力。
本发明的一种显示面板，通过上述的低温多晶硅阵列基板以及制作方法获得，在此不再赘述。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种低温多晶硅阵列基板，其中：包括基板、设于基板上的凹槽、设于基板上的缓冲层、设于缓冲层上的多晶硅有源层，所述凹槽位于薄膜晶体管的沟道处，所述缓冲层覆盖凹槽的表面使凹槽内形成空气层。
  2. 根据权利要求1所述的低温多晶硅阵列基板，其中：所述凹槽的深度与多晶硅有源层的厚度相等。
  3. 一种低温多晶硅阵列基板的制作方法，其中：包括如下步骤：
    提供一基板；
    在基板上位于薄膜晶体管的沟道处制作凹槽；
    在凹槽内设有用于填充凹槽的金属牺牲层；
    在基板上依次形成缓冲层以及非晶硅层；
    去除凹槽内的金属牺牲层，使凹槽内形成空气层；
    对非晶硅层进行准分子激光退火，使非晶硅层形成多晶硅有源层。
  4. 根据权利要求3所述的低温多晶硅阵列基板的制作方法，其中：在基板上位于薄膜晶体管的沟道处制作凹槽具体为通过光刻工艺以及蚀刻工艺在基板上制作凹槽。
  5. 根据权利要求4所述的低温多晶硅阵列基板的制作方法，其中：所述光刻工艺采用一次光刻工艺。
  6. 根据权利要求3所述的低温多晶硅阵列基板的制作方法，其中：在凹槽内设有用于填充凹槽的金属牺牲层具体为在基板上沉积金属牺牲层，并通过蚀刻工艺蚀刻除凹槽以外的金属牺牲层。
  7. 根据权利要求3所述的低温多晶硅阵列基板的制作方法，其中：所述凹槽的深度与多晶硅有源层的厚度相等。
  8. 根据权利要求4所述的低温多晶硅阵列基板的制作方法，其中：所述凹槽的深度与多晶硅有源层的厚度相等。
  9. 根据权利要求5所述的低温多晶硅阵列基板的制作方法，其中：所述凹槽的深度与多晶硅有源层的厚度相等。
  10. 根据权利要求6所述的低温多晶硅阵列基板的制作方法，其中：所述凹槽的深度与多晶硅有源层的厚度相等。
  11. 根据权利要求6所述的低温多晶硅阵列基板的制作方法，其中：去除凹槽内的金属牺牲层采用蚀刻液，将凹槽中的金属牺牲层蚀刻掉。
  12. 一种显示面板，其中：包括低温多晶硅阵列基板所述低温多晶硅阵列基板包括基板、设于基板上的凹槽、设于基板上的缓冲层、设于缓冲层上的多晶硅有源层，所述凹槽位于薄膜晶体管的沟道处，所述缓冲层覆盖凹槽的表面使凹槽内形成空气层。
  13. 根据权利要求12所述的显示面板，其中：所述凹槽的深度与多晶硅有源层的厚度相等。
PCT/CN2017/105962 2017-08-21 2017-10-13 低温多晶硅阵列基板及制作方法、显示面板 WO2019037210A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/578,562 US10355034B2 (en) 2017-08-21 2017-10-13 Low-temperature polycrystalline silicon array substrate and manufacturing method, display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710717966.0 2017-08-21
CN201710717966.0A CN107611140A (zh) 2017-08-21 2017-08-21 低温多晶硅阵列基板及制作方法、显示面板

Publications (1)

Publication Number Publication Date
WO2019037210A1 true WO2019037210A1 (zh) 2019-02-28

Family

ID=61065228

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/105962 WO2019037210A1 (zh) 2017-08-21 2017-10-13 低温多晶硅阵列基板及制作方法、显示面板

Country Status (2)

Country Link
CN (1) CN107611140A (zh)
WO (1) WO2019037210A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108766981B (zh) * 2018-05-28 2021-01-22 京东方科技集团股份有限公司 一种绝热膜的制作方法、绝热结构、显示装置
CN109817644A (zh) * 2019-01-30 2019-05-28 武汉华星光电半导体显示技术有限公司 一种tft阵列基板及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030155572A1 (en) * 2002-02-19 2003-08-21 Min-Koo Han Thin film transistor and method for manufacturing thereof
CN102097459A (zh) * 2010-10-28 2011-06-15 广东中显科技有限公司 一种用于可调控地制备多晶硅薄膜的多层膜结构
CN105957805A (zh) * 2016-06-29 2016-09-21 京东方科技集团股份有限公司 低温多晶硅薄膜制作方法、薄膜晶体管、阵列基板和显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538310A (zh) * 2015-01-16 2015-04-22 京东方科技集团股份有限公司 低温多晶硅薄膜的制备方法、tft、阵列基板及显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030155572A1 (en) * 2002-02-19 2003-08-21 Min-Koo Han Thin film transistor and method for manufacturing thereof
CN102097459A (zh) * 2010-10-28 2011-06-15 广东中显科技有限公司 一种用于可调控地制备多晶硅薄膜的多层膜结构
CN105957805A (zh) * 2016-06-29 2016-09-21 京东方科技集团股份有限公司 低温多晶硅薄膜制作方法、薄膜晶体管、阵列基板和显示装置

Also Published As

Publication number Publication date
CN107611140A (zh) 2018-01-19

Similar Documents

Publication Publication Date Title
KR100785020B1 (ko) 하부 게이트 박막 트랜지스터 및 그 제조방법
US7192818B1 (en) Polysilicon thin film fabrication method
KR100882909B1 (ko) 박막트랜지스터, 그의 제조 방법, 이를 포함하는유기전계발광표시장치, 및 그의 제조 방법
CN102969250B (zh) Ltps薄膜及薄膜晶体管的制备方法,阵列基板及显示装置
CN103681776B (zh) 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置
WO2016101392A1 (zh) Amoled背板的制作方法及其结构
WO2016155055A1 (zh) 低温多晶硅tft基板结构及其制作方法
JP2007184562A (ja) 多結晶シリコンフィルムの製造方法及びそれを適用した薄膜トランジスタの製造方法
JP2009088106A (ja) 半導体層とこの半導体層を用いた半導体装置および表示装置
WO2015192558A1 (zh) 低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置
JP6081689B2 (ja) 多結晶シリコン層、薄膜トランジスタ、及び有機電界発光表示装置の製造方法
JP2007220918A (ja) レーザアニール方法、薄膜半導体装置及びその製造方法、並びに表示装置及びその製造方法
KR20110137086A (ko) 다결정 실리콘층의 형성 방법 및 이를 이용한 박막 트랜지스터의 형성방법
WO2019037210A1 (zh) 低温多晶硅阵列基板及制作方法、显示面板
US20180040648A1 (en) Array Substrate, Manufacturing Method Therefor, Display Panel, And Display Apparatus
US10355034B2 (en) Low-temperature polycrystalline silicon array substrate and manufacturing method, display panel
WO2013001579A1 (ja) 薄膜トランジスタ装置及び薄膜トランジスタ装置の製造方法
US11521989B2 (en) Display substrate, display apparatus and manufacturing method of display substrate
KR100579176B1 (ko) 반도체 소자 및 그 형성 방법
US11342448B2 (en) Method for manufacturing semiconductor device
CN107799398B (zh) 多晶硅薄膜的制作方法、薄膜、晶体管、基板及激光设备
JP3800336B2 (ja) 多結晶シリコン層の結晶方法
WO2015192552A1 (zh) 低温多晶硅薄膜的制造方法、tft、阵列基板及显示装置
KR100751315B1 (ko) 박막 트랜지스터, 박막 트랜지스터 제조 방법 및 이를구비한 평판 디스플레이 소자
JP2006324564A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17922693

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17922693

Country of ref document: EP

Kind code of ref document: A1