TWI599035B - 垂直結構薄膜電晶體及其製造方法 - Google Patents

垂直結構薄膜電晶體及其製造方法 Download PDF

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TWI599035B
TWI599035B TW105125618A TW105125618A TWI599035B TW I599035 B TWI599035 B TW I599035B TW 105125618 A TW105125618 A TW 105125618A TW 105125618 A TW105125618 A TW 105125618A TW I599035 B TWI599035 B TW I599035B
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thin film
semiconductor layer
forming
film transistor
channel
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嚴進嶸
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創王光電股份有限公司
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Description

垂直結構薄膜電晶體及其製造方法
本發明係關於一種薄膜電晶體，並且特別地，關於一種具有垂直通道之上閘極結構之垂直結構薄膜電晶體。
隨著顯示技術的進步，在主動式矩陣有機發光二極體(Active-matrix organic light-emitting diode,AMOLED)顯示技術中，畫素(Pixel)的電路設計在補償製程不穩定性中扮演了重要的角色，其補償不穩定性包含補償元件內之臨界電壓(Threshold voltage,Vth)或電路之電壓衰退(IR drop)之影響。不論是何種補償電路方式，在驅動用薄膜電晶體(Driving Thin Film Transistor,Driving TFT)之設計上皆需要採用較長之通道設計來改善元件電性之穩定性。常見的通道設計方式為S型或V型設計，此種設計方式之通道長度可達40微米以上，得以改善其元件穩定性，但卻也佔據了佈局面積。
當顯示技術的提升，每單位尺寸內的畫素越來越多，而使得顯示每一畫素所需使用之元件尺寸需相對應之縮小，上述之通道設計已無法滿足縮小後之元件尺寸，當通道長度縮小至2微米以下時，將會產生嚴重之短通道效應。
習知技術中，為減少通道佈局面積，通道之設計可藉由 受限之佈局面積內做一垂直通道設計以延伸通道長度，進而避免短通道效應之發生。習知技術中，可利用下閘極結構(Bottom gate)之薄膜電晶體元件特性，將閘極電極之形貌作為所需通道之乘載層，以得到具有垂直通道設計之較長通道。
在低溫多晶矽(Low Temperature Poly-silicon,LTPS)薄膜電晶體之製程中，非晶矽利用雷射回火(Laser Annealing)方式結晶成所需之多晶矽薄膜層。相較於傳統之非晶矽薄膜電晶體，得以提高電子移動速率、降低材料成本、提高開口率及降低面板重量與耗電量。
然而，下閘極結構之薄膜電晶體因其結構特性，容易造成雷射回火效果不佳，使得電子移動速率受到影響。雖其下閘極結構之薄膜電晶體可提供垂直通道設計以增加單位面積內之通道長度，但卻也衍伸出通道導電率不佳之另一問題。
由此可見，上述習知技術仍有諸多缺失，實非一良善之設計，而亟待加以改良。有鑑於此，本發明將提出一種上閘極結構之垂直結構薄膜電晶體以同時滿足垂直通道設計及雷射回火製程之需求。
本發明之一範疇在於提供一種垂直結構薄膜電晶體。根據本發明之一具體實施例，本發明垂直結構薄膜電晶體包含有一基板、一緩衝層、一半導體層及一閘極電極。緩衝層設置於基板上，緩衝層具有一表面，該表面具有一孔洞，緩衝層於該孔洞內具有一側壁及一底面。半導體層設置於緩衝層之表面上，並於側壁上形成一垂直 通道以及於底面上形成一水平通道，且水平通道電性連接於垂直通道。閘極電極設置於半導體層上。
其中，半導體層具有二摻雜區，分別位於半導體層的相對二側，閘極電極介於二摻雜區之間。
再者，上述垂直結構薄膜電晶體另包含有一源極電極與一汲極電極，分別連接於該二摻雜區。
此外，上述垂直結構薄膜電晶體另包含一閘極絕緣層，設置於該閘極電極與該半導體層之間。
本發明之另一範疇在於提供一種垂直結構薄膜電晶體之製作方法。根據本發明之另一具體實施例，本發明垂直結構薄膜電晶體之製作方法，其包含下列步驟：S1：準備一基板，S2：形成一緩衝層於基板上，該緩衝層具有一表面，S3：形成一孔洞於緩衝層之表面上，該緩衝層於該孔洞內具有一側壁以及一底面，S4：形成一半導體層於緩衝層之表面上，並於側壁上形成一垂直通道以及於底面上形成一水平通道，該水平通道電性連接於該垂直通道，S5：形成一閘極電極於半導體層上。
其中，步驟S4與步驟S5之間另包含有以下步驟：分別於半導體層的相對二側形成一摻雜區，閘極電極形成於二摻雜區之間。
再者，上述分別於半導體層的相對二側形成二摻雜區之步驟，另包含有以下步驟：形成一源極電極與一汲極電極，源極電極與汲極電極分別連接於二摻雜區。
相較於習知技術，本發明垂直結構薄膜電晶體提供一種 具有垂直通道之上閘極結構薄膜電晶體，藉由垂直方向之電流路徑以增加電流有效通道。在畫素(pixel)電路中的驅動薄膜電晶體(driving TFT)應用上，於300~500每英吋畫素(pixels per inch,ppi)的產品應用中，可以在相同佈局面積下提升通道長度以增加電流穩定性，即可把空間讓出來給其他元件設計規範，進而提升產品良率。
再者，在高解析度(1,000ppi以上)的應用中，若使用2微米以下的通道長度將會有嚴重的短通道效應，但若利用本發明垂直結構薄膜電晶體之垂直結構以增加等效通道長度，則可以在2微米的閘極長度下，實際做到更長的通道長度以改善短通道效應。
關於本發明之優點與精神可以藉由以下的發明詳述以及所附圖式得到進一步的了解。
1‧‧‧垂直結構薄膜電晶體
11‧‧‧基板
12‧‧‧緩衝層
121‧‧‧表面
1211‧‧‧側壁
1212‧‧‧底面
13‧‧‧半導體層
131‧‧‧垂直通道
132‧‧‧水平通道
133‧‧‧摻雜區
14‧‧‧閘極電極
15‧‧‧閘極絕緣層
16‧‧‧閘極電極層
L14‧‧‧閘極長度
S1~S5、S41‧‧‧步驟
圖一係繪示本發明垂直結構薄膜電晶體之一具體實施例之示意圖。
圖二係繪示本發明垂直結構薄膜電晶體之一具體實施例之電流路徑之三維示意圖。
圖三係繪示本發明垂直結構薄膜電晶體之一具體實施例之電流路徑之俯視示意圖。
圖四~圖八係繪示本發明垂直結構薄膜電晶體之製作方法之製程順序示意圖。
為使本發明之目的、技術方案及優點更加清楚明白，以 下參照附圖並舉實施例，對本發明作進一步詳細說明。
請參閱圖一，圖一係繪示本發明垂直結構薄膜電晶體1之一具體實施例之示意圖。本發明之一範疇在於提供一種垂直結構薄膜電晶體1。根據本發明之一具體實施例，本發明垂直結構薄膜電晶體1包含有一基板11、一緩衝層12、一半導體層13及一閘極電極14。緩衝層12設置於基板11上，緩衝層12具有一表面121，該表面121具有一孔洞，該孔洞具有一側壁1211。半導體層13設置於緩衝層12之表面121上，並於側壁1211上形成一垂直通道131。閘極電極14設置於半導體層13上。
其中，孔洞之一寬度得為2微米，孔洞之一深度得為0.6微米。
再者，孔洞另具有一底面1212，半導體層13得設置於緩衝層12之表面121上並於底面1212上形成一水平通道132，水平通道132係電性連接於垂直通道131。
此外，閘極電極14之閘極長度L14(Gate length)得為2微米。
於實際應用中，水平通道132可呈S型或V型設計。
於實際應用中，半導體層13得為一多晶矽層。該多晶矽層得藉由一非晶矽層並利用一準分子雷射退火(Excimer Laser Annealing,ELA)製程而得。
請參閱圖一、圖二及圖三，圖二係繪示本發明垂直結構薄膜電晶體1之一具體實施例之電流路徑之三維示意圖，圖三係繪示本 發明垂直結構薄膜電晶體1之一具體實施例之電流路徑之俯視示意圖。於一實際應用中，孔洞之一寬度得為2微米，孔洞之一深度得為0.6微米，使得水平通道132之X方向為2微米長，垂直通道131(Z方向)為0.6微米長。因本示意圖擁有兩個孔洞，相較於習知技術僅水平方向之電流通道路徑，本發明垂直結構薄膜電晶體1額外具有4個垂直通道131，因此在相同的佈局面積下，可有效提升通道長度2.4微米。
於實際應用中，本發明垂直結構薄膜電晶體1另包含一閘極絕緣層15，設置於閘極電極14與半導體層13間。
再者，本發明垂直結構薄膜電晶體1另包含有一源極電極與一汲極電極，分別連接於半導體層之摻雜區133。其中，摻雜區133可為N型半導體或P型半導體。
請參閱圖四~圖八，圖四~圖八係繪示本發明垂直結構薄膜電晶體1之製作方法之製程順序示意圖。本發明之另一範疇在於提供一種垂直結構薄膜電晶體1之製作方法。根據本發明之另一具體實施例，本發明垂直結構薄膜電晶體1之製作方法，其包含下列步驟：S1：準備一基板11，S2：形成一緩衝層12於基板11上，該緩衝層12具有一表面121，S3：形成一孔洞於緩衝層12之表面121上，該孔洞具有一側壁1211，S4：形成一半導體層13於緩衝層12之表面121上，並於側壁1211上形成一垂直通道131，S5：形成一閘極電極14於半導體層13上。
其中，閘極電極14之閘極長度L14(Gate length)得為2微米。
再者，步驟S5得先沉積一閘極電極層16後經一圖案化蝕 刻製程得所需之閘極電極14。
所使用之閘極電極14材料得為鉬。
此外，步驟S3得利用一蝕刻製程將緩衝層12蝕刻出所需之孔洞。
於實際應用中，孔洞另具有一底面1212，半導體層13得設置於緩衝層12之表面121上並於底面1212上形成一水平通道132，水平通道132係電性連接於垂直通道131。
其中，半導體層13得為一多晶矽層。步驟S4得藉由一非晶矽層利用一準分子雷射退火(ELA)製程而得。
於實際應用中，孔洞之一寬度得為2微米，孔洞之一深度得為0.6微米，因其ELA製程對所述之該孔洞之上下起伏幅度並無影響，使得半導體層13可緊密連接於孔洞上方。
此外，於實際應用中，步驟S4另包含一步驟S41：形成一閘極絕緣層15於半導體層13上。
閘極電極14得形成於所述之閘極絕緣層15上。
相較於習知技術，本發明垂直結構薄膜電晶體提供一種具有垂直通道之上閘極結構薄膜電晶體，藉由垂直方向之電流路徑以增加電流有效通道。在畫素(pixel)電路中的驅動薄膜電晶體(driving TFT)應用上，於300~500每英吋畫素(pixels per inch,ppi)的產品應用中，可以在相同佈局面積下提升通道長度以增加電流穩定性，即可把空間讓出來給其他元件設計規範，進而提升產品良率。
再者，在高解析度(1,000ppi以上)的應用中，若使用2微 米以下的通道長度將會有嚴重的短通道效應，但若利用本發明垂直結構薄膜電晶體之垂直結構以增加等效通道長度，則可以在2微米的閘極長度下，實際做到更長的通道長度以改善短通道效應。
藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。
1‧‧‧垂直結構薄膜電晶體
11‧‧‧基板
12‧‧‧緩衝層
121‧‧‧表面
1211‧‧‧側壁
1212‧‧‧底面
13‧‧‧半導體層
131‧‧‧垂直通道
132‧‧‧水平通道
133‧‧‧摻雜區
14‧‧‧閘極電極
15‧‧‧閘極絕緣層
L14‧‧‧閘極長度

Claims (10)

  1. 一種垂直結構薄膜電晶體，其包含有：一基板；一緩衝層，設置於該基板上，該緩衝層具有一表面，該表面具有一孔洞，該緩衝層於該孔洞內具有一側壁及一底面；一半導體層，設置於該緩衝層之該表面上，並於該側壁上形成一垂直通道以及於該底面上形成一水平通道，該水平通道電性連接該垂直通道；以及一閘極電極，設置於該半導體層上。
  2. 如申請專利範圍第1項所述之垂直結構薄膜電晶體，其中該半導體層具有二摻雜區，分別位於該半導體層的相對二側，該閘極電極介於該二摻雜區之間。
  3. 如申請專利範圍第2項所述之垂直結構薄膜電晶體，另包含有一源極電極與一汲極電極，分別連接於該二摻雜區。
  4. 如申請專利範圍第1項所述之垂直結構薄膜電晶體，另包含有一閘極絕緣層，設置於該閘極電極與該半導體層之間。
  5. 如申請專利範圍第1項所述之垂直結構薄膜電晶體，其中該緩衝層的該表面具有多個該孔洞，該半導體層分別於各個該孔洞內形成該垂直通道與該水平通道。
  6. 一種垂直結構薄膜電晶體之製作方法，其包含下列步驟：S1：準備一基板；S2：形成一緩衝層於該基板上，該緩衝層具有一表面；S3：形成一孔洞於該緩衝層之該表面上，該緩衝層於該孔洞內具有一側壁以及一底面；S4：形成一半導體層於該緩衝層之該表面上，並於該側壁上形成一垂直通道以及於該底面上形成一水平通道，該水平通道電性連接於該垂直通道；以及S5：形成一閘極電極於該半導體層上。
  7. 如申請專利範圍第6項所述之垂直結構薄膜電晶體之製作方法，其中步驟S4與步驟S5之間另包含有以下步驟：分別於該半導體層的相對二側形成一摻雜區，該閘極電極形成於該二摻雜區之間。
  8. 如申請專利範圍第7項所述之垂直結構薄膜電晶體之製作方法，其中分別於該半導體層的相對二側形成該二摻雜區之步驟，另包含有以下步驟：形成一源極電極與一汲極電極，該源極電極與該汲極電極分別連接於該二摻雜區。
  9. 如申請專利範圍第6項所述之垂直結構薄膜電晶體之製作方法，其中步驟S4與步驟S5之間另包含有以下步驟：形成一閘極絕緣層於該半導體層上，該閘極絕緣層介於該半導體層與該閘極電極之間。
  10. 如申請專利範圍第6項所述之垂直結構薄膜電晶體之製作方法，其中步驟S3係形成多個該孔洞；在步驟S4中，該半導體層於各個該孔洞中形成該垂直通道以及該水平通道。
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