WO2014201716A1 - 薄膜晶体管的沟道形成方法及补偿电路 - Google Patents

薄膜晶体管的沟道形成方法及补偿电路 Download PDF

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WO2014201716A1
WO2014201716A1 PCT/CN2013/078228 CN2013078228W WO2014201716A1 WO 2014201716 A1 WO2014201716 A1 WO 2014201716A1 CN 2013078228 W CN2013078228 W CN 2013078228W WO 2014201716 A1 WO2014201716 A1 WO 2014201716A1
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amorphous silicon
crystallization
crystallization zone
film transistor
thin film
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PCT/CN2013/078228
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English (en)
French (fr)
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许宗义
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深圳市华星光电技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a channel forming method and a compensation circuit for a thin film transistor.
  • Thin film transistor Transistor has been widely used in the driving of active liquid crystal displays.
  • silicon thin film materials used according to thin film transistors are generally of two types: amorphous-silicon and poly-silicon.
  • polysilicon materials have many properties superior to amorphous silicon materials.
  • Polycrystalline silicon has a larger grain, so that electrons are easily free to move in polycrystalline silicon, so the mobility of polycrystalline silicon is higher than that of amorphous silicon.
  • a thin film transistor made of polysilicon has a faster reaction time than an amorphous silicon thin film transistor.
  • a polysilicon thin film transistor (poly-Si) is used.
  • the substrate area occupied by the TFT can be smaller than the area of the substrate occupied by the amorphous silicon thin film transistor, and the aperture ratio of the liquid crystal panel is improved.
  • Liquid crystal display using polysilicon thin film transistor (poly-Si) under the same shell degree TFT LCD) can use a low wattage backlight to achieve low power consumption.
  • polycrystalline silicon thin films are mostly fabricated on a substrate using a low temperature polysilicon preparation process (Low Temperature). Poly-Silicon, LTPS).
  • the low temperature polysilicon preparation process is an excimer laser (Excimer) Laser) as a heat source.
  • Excimer Excimer
  • the amorphous silicon film absorbs the energy of the excimer laser and is converted into a polysilicon film.
  • Sequential Lateral Crystallization Solidification, SLS Sequential Lateral Crystallization Solidification, SLS
  • the upper temperature difference is used to achieve the lateral crystallization technique, and the laser is transmitted through the reticle to generate a laser of a specific shape.
  • the first laser first crystallizes the laterally grown crystal grains, and the second laser irradiation region overlaps with the first crystallization region.
  • the silicon film in the region irradiated by the second laser starts to melt, and the long crystalline columnar crystal particles are grown by using the first crystalline polycrystalline silicon film as a seed crystal.
  • the electron mobility of the TFT is high, for example, 300 cm 2 /V-s; however, if the channel length of the TFT is perpendicular to the grain boundary of the polysilicon film, the electron mobility of the TFT is greatly reduced to 100 cm 2 /V-s, Therefore, in the prior art SLS lateral crystallization technique, the electron mobility of the TFT channel is low, and the electrical non-uniformity of the TFT.
  • the present invention constructs a channel forming method for a thin film transistor, wherein the method comprises the following steps:
  • each of the amorphous silicon layers Forming two open spaces in each of the amorphous silicon layers, the two open spaces being respectively formed on adjacent bent portions of the amorphous silicon layer; wherein each of the open spaces extends along a length direction, the break The open space has a width perpendicular to the length direction, and the width ranges from 1 to 3 microns;
  • Laser irradiation treatment is performed on the amorphous silicon pattern in which the disconnected space has been formed, so that the crystal grains in the amorphous silicon layer located on both sides of each of the disconnected spaces grow toward the corresponding disconnected space by the temperature difference And crystallizing into a channel of the thin film transistor in the disconnected space, wherein the scanning pitch of the laser is in the range of 0-30 micrometers.
  • the present invention also constructs a channel forming method of a thin film transistor, the method comprising the following steps:
  • Each of the amorphous silicon layers forms two open spaces, and the two open spaces are respectively formed at adjacent bent portions of the amorphous silicon layer;
  • the present invention also constructs a compensation circuit including at least one thin film transistor including a substrate and a channel formed on the substrate; wherein the channel is a bent structure, A first crystalline unit and a second crystalline unit are included;
  • the first crystallization unit and the second crystallization unit are located on a bent part adjacent to the channel, the first crystallization unit includes a first crystallization zone and a second crystallization zone, and the second crystallization unit includes a third crystallization zone and a fourth crystallization zone;
  • the grain boundaries in the first crystallization zone and the second crystallization zone are perpendicular to an interface between the first crystallization zone and the second crystallization zone; the third crystallization zone and the fourth crystallization The grain boundaries in the regions are both perpendicular to the interface between the third crystalline region and the fourth crystalline region.
  • the present invention forms two open spaces in adjacent bent portions of the amorphous silicon layer, and each open space separates the corresponding amorphous silicon layers into two adjacent intervals, after being irradiated by laser, adjacent
  • the grains in the two intervals will grow toward the corresponding breaking space and meet in the breaking space, and then crystallize to form two crystal regions.
  • the grain boundaries in the two crystal regions are perpendicular to the interface between the two crystal regions. This can increase the electron mobility of the formed channel and make the electrical properties of the formed TFT more uniform.
  • 1A-1M are schematic views showing a process of forming a channel by crystallization using an amorphous silicon film according to an embodiment of the present invention
  • FIGS. 2A to 2D are schematic views showing a process of forming a thin film transistor array substrate according to a channel formed by the processes of Figs. 1A-1M;
  • FIG. 3 is a schematic view showing application of the thin film transistor array substrate formed by the processes of FIGS. 2A to 2D to the compensation circuit of the first embodiment;
  • FIGS. 4 is a schematic view showing application of the thin film transistor array substrate formed by the processes of FIGS. 2A to 2D to the compensation circuit of the second embodiment;
  • FIG. 5 is a schematic view showing the application of the thin film transistor array substrate formed by the processes of FIGS. 2A to 2D to the compensation circuit of the second embodiment.
  • FIG. 1A-1M are schematic diagrams showing processes of a channel forming method of a thin film transistor array substrate according to an embodiment of the present invention.
  • a substrate 100 is provided on which a buffer layer 101 (Buffer) is formed.
  • Buffer buffer layer 101
  • the substrate 100 is, for example, a glass substrate, a flexible plastic substrate, a wafer substrate, or a heat dissipation substrate.
  • the buffer layer 101 is preferably formed of silicon nitride (SiNx) or silicon oxide (SiO 2 ), and the buffer layer 101 mainly prevents impurities from diffusing from the substrate 100.
  • an amorphous silicon (a-Si:H) layer 102 is formed on the buffer layer 101.
  • the embodiment of the present invention preferably uses chemical vapor deposition (CVD) on the buffer layer 101.
  • the amorphous silicon layer 102 is deposited thereon, and a top view of the amorphous silicon layer 102 is shown in FIG. 1C.
  • the amorphous silicon layer 102 is subjected to a first etching process to form an amorphous silicon pattern.
  • FIG. 1D is a top view of the amorphous silicon layer 102 after the first etching process, wherein the substrate 100 having the buffer layer 101 and the amorphous silicon layer 102 defines a plurality of images thereon. a pixel region P and a plurality of TFT regions T, wherein the TFT region T is located at an angle of each pixel region P, and the amorphous silicon pattern after the first etching process includes a plurality of amorphous silicon layers 102 Each amorphous silicon layer 102 is located in the TFT region T.
  • the first etching in the embodiment of the present invention may be performed by dry etching or wet etching.
  • FIG. 1E is a schematic structural diagram of the amorphous silicon layer 102.
  • the amorphous silicon layer 102 is a bent structure, and includes a first flat layer 201 and a second flat layer 202.
  • the first leveling layer 201 and the second leveling layer 202 are connected to each other and perpendicular to each other.
  • the amorphous silicon layer 102 is etched to form a bent structure, and the main purpose thereof is to form a subsequent double gate (Daul Gate) TFT.
  • Daul Gate double gate
  • the second etching process is continued on the amorphous silicon layer 102 after the first etching process to form a disconnected space in each amorphous silicon layer 102 of the amorphous silicon layer pattern. .
  • the disconnected space includes a first open space R1 formed in the first leveling layer 201, and a second open space formed in the second leveling layer 202. R2.
  • FIG. 1F is a cross-sectional view taken along line G-G' of FIG. 1G
  • FIG. 1I is a plan view of FIG. 1H.
  • the first breaking space R1 extends along the length direction D, and the first breaking space R1 has a width L perpendicular to the length direction D, and the width L preferably ranges from 1 to 3 micrometers ( Um), the first open space R1 divides the amorphous silicon layer 102 into two sections: a first section 301 and a second section 302.
  • the structure of the second breaking space R2 is similar.
  • the width of the second space is preferably in the range of 1 to 3 micrometers, etc., and details are not described herein again.
  • the second etching process may use dry etching, wet etching or laser etching, which will not be described in detail herein.
  • FIG. 1J the amorphous silicon layer 102 in which the open space has been formed is subjected to laser irradiation treatment to form the channel 103.
  • FIG. 1K is a plan view of FIG. 1H after laser irradiation
  • FIG. 1L is a plan view. Corresponding to the illustration of Figure 1G.
  • 1K is an example of a first open space R1.
  • the amorphous silicon layer 102 corresponding to the first interval 301 and the second interval 302 on both sides of the first open space R1 is temperature difference. Forming lateral crystals.
  • the dies of the first interval 301 and the second interval 302 that are close to the first open space R1 are grown toward the first open space R1, wherein the first interval 301 a crystal grain in the first open space R1 is grown toward the first open space R1 (from left to right), and a first crystallized region 401 is formed in the first open space R1;
  • the grains of the second interval 302 near the first open space R1 are grown toward the first open space R1 (from right to left), and the second crystal region 402 is formed in the first open space R1.
  • the crystal grains of the first crystallization zone 401 and the second crystallization zone 402 meet at the central axis Q of the disconnection space M, stop growing and crystallize.
  • the first crystallization zone 401 and the second crystallization zone 402 constitute a first crystallization unit F1, and the first crystallization unit F1 corresponds to the first disconnection space R1.
  • the grain boundaries of the grains in the first crystallization zone 401 and the second crystallization zone 402 are perpendicular to a plane between the first crystallization zone 401 and the second crystallization zone 402.
  • a second crystallization unit F2 is formed at the second opening space R2, and the second crystallization unit F2 includes a third crystallization area 403 and a fourth crystallization area 404.
  • the grain boundaries in the third crystallization zone 403 and the fourth crystallization zone 404 are both perpendicular to the interface between the third crystallization zone 403 and the fourth crystallization zone 404, with respect to the detailed formation of the second crystallization unit F2
  • For the procedure please refer to the detailed description of the first crystallization unit F1, and details are not described herein again.
  • first crystallization unit F2 in the first crystallization unit F2, an intersection between the first crystallization zone 401 and the second crystallization zone 402 (not shown) and the third crystallization zone 403 and the fourth crystallization zone 404.
  • the intersection lines (not shown) intersect, preferably vertical.
  • 1M is a plan view of the channel 103 formed by laser irradiation of the amorphous silicon layer 102 having an open space in FIG. 1F.
  • the channel 103 is located corresponding to the TFT region T, and each of the channels 103 serves as an active layer in a thin film transistor (TFT).
  • TFT thin film transistor
  • the present invention forms two open spaces in adjacent bent portions of the amorphous silicon layer, and each open space separates the corresponding amorphous silicon layers into two adjacent intervals, after being irradiated by laser, adjacent
  • the grains in the two intervals will grow toward the corresponding breaking space and meet in the breaking space, and then crystallize to form two crystal regions.
  • the grain boundaries in the two crystal regions are perpendicular to the interface between the two crystal regions. This can increase the electron mobility of the formed TFT channel and make the electrical conductivity of the TFT more uniform.
  • the scanning direction of the laser light is preferably perpendicular to the longitudinal direction of the disconnected space, or is the length of the disconnected space.
  • the directions are parallel, and of course, the angle between the longitudinal direction of the disconnected space is in the range of 0 to 90 degrees, and the scanning pitch of the laser is preferably in the range of 0 to 30 micrometers. The distance between adjacent laser lines.
  • FIGS. 2A to 2D show the processing steps for forming a thin film transistor array substrate in accordance with the trenches formed in the processes of Figs. 1A-1M.
  • a substrate 501 is provided on which a buffer layer 502 is formed. Then, a channel 503 is formed by the above-described steps 1A-1M at a position where a thin film transistor (TFT) is to be formed in the TFT region.
  • the channel 503 on the buffer layer 502 has an island shape.
  • the channel 503 is divided into an active region 503a, a source and a drain region 503b. The source and the drain region 503b are disposed on both sides of the active region 503a.
  • a layer of silicon nitride or silicon oxide insulating material 504 is then formed over the buffer layer 501 to cover the channel 503.
  • a metallic conductive material is deposited on the insulating material 504.
  • the conductive material and the insulating material 504 are then patterned simultaneously to form a gate insulating layer 505 and a gate 506 continuously on the channel 503.
  • Impurities of p-type or n-type ions are then doped on the exposed portions of the channel 503, that is, the source and drain regions 503b.
  • the gate 506 acts as an ion plug to prevent impurities from penetrating into the active region 503a while doping impurities.
  • the source of the doped impurity and the drain region 503b are annealed after doping to activate ions doped in the source and drain regions 503b. Simultaneously performing the step of restoring the source and the drain region 503b to polymorphism, avoiding that the semiconductor structure of the source and drain regions 503b may change from polycrystalline to amorphous due to excessive ion doping. .
  • an insulating layer 507 is formed on the entire surface of the substrate 501 to cover the gate electrode 506 and the gate insulating layer 505.
  • the insulating layer 507 is then patterned to form a first contact hole 508 and a second contact hole 509 that expose the source and the drain region 503b, respectively.
  • the insulating layer 507 may include silicon oxide and silicon nitride.
  • a metal layer is deposited on the insulating layer 507 and patterned to form a source 510 and a drain 511.
  • the source 210 contacts the source region 503b through the first contact hole 508, and the drain 511 contacts the drain region 503b through the second contact hole 509.
  • the source 510, the drain 511, the gate 506, and the polysilicon pattern 503 are commonly formed to form a thin film transistor (TFT).
  • TFT thin film transistor
  • the embodiment of the present invention further provides a thin film transistor array substrate (TFT substrate), the thin film transistor array substrate includes a substrate, a buffer layer formed on the substrate, a channel formed on the buffer layer, and a gate insulating layer Layer, gate, insulating layer, source and drain.
  • TFT substrate thin film transistor array substrate
  • the thin film transistor array substrate includes a substrate, a buffer layer formed on the substrate, a channel formed on the buffer layer, and a gate insulating layer Layer, gate, insulating layer, source and drain.
  • the channel is a bent structure comprising a first crystalline unit and a second crystalline unit.
  • the first crystallization unit and the second crystallization unit are located on a bent part adjacent to the channel, the first crystallization unit includes a first crystallization zone and a second crystallization zone, and the second crystallization unit includes a third crystalline zone and a fourth crystalline zone.
  • the grain boundaries in the first crystallization zone and the second crystallization zone are perpendicular to an interface between the first crystallization zone and the second crystallization zone; the third crystallization zone and the fourth crystallization The grain boundaries in the regions are both perpendicular to the interface between the third crystalline region and the fourth crystalline region.
  • the first crystallization zone and the second crystallization zone are formed by laser irradiation of an amorphous silicon layer on both sides of the same breaking space (such as the first breaking space), and the breaking space is along a length.
  • the direction is extended, and the widths of the first crystallization zone and the second crystallization zone are perpendicular to the length direction, and the width ranges from 1 to 3 micrometers.
  • the third crystallization zone and the fourth crystallization zone are formed by laser irradiation of an amorphous silicon layer on both sides of the same breaking space (for example, the second breaking space), and the breaking space is along a length.
  • the direction is extended, and the widths of the third crystallization zone and the fourth crystallization zone are perpendicular to the length direction, and the width ranges from 1 to 3 micrometers.
  • FIG. 1A-1M and FIG. 2A-2D For detailed formation process of the thin film transistor and the channel in the thin film transistor array substrate, please refer to FIG. 1A-1M and FIG. 2A-2D for detailed description, and details are not described herein again.
  • FIG. 3 is a schematic structural diagram of a compensation circuit according to a first embodiment of the present invention.
  • the compensation circuit comprises: six thin film transistor TFTs, which are sequentially identified as M1, M2, M3, M4, M5 and M6; capacitors C1 and C2; power supply voltage VDD; ground voltage VSS; circuit input voltage Vini; data line voltage Vdata; Scanning line Scan N and Scan N-1, LED EM.
  • At least one of the six thin film transistors is selected to be formed by the processes of FIGS. 2A to 2D, and the channels of FIGS. 2A to 2D are according to 1A-.
  • the 1M process is made, and the film transistors labeled M5 and M6 as shown in FIG. 3 each include a double gate formed by 1A-1M (Daul The channel of the Gate structure, please refer to the description above, and will not be described here.
  • FIG. 4 is a schematic structural diagram of a compensation circuit according to a second embodiment of the present invention.
  • the compensation circuit comprises: five thin film transistor TFTs, which are sequentially identified as N1, N2, N3, N4 and N5; capacitor C; scan lines G1, G2 and G3; anode ANODE, cathode CATHODE and voltage V0; data line DATA; LED (Organic Light-Emitting Diode, OLED).
  • At least one of the five thin film transistors is selected to be formed by the processes of FIGS. 2A to 2D, and the channels of FIGS. 2A to 2D are according to 1A-.
  • the 1M process is made, and the film transistors labeled N2 and N3 as shown in FIG. 4 each include a double gate formed by 1A-1M (Daul The channel of the Gate structure, please refer to the description above, and will not be described here.
  • FIG. 5 is a schematic structural diagram of a compensation circuit according to a third embodiment of the present invention.
  • the compensation circuit comprises: five thin film transistor TFTs, which are sequentially identified as Q1, Q2, Q3, Q4 and Q5; capacitor C; scan lines G1, G2 and G3; anode ANODE, cathode CATHODE and voltage V0; data line DATA; LED (Organic Light-Emitting Diode, OLED).
  • At least one of the five thin film transistors is selected to be formed by the processes of FIGS. 2A to 2D, and the channels in FIGS. 2A to 2D are according to 1A-.
  • the 1M process is made, and the film transistors labeled Q2 and Q3 in Figure 5 each include a double gate formed by 1A-1M (Daul The channel of the Gate structure, please refer to the description above, and will not be described here.
  • the present invention forms two open spaces in adjacent bent portions of the amorphous silicon layer, and each open space separates the corresponding amorphous silicon layers into two adjacent intervals, after being irradiated by laser, adjacent
  • the grains in the two intervals will grow toward the corresponding breaking space and meet in the breaking space, and then crystallize to form two crystal regions.
  • the grain boundaries in the two crystal regions are perpendicular to the interface between the two crystal regions. This can increase the electron mobility of the formed channel and make the electrical properties of the formed TFT more uniform.

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Abstract

本发明对基板上的非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形，非晶硅层具有弯折结构，在每一非晶硅层相邻的弯折部位分别形成两断开空间，激光照射使得位于每一断开空间两侧的非晶硅层内的晶粒在温度差的作用下朝着对应的断开空间方向生长，在断开空间内结晶形成薄膜晶体管的沟道。

Description

薄膜晶体管的沟道形成方法及补偿电路 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种薄膜晶体管的沟道形成方法及补偿电路。
 背景技术
薄膜晶体管(Thin Film Transistor，TFT)已广泛应用在主动式液晶显示器的驱动上，其中根据薄膜晶体管使用的硅薄膜材料通常有非晶硅（amorphous-silicon）与多晶硅(poly-silicon)两种类型。
在液晶显示器的制造中，多晶硅材料具有许多优于非晶硅材料的特性。多晶硅具有较大的晶粒(grain)，使得电子在多晶硅中容易自由移动，所以多晶硅的电子迁移率(mobility)高于非晶硅。以多晶硅制作的薄膜晶体管，其反应时间比非晶硅薄膜晶体管快。在相同分辨率的液晶显示器中，使用多晶硅薄膜晶体管(poly-Si TFT)所占用的基板面积可以比使用非晶硅薄膜晶体管所占用的基板面积小，而提高液晶面板的开口率。在相同的壳度下，使用多晶硅薄膜晶体管的液晶显示器(poly-Si TFT LCD)可以采用低瓦数的背光源，达到低耗电量的要求。
目前在基板上制作多晶硅薄膜大多利用低温多晶硅制备工艺(Low Temperature Poly-Silicon，LTPS)。低温多晶硅制备工艺是以准分子激光(Excimer Laser)作为热源。当激光照射(irradiate)于具有非晶硅薄膜的基板上，非晶硅薄膜吸收准分子激光的能量而转变成为多晶硅薄膜。
依序侧向结晶(Sequential Lateral Solidification，SLS)技术为利用光罩或是其他方式造成在a-Si precursor 上温度高低差来达到侧向结晶技术,利用激光透过光罩产生特定形状的激光，第一道激光先结晶出侧向成长的晶粒后第二道激光照射区域与第一道结晶区域重叠一部份，通过照射非晶硅区域，第二道激光所照射区域的硅薄膜开始熔融后会以第一道结晶多晶硅薄膜为晶种成长出长柱状的结晶颗粒。
当TFT的沟道长度（channel length）平行于多晶硅薄膜的晶粒边界（grain boundary）时，电子迁移率较高，譬如为300cm2/V-s；但是如果TFT的沟道长度垂直于多晶硅薄膜的晶粒边界，则会使的TFT的电子迁移率大幅下降至100cm2/V-s, 因此现有技术中SLS侧向结晶技术中，TFT沟道的电子迁移率较低，TFT的电性不均匀性。
 技术问题
本发明的目的在于提供一种薄膜晶体管的沟道形成方法及补偿电路，旨在现有技术中TFT沟道的电子迁移率较低，TFT的电性不均匀性的技术问题。
 技术解决方案
本发明构造了一种薄膜晶体管的沟道形成方法，其中所述方法包括以下步骤：
提供基板，在所述基板上形成非晶硅层；
对所述非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形，其中所述多晶硅图形中的每一非晶硅层均为弯折结构；
在每一非晶硅层形成两断开空间，所述两断开空间分别形成于所述非晶硅层的相邻的弯折部位；其中每一断开空间沿一长度方向延伸，该断开空间具有一与该长度方向垂直的宽度，所述宽度的范围为1~3微米；
对已形成断开空间的非晶硅图形进行激光照射处理，以使得位于每一断开空间两侧的非晶硅层内的晶粒在温度差的作用下朝着对应的断开空间方向生长，并在所述断开空间内结晶形成薄膜晶体管的沟道，其中所述激光的扫描间距的范围为0-30微米。
为解决上述技术问题，本发明还构造了一种薄膜晶体管的沟道形成方法，所述方法包括以下步骤：
提供基板，在所述基板上形成非晶硅层；
对所述非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形，其中所述多晶硅图形中的每一非晶硅层均为弯折结构；
在所述非晶硅图形中的每一非晶硅层形成两断开空间，所述两断开空间分别形成于所述非晶硅层的相邻的弯折部位；
对已形成断开空间的非晶硅图形进行激光照射处理，以使得位于每一断开空间两侧的非晶硅层内的晶粒朝着对应的断开空间方向生长，并在所述断开空间内结晶形成薄膜晶体管的沟道。
为解决上述技术问题，本发明还构造了一种补偿电路，包括至少一个的薄膜晶体管，所述薄膜晶体管包括基板以及形成于所述基板上的沟道；其中所述沟道为弯折结构，包括有第一结晶单元和第二结晶单元；
所述第一结晶单元和所述第二结晶单元位于所述沟道相邻的弯折部件上，所述第一结晶单元包括第一结晶区和第二结晶区，所述第二结晶单元包括第三结晶区和第四结晶区；
其中所述第一结晶区和所述第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直；所述第三结晶区和所述第四结晶区中的晶粒边界均与所述第三结晶区和第四结晶区之间的界面垂直。
 有益效果
本发明通过在非晶硅层的相邻弯折部形成两断开空间，每一断开空间将对应的非晶硅层分开为相邻的两个区间，在通过激光照射后，相邻的两个区间的晶粒会朝着对应的断开空间的方向生长并在断开空间交汇，进而结晶形成两结晶区，两结晶区中的晶粒边界与两结晶区之间的界面垂直，由此可提高形成的沟道的电子迁移率，并使得形成的TFT的电性更加均匀。
 附图说明
图1A-1M为本发明实施例中使用非晶硅薄膜进行结晶形成沟道的过程示意图；
图2A到2D所示为按照图1A-1M的处理过程制成的沟道来形成薄膜晶体管阵列基板的过程示意图；
图3为将图2A至2D制程形成的薄膜晶体管阵列基板应用到第一实施例补偿电路的示意图；
图4为将图2A至2D制程形成的薄膜晶体管阵列基板应用到第二实施例补偿电路的示意图；
图5为将图2A至2D制程形成的薄膜晶体管阵列基板应用到第二实施例补偿电路的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参阅图1A-1M，图1A-1M为本发明实施例中薄膜晶体管阵列基板的沟道形成方法的过程示意图。
在图1A中，提供基板100，在所述基板100上形成缓冲层101（Buffer）。
其中所述基板100譬如为玻璃基板、可挠性塑料基板、晶圆基板或散热基板。所述缓冲层101优选由氮化硅(SiNx)或氧化硅(Si02)形成，所述缓冲层101主要是防止杂质从所述基板100扩散。
在图1B中，在所述缓冲层101上形成非晶硅(a-Si：H)层102，在具体实施过程中，本发明实施例优选使用化学蒸气沉积(CVD)在所述缓冲层101上沉积形成所述非晶硅层102，其中形成非晶硅层102后的俯视图请参阅图1C。
在图1D中，对所述非晶硅层102进行第一次刻蚀处理，形成非晶硅图形。
请一并参阅图1D，图1D为对所述非晶硅层102进行第一次刻蚀处理后的俯视图，其上具有缓冲层101和非晶硅层102的基板100上限定有多个象素区P和多个TFT区T，其中所述TFT区T位于在各个象素区P的角上，而经第一次刻蚀处理后的非晶硅图形包括有多个非晶硅层102，每一非晶硅层102位于TFT区T。
其中本发明实施例中的第一次刻蚀可以采用干法刻蚀或者湿法刻蚀。
请一并参阅图1E，图1E为所述非晶硅层102的结构示意图，所述非晶硅层102为弯折结构，其包括第一平层201和第二平层202，在本实施例中，所述第一平层201和所述第二平层202相互连接且相互垂直。本发明实施例将所述非晶硅层102刻蚀形成弯折结构，其主要目的为形成后续的双栅（Daul Gate）TFT。
在图1F中，对经第一次刻蚀处理后的非晶硅层102继续进行第二次刻蚀处理，以在所述非晶硅层图形的每一非晶硅层102形成断开空间。
更具体的，请一并参阅图1G，所述断开空间包括形成于所述第一平层201的第一断开空间R1，以及形成于所述第二平层202的第二断开空间R2。
请一并参阅图1H和图1I，图1F为沿图1G中G-G'的剖视图，图1I为图1H的俯视图。其中所述第一断开空间R1沿长度方向D延伸，且所述第一断开空间R1具有一垂直于所述长度方向D的宽度L，所述宽度L的范围优选为1~3微米（um），所述第一断开空间R1将所述非晶硅层102分为两个区间：第一区间301和第二区间302。同理，所述第二断开空间R2的结构类似，譬如第二空间的宽度范围优选为1~3微米等，此处不再赘述。
在具体实施过程中，所述二次刻蚀处理可使用干法刻蚀、湿法刻蚀或者激光刻蚀，此处不再详述。
在图1J中，对已形成断开空间的非晶硅层102进行激光照射处理，以形成沟道103，请一并参阅图1K，图1K为图1H经激光照射后的俯视图，图1L是对应图1G的图示。
图1K是以第一断开空间R1为例，在所述激光照射下，所述第一断开空间R1两侧的第一区间301和第二区间302对应的非晶硅层102因为温度差形成侧向长晶。
具体的，所述第一区间301和第二区间302中靠近所述第一断开空间R1的晶粒会朝着所述第一断开空间R1的方向进行生长，其中所述第一区间301中靠近所述第一断开空间R1的晶粒朝向所述第一断开空间R1生长（从左向右），并在所述第一断开空间R1形成第一结晶区401；所述第二区间302靠近所述第一断开空间R1的晶粒朝向所述第一断开空间R1生长（从右向左），并在所述第一断开空间R1形成第二结晶区402。所述第一结晶区401和所述第二结晶区402的晶粒在断开空间M的中轴Q处交汇，停止生长并结晶。所述第一结晶区401和第二结晶区402构成第一结晶单元F1，所述第一结晶单元F1对应所述第一断开空间R1。本发明实施例中，所述第一结晶区401和所述第二结晶区402中晶粒的晶粒边界垂直于所述第一结晶区401和所述第二结晶区402之间的平面，由此大幅提高了其后形成的TFT沟道的电子迁移率（mobility），并保证了TFT电性的均匀。
同理，请一并参阅图1L，在对应所述第二断开空间R2处形成有第二结晶单元F2，所述第二结晶单元F2包括有第三结晶区403和第四结晶区404，所述第三结晶区403和第四结晶区404中的晶粒边界均与所述第三结晶区403和第四结晶区404之间的界面垂直，关于所述第二结晶单元F2的详细形成过程请参阅针对第一结晶单元F1的详细描述，此处不再赘述。
请再参阅图1L，其中第一结晶单元F2中，第一结晶区401和第二结晶区402之间的交汇线（图未标示）与第三结晶区403和第四结晶区404之间的交汇线（图未标示）交叉，优选为垂直。
图1M为形成沟道103后的俯视图，其中所述沟道103由图1F中的具有断开空间的非晶硅层102经激光照射形成。所述沟道103位置对应着TFT区T，各个所述沟道103作为薄膜晶体管(TFT)中的有源层，具体请参阅图2A-2D的描述。
本发明通过在非晶硅层的相邻弯折部形成两断开空间，每一断开空间将对应的非晶硅层分开为相邻的两个区间，在通过激光照射后，相邻的两个区间的晶粒会朝着对应的断开空间的方向生长并在断开空间交汇，进而结晶形成两结晶区，两结晶区中的晶粒边界与两结晶区之间的界面垂直，由此可提高形成的TFT沟道的电子迁移率，并使得TFT的电性更加均匀。
其中，在通过激光照射所述具有断开空间的非晶硅层102（图1F）时，所述激光的扫描方向优选与断开空间的长度方向垂直，或者是与所述断开空间的长度方向平行，当然也可以与所述断开空间的长度方向的夹角在0至90度的区间内，所述激光的扫描间距的范围优选在0至30微米之间，所述扫描间距为相邻激光线之间的距离。
图2A到2D所示为按照图1A-1M的处理过程制成的沟道来形成薄膜晶体管阵列基板的处理步骤。
在图2A中，提供一基板501，在所述基板501上形成缓冲层502。之后通过上述步骤1A-1M在TFT区内要形成薄膜晶体管（TFT）的位置形成沟道503。所述缓冲层502上的沟道503具有岛状形状。所述沟道503被划分成有源区503a、源极和漏极区503b。所述源极和所述漏极区503b被设置在有源区503a两侧。之后在所述缓冲层501上形成一层氮化硅或氧化硅绝缘材料504覆盖所述沟道503。
在图2B中，在所述绝缘材料504上沉积一金属导电材料。之后同时对所述导电材料和所述绝缘材料504进行构图，以在所述沟道503上连续形成栅极绝缘层505和栅极506。之后在所述沟道503的暴露部分也就是源极和漏极区503b上掺杂p-型或n-型离子的杂质。在掺杂杂质的同时，所述栅极506作为离子塞防止杂质渗入有源区503a。
在掺杂之后对掺杂杂质的所述源极和所述漏极区503b进行退火处理，激活掺杂在所述源极和所述漏极区503b内的离子。同时执行使所述源极和所述漏极区503b恢复多晶态的步骤，避免所述源极和漏极区503b的半导体构造可能会因离子掺杂过量从多晶态变成非晶态。
在图2C中，在所述基板501的整个表面上形成一个绝缘层507来覆盖所述栅极506和所述栅极绝缘层505。之后对所述绝缘层507构图形成分别暴露出所述源极和所述漏极区503b的第一接触孔508和第二接触孔509。其中所述绝缘层507可以包括氧化硅和氮化硅。
在图2D中，在所述绝缘层507上沉积一个金属层并且构图，形成源极510和漏极511。其中所述源极210通过所述第一接触孔508接触到所述源极区503b，而所述漏极511通过所述第二接触孔509接触到所述漏极区503b。所述源极510、漏极511、栅极506以及多晶硅图形503共通构成一薄膜晶体管（TFT）。
本发明实施例还提供一薄膜晶体管阵列基板（TFT基板），所述薄膜晶体管阵列基板包括有基板、形成于所述基板上的缓冲层、形成于所述缓冲层上的沟道、栅极绝缘层、栅极、绝缘层、源极以及漏极。
其中所述沟道为弯折结构，包括第一结晶单元和第二结晶单元。所述第一结晶单元和所述第二结晶单元位于所述沟道相邻的弯折部件上，所述第一结晶单元包括第一结晶区和第二结晶区，所述第二结晶单元包括第三结晶区和第四结晶区。
其中所述第一结晶区和所述第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直；所述第三结晶区和所述第四结晶区中的晶粒边界均与所述第三结晶区和第四结晶区之间的界面垂直。
具体的，所述第一结晶区和所述第二结晶区由处于同一断开空间（譬如第一断开空间）两侧的非晶硅层经激光照射形成，所述断开空间沿一长度方向延伸，所述第一结晶区和所述第二结晶区的宽度与所述长度方向垂直，该宽度的范围为1~3微米。
具体的，所述第三结晶区和所述第四结晶区由处于同一断开空间（譬如第二断开空间）两侧的非晶硅层经激光照射形成，所述断开空间沿一长度方向延伸，所述第三结晶区和所述第四结晶区的宽度与所述长度方向垂直，该宽度的范围为1~3微米。
关于所述薄膜晶体管阵列基板中薄膜晶体管以及沟道的详细形成过程请参阅图1A-1M以及图2A-2D的详细描述，此处不再赘述。
请参阅图3，图3是本发明第一实施例补偿电路的结构示意图。所述补偿电路包括：六个薄膜晶体管TFT，依次标识为M1、M2、M3、M4、M5和M6；电容C1和C2；电源电压VDD；接地电压VSS；电路输入电压Vini；数据线电压Vdata；扫描线Scan N以及Scan N-1，发光二极管EM。
其中在图3所示的第一实施例补偿电路中，所述六个薄膜晶体管中的至少一个膜晶体管选用为图2A到2D的制程形成，而图2A到2D中的沟道为按照1A-1M的处理过程制成，譬如图3中标号为M5和M6的膜晶体管均包括通过1A-1M形成的具有双栅（Daul Gate）结构的沟道，具体请参阅上文的描述，此处不再赘述。
请参阅图4，图4为本发明第二实施例中补偿电路的结构示意图。所述补偿电路包括：五个薄膜晶体管TFT，依次标识为N1、N2、N3、N4和N5；电容C；扫描线G1、G2和G3；阳极ANODE、阴极CATHODE和电压V0；数据线DATA；有机发光二极管（Organic Light-Emitting Diode，OLED）。
其中在图4所示的第二实施例补偿电路中，所述五个薄膜晶体管中的至少一个膜晶体管选用为图2A到2D的制程形成，而图2A到2D中的沟道为按照1A-1M的处理过程制成，譬如图4中标号为N2和N3的膜晶体管均包括通过1A-1M形成的具有双栅（Daul Gate）结构的沟道，具体请参阅上文的描述，此处不再赘述。
请参阅图5，图5为本发明第三实施例中补偿电路的结构示意图。所述补偿电路包括：五个薄膜晶体管TFT，依次标识为Q1、Q2、Q3、Q4和Q5；电容C；扫描线G1、G2和G3；阳极ANODE、阴极CATHODE和电压V0；数据线DATA；有机发光二极管（Organic Light-Emitting Diode，OLED）。
其中在图5所示的第三实施例补偿电路中，所述五个薄膜晶体管中的至少一个膜晶体管选用为图2A到2D的制程形成，而图2A到2D中的沟道为按照1A-1M的处理过程制成，譬如图5中标号为Q2和Q3的膜晶体管均包括通过1A-1M形成的具有双栅（Daul Gate）结构的沟道，具体请参阅上文的描述，此处不再赘述。
本发明通过在非晶硅层的相邻弯折部形成两断开空间，每一断开空间将对应的非晶硅层分开为相邻的两个区间，在通过激光照射后，相邻的两个区间的晶粒会朝着对应的断开空间的方向生长并在断开空间交汇，进而结晶形成两结晶区，两结晶区中的晶粒边界与两结晶区之间的界面垂直，由此可提高形成的沟道的电子迁移率，并使得形成的TFT的电性更加均匀。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
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Claims (17)

  1. 一种薄膜晶体管的沟道形成方法，其中所述方法包括以下步骤：
    提供基板，在所述基板上形成非晶硅层；
    对所述非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形，其中所述多晶硅图形中的每一非晶硅层均为弯折结构；
    在每一非晶硅层形成两断开空间，所述两断开空间分别形成于所述非晶硅层的相邻的弯折部位；其中每一断开空间沿一长度方向延伸，该断开空间具有一与该长度方向垂直的宽度，所述宽度的范围为1~3微米；
    对已形成断开空间的非晶硅图形进行激光照射处理，以使得位于每一断开空间两侧的非晶硅层内的晶粒在温度差的作用下朝着对应的断开空间方向生长，并在所述断开空间内结晶形成薄膜晶体管的沟道，其中所述激光的扫描间距的范围为0-30微米。
  2. 根据权利要求1所述的薄膜晶体管的沟道形成方法，其中所述断开空间包括第一断开空间和第二断开空间，所述非晶硅层包括相邻的第一平层和第二平层，所述第一平层和第二平层相互弯折；
    其中所述第一断开空间形成于所述第一平层，所述第二断开空间形成于所述第二平层。
  3. 根据权利要求1所述的薄膜晶体管的沟道形成方法，其中所述沟道包括对应所述第一断开空间的第一结晶单元，以及对应所述第二断开空间的第二结晶单元；所述第一结晶单元包括第一结晶区和第二结晶区，所述第二结晶单元包括第三结晶区和第四结晶区；
    其中所述第一结晶区和第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直；所述第三结晶区和第四结晶区中的晶粒边界均与所述第三结晶区和第四结晶区之间的界面垂直。
  4. 根据权利要求1所述的薄膜晶体管的沟道形成方法，其中每一断开空间沿一长度方向延伸，所述激光的扫描方向与该长度方向垂直。
  5. 根据权利要求1所述的薄膜晶体管的沟道形成方法，其中每一断开空间沿一长度方向延伸，所述激光的扫描方向与该长度方向平行。
  6. 根据权利要求1所述的薄膜晶体管的沟道形成方法，其中每一断开空间沿一长度方向延伸，所述激光的扫描方向与该长度方向的夹角为0至90度。
  7. 一种薄膜晶体管的沟道形成方法，其中所述方法包括以下步骤：
    提供基板，在所述基板上形成非晶硅层；
    对所述非晶硅层进行刻蚀处理，以形成包括多个非晶硅层的非晶硅图形，其中所述多晶硅图形中的每一非晶硅层均为弯折结构；
    在每一非晶硅层形成两断开空间，所述两断开空间分别形成于所述非晶硅层的相邻的弯折部位；
    对已形成断开空间的非晶硅图形进行激光照射处理，以使得位于每一断开空间两侧的非晶硅层内的晶粒在温度差的作用下朝着对应的断开空间方向生长，并在所述断开空间内结晶形成薄膜晶体管的沟道。
  8. 根据权利要求7所述的薄膜晶体管的沟道形成方法，其中所述断开空间包括第一断开空间和第二断开空间，所述非晶硅层包括相邻的第一平层和第二平层，所述第一平层和第二平层相互弯折；
    其中所述第一断开空间形成于所述第一平层，所述第二断开空间形成于所述第二平层。
  9. 根据权利要求7所述的薄膜晶体管的沟道形成方法，其中每一断开空间沿一长度方向延伸，该断开空间具有一与所述长度方向垂直的宽度，所述宽度的范围为1~3微米。
  10. 根据权利要求7所述的薄膜晶体管的沟道形成方法，其中所述沟道包括对应所述第一断开空间的第一结晶单元，以及对应所述第二断开空间的第二结晶单元；所述第一结晶单元包括第一结晶区和第二结晶区，所述第二结晶单元包括第三结晶区和第四结晶区；
    其中所述第一结晶区和第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直；所述第三结晶区和第四结晶区中的晶粒边界均与所述第三结晶区和第四结晶区之间的界面垂直。
  11. 根据权利要求7所述的薄膜晶体管的沟道形成方法，其中每一断开空间沿一长度方向延伸，所述激光的扫描方向与该长度方向垂直。
  12. 根据权利要求7所述的薄膜晶体管的沟道形成方法，其中每一断开空间沿一长度方向延伸，所述激光的扫描方向与该长度方向平行。
  13. 根据权利要求7所述的薄膜晶体管的沟道形成方法，其中每一断开空间沿一长度方向延伸，所述激光的扫描方向与该长度方向的夹角为0至90度。
  14. 根据权利要求7所述的薄膜晶体管的沟道形成方法，其中所述激光的扫描间距的范围为0-30微米。
  15. 一种补偿电路，其中包括至少一个的薄膜晶体管，所述薄膜晶体管包括基板以及形成于所述基板上的沟道；其中所述沟道为弯折结构，包括有第一结晶单元和第二结晶单元；
    所述第一结晶单元和所述第二结晶单元位于所述沟道相邻的弯折部件上，所述第一结晶单元包括第一结晶区和第二结晶区，所述第二结晶单元包括第三结晶区和第四结晶区；
    其中所述第一结晶区和所述第二结晶区中的晶粒边界均与所述第一结晶区和第二结晶区之间的界面垂直；所述第三结晶区和所述第四结晶区中的晶粒边界均与所述第三结晶区和第四结晶区之间的界面垂直。
  16. 根据权利要求15所述的补偿电路，其中所述第一结晶区和所述第二结晶区由处于同一断开空间两侧的非晶硅层经激光照射形成，所述断开空间沿一长度方向延伸，该断开空间的宽度与所述长度方向垂直，所述宽度的范围为1~3微米。
  17. 根据权利要求15所述的补偿电路，其中所述第三结晶区和所述第四结晶区由处于同一断开空间两侧的非晶硅层经激光照射形成，所述断开空间沿一长度方向延伸，该断开空间的宽度与所述长度方向垂直，所述宽度的范围为1~3微米。
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