WO2017219421A1 - 一种tft阵列基板及其制作方法、液晶显示装置 - Google Patents

一种tft阵列基板及其制作方法、液晶显示装置 Download PDF

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Publication number
WO2017219421A1
WO2017219421A1 PCT/CN2016/090586 CN2016090586W WO2017219421A1 WO 2017219421 A1 WO2017219421 A1 WO 2017219421A1 CN 2016090586 W CN2016090586 W CN 2016090586W WO 2017219421 A1 WO2017219421 A1 WO 2017219421A1
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Prior art keywords
semiconductor layer
drain
source
substrate
array substrate
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PCT/CN2016/090586
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English (en)
French (fr)
Inventor
吕晓文
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深圳市华星光电技术有限公司
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Priority to US15/123,776 priority Critical patent/US20180197960A1/en
Publication of WO2017219421A1 publication Critical patent/WO2017219421A1/zh

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    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate, a method for fabricating the same, and a liquid crystal display device.
  • TFT Thin Film Transistor
  • TFT Thin Film Transistor
  • LCD Thin Film Transistor Liquid Crystal Display
  • TFT In TFT During the preparation process, the contact interface treatment of M2 (the metal layer where the source/drain is located) and A-Si (amorphous silicon) is a very important part, because the metal and A-Si have potential energy difference, which is easy to form Xiao. Special contact. But TFT devices require electrical contact, and such contacts must be low impedance rather than rectified. For this reason, it is often necessary to dope the semiconductor so that M2 and A-Si form an ohmic contact, but even for A-Si With P doping, the resistance of metals and semiconductors is still large.
  • M2 the metal layer where the source/drain is located
  • A-Si amorphous silicon
  • the technical problem to be solved by the present invention is to provide a TFT array substrate, a method for fabricating the same, and a liquid crystal display device, which can reduce the contact resistance between the semiconductor layer and the metal layer, and improve the electrical characteristics of the TFT device.
  • a technical solution adopted by the present invention is to provide a TFT array substrate including a substrate and a TFT disposed on the substrate; the TFT includes a gate and a gate sequentially disposed on the substrate An insulating layer, the semiconductor layer, and a source/drain layer, wherein the source and drain layers include a source and a drain; wherein the source and the drain are metal; wherein the semiconductor layer and the source and/or drain
  • the contact surface of the pole has a concave-convex structure.
  • the contact surface of the semiconductor layer with the source and the drain includes a plurality of intersecting grooves.
  • the plurality of intersecting grooves include a plurality of grooves extending in the first direction and a plurality of grooves extending in the second direction, wherein the grooves extending in the first direction and the grooves extending in the second direction are mutually staggered.
  • the contact surface of the semiconductor layer with the source and the drain includes a plurality of non-intersecting recesses.
  • the semiconductor layer is a doped amorphous silicon layer.
  • the semiconductor layer is IGZO.
  • another technical solution adopted by the present invention is to provide a method for fabricating a TFT array substrate, the method comprising: providing a substrate; sequentially forming a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate; An uneven structure is formed on the upper surface of the semiconductor layer; a source and a drain are formed on the semiconductor layer.
  • the uneven structure is formed on the upper surface of the semiconductor layer, and the uneven structure is formed on the upper surface of the semiconductor layer by imprinting, laser processing, or photolithography.
  • a liquid crystal display device including a display panel and a backlight
  • the display panel includes a TFT array substrate, a color filter substrate, and a liquid crystal layer therebetween.
  • the TFT array substrate includes a substrate and a TFT disposed on the substrate; the TFT includes a semiconductor layer and a source and a drain disposed on the semiconductor layer, wherein the contact surface of the semiconductor layer and the source and/or the drain has a concave-convex structure .
  • the contact surface of the semiconductor layer with the source and the drain includes a plurality of intersecting grooves.
  • the plurality of intersecting grooves include a plurality of grooves extending in the first direction and a plurality of grooves extending in the second direction, wherein the grooves extending in the first direction and the grooves extending in the second direction are mutually staggered.
  • the contact surface of the semiconductor layer with the source and the drain includes a plurality of non-intersecting recesses.
  • the semiconductor layer is a doped amorphous silicon layer.
  • the semiconductor layer is IGZO.
  • the TFT includes a gate, a gate insulating layer, a semiconductor layer, and a source/drain layer sequentially disposed on the substrate, wherein the source and drain layers include a source and a drain.
  • the TFT array substrate of the present invention includes a substrate and a TFT disposed on the substrate; the TFT includes a semiconductor layer and a source and a drain disposed on the semiconductor layer, wherein The contact surface of the semiconductor layer with the source and/or the drain has a concave-convex structure.
  • the contact area between the semiconductor layer and the metal layer (source/drain layer) can be increased, the distance between the metal layer and the channel can be reduced, and the contact resistance between the semiconductor layer and the metal layer can be reduced, and the semiconductor surface can be reduced.
  • the Schottky barrier improves the electrical properties of TFT devices.
  • FIG. 1 is a schematic structural view of an embodiment of a TFT array substrate of the present invention.
  • FIG. 2 is a schematic side view showing the contact between a semiconductor layer and a source/drain layer in an embodiment of the TFT array substrate of the present invention
  • FIG. 3 is a plan view showing a semiconductor layer in an embodiment of a TFT array substrate of the present invention.
  • FIG. 4 is another top plan view of a semiconductor layer in an embodiment of a TFT array substrate of the present invention.
  • FIG. 5 is another top plan view of a semiconductor layer in an embodiment of a TFT array substrate of the present invention.
  • FIG. 6 is a schematic flow chart of an embodiment of a method for fabricating a TFT array substrate according to the present invention.
  • Fig. 7 is a schematic view showing the structure of an embodiment of a liquid crystal display device of the present invention.
  • FIG. 1 is a schematic structural view of an embodiment of a TFT array substrate according to the present invention.
  • the TFT array substrate includes a substrate 10 and a TFT disposed on the substrate 10.
  • the TFT includes a gate electrode 11 sequentially disposed on the substrate 10, a gate insulating layer 12, a semiconductor layer 13, and a source/drain layer 14, wherein the source/drain layer 14 includes a source electrode 141 and a drain electrode 142.
  • the substrate 10 may be a glass substrate or a plastic substrate.
  • the gate 11 and the source drain layer 14 are metal layers.
  • the gate insulating layer 12 may be SiOx or SiNx, or may be a mixture of SiOx and SiNx, and may further include a layer of SiOx and a layer of SiNx.
  • the semiconductor layer 13 may be one of amorphous silicon (A-Si), polycrystalline silicon (P-Si), or low temperature polycrystalline silicon (LTPS), or may be doped three kinds of semiconductors.
  • the semiconductor layer 13 includes amorphous silicon (A-Si) 131 and an N+ doped region or a P+ doped region (at the numeral 132 in FIG. 1) formed on the amorphous silicon 131.
  • the semiconductor layer 13 can also be IGZO (indium gallium zinc) Oxide, indium gallium zinc oxide).
  • IGZO indium gallium zinc Oxide
  • the TFT includes a semiconductor layer 13 and a source 141 and a drain 142 disposed on the semiconductor layer 13, wherein the contact surface of the semiconductor layer 13 with the source 141 and/or the drain 142 has a concave-convex structure.
  • FIG. 2 is a schematic side view showing a contact between a semiconductor layer and a source/drain layer in an embodiment of the TFT array substrate of the present invention
  • FIG. 3 is a plan view of the semiconductor layer in an embodiment of the TFT array substrate of the present invention.
  • the shaded portion indicates a convex portion
  • the blank portion indicates a concave portion.
  • the contact of the semiconductor layer 13 with the source/drain layer 14 is a Schottky contact
  • the Schottky contact refers to a band gap of the semiconductor at the interface when the metal and the semiconductor material are in contact, forming a Schottky barrier, a barrier
  • the presence of this results in a large interface resistance, resulting in poor electrical characteristics of the TFT.
  • the electrical characteristics of the TFT are improved by doping on the semiconductor layer 13, the effect is not good.
  • the contact area thereof is larger than that of the planar contact, thereby reducing the semiconductor layer 13 and the source and drain. Contact resistance between layers 14.
  • FIG. 4 is another plan view of a semiconductor layer in an embodiment of the TFT array substrate of the present invention, in which a hatched portion indicates a bump and a blank portion indicates a recess.
  • the contact surface of the semiconductor layer 13 with the source and the drain includes a plurality of intersecting grooves.
  • the plurality of intersecting grooves include a plurality of grooves extending in the first direction and a plurality of grooves extending in the second direction, wherein the grooves extending in the first direction and the grooves extending in the second direction are interdigitated .
  • first direction and the second direction may be two directions perpendicular to each other as shown in FIG. 4, and in other embodiments, the first direction and the second direction may be any angle between 0-90 degrees. And the first direction may be a direction at an angle to a frame of the display panel.
  • the groove includes two grooves which are mutually staggered in direction, the number of grooves can be increased, thereby further increasing the contact area of the semiconductor layer and the source and drain layers.
  • FIG. 5 is still another plan view of a semiconductor layer in an embodiment of the TFT array substrate of the present invention, in which a hatched portion indicates a bump and a blank portion indicates a recessed hole.
  • the contact surface of the semiconductor layer 13 with the source and the drain includes a plurality of non-intersecting recesses.
  • the contact area of the semiconductor layer and the source and drain layers is further increased.
  • the array substrate may further include a pixel electrode, a common electrode, and the like formed on the TFT.
  • the TFT array substrate of the present embodiment includes a substrate and a TFT disposed on the substrate; the TFT includes a semiconductor layer and a source and a drain disposed on the semiconductor layer, wherein the semiconductor layer and the source and/or The contact surface of the drain has a concave-convex structure.
  • the contact area between the semiconductor layer and the metal layer (source/drain layer) can be increased, the distance between the metal layer and the channel can be reduced, and the contact resistance between the semiconductor layer and the metal layer can be reduced, and the semiconductor surface can be reduced.
  • the Schottky barrier improves the electrical properties of TFT devices.
  • FIG. 6 is a schematic flow chart of an implementation manner of a method for fabricating a TFT array substrate according to the present invention. The method includes:
  • the substrate may be a transparent glass substrate or a plastic substrate.
  • S62 sequentially forming a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate.
  • a gate electrode, a gate insulating layer and a semiconductor layer are formed on the substrate, generally by physical vapor deposition or chemical vapor deposition.
  • the process of forming a semiconductor layer may specifically include:
  • A-Si amorphous silicon
  • polysilicon includes low temperature polysilicon (LTPS) and high temperature polysilicon (HTPS).
  • S63 A concave-convex structure is formed on the upper surface of the semiconductor layer.
  • the step S63 may be specifically: forming an uneven structure on the upper surface of the semiconductor layer by imprinting, laser processing or photolithography.
  • the source and the drain are formed in the semiconductor layer in such a manner that a metal is deposited on the semiconductor layer, the metal is first filled in the uneven structure on the semiconductor layer, so that the contact area between the semiconductor and the metal is increased. .
  • a pixel electrode, a common electrode, and the like may also be formed on the TFT.
  • the method for fabricating the TFT array substrate of the present embodiment includes: providing a substrate; sequentially forming a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate; and forming a concave-convex structure on the upper surface of the semiconductor layer; A source and a drain are formed on the semiconductor layer.
  • the contact area between the semiconductor layer and the metal layer (source/drain layer) can be increased, the distance between the metal layer and the channel can be reduced, and the contact resistance between the semiconductor layer and the metal layer can be reduced, and the semiconductor surface can be reduced.
  • the Schottky barrier improves the electrical properties of TFT devices.
  • FIG. 7 is a schematic structural diagram of an embodiment of a liquid crystal display device according to the present invention.
  • the liquid crystal display device includes a display panel 71 and a backlight 72.
  • the display panel 71 includes a TFT array substrate 711, a color filter substrate 712, and a liquid crystal layer therebetween. 713, wherein the TFT array substrate 711 includes a substrate and a TFT disposed on the substrate; the TFT includes a semiconductor layer and a source and a drain disposed on the semiconductor layer, wherein a contact surface of the semiconductor layer with the source and/or the drain It has a concave-convex structure.
  • the array substrate 711 is the array substrate as described in the above embodiments, and the structure, the manufacturing method, and the implementation principles and steps are all referred to the above embodiments, and details are not described herein again.

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Abstract

提供了一种TFT阵列基板及其制作方法、液晶显示装置， TFT阵列基板包括基板（10）以及设置于基板（10）上的TFT；TFT包括半导体层（13）以及设置于半导体层（13）上的源极（141）和漏极（142），其中，半导体层（13）与源极（141）和/或漏极（142）的接触面呈凹凸结构。通过这种方式，能够减小半导体层和金属层之间的接触电阻，提高TFT器件的电学特性。

Description

一种TFT阵列基板及其制作方法、液晶显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种TFT阵列基板及其制作方法、液晶显示装置。
【背景技术】
TFT（Thin Film Transistor）是薄膜晶体管的缩写。TFT是指液晶显示器上的每一液晶像素点都是由集成在其后的薄膜晶体管来驱动，从而可以做到高速度高亮度高对比度显示屏幕信息，TFT-LCD（薄膜晶体管液晶显示器）是多数液晶显示器的一种。
在TFT 的制备过程中，M2（源/漏极所在的金属层）和A-Si（非晶硅）的接触界面处理是其中非常重要的一环，因为金属和A-Si存在势能差，易形成肖特基接触。但是TFT器件需要电学接触，并且这种接触必须是低阻的而不是整流的。为此，常常需对半导体进行掺杂，使M2和A-Si形成欧姆接触，但是即使是对A-Si 进行了P掺杂，金属和半导体的阻值仍然很大。
【发明内容】
本发明主要解决的技术问题是提供一种TFT阵列基板及其制作方法、液晶显示装置，能够减小半导体层和金属层之间的接触电阻，提高TFT器件的电学特性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种TFT阵列基板，该TFT阵列基板包括基板以及设置于基板上的TFT；该TFT包括依次设置于基板上的栅极、栅极绝缘层、所述半导体层以及源漏层，其中，所述源漏层包括源极和漏极；其中，所述源极和所述漏极为金属；其中，半导体层与源极和/或漏极的接触面呈凹凸结构。
其中，半导体层与源极和漏极的接触面包括多条相交的凹槽。
其中，多条相交的凹槽包括多条第一方向延伸的凹槽以及多条第二方向延伸的凹槽，其中，第一方向延伸的凹槽和第二方向延伸的凹槽相互交错。
其中，半导体层与源极和漏极的接触面包括多个不相交的凹孔。
其中，半导体层是经过掺杂的非晶硅层。
其中，半导体层是IGZO。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT阵列基板的制作方法，该方法包括：提供一基板；在基板上依次形成栅极、栅极绝缘层、半导体层；在半导体层的上表面制作凹凸状结构；在半导体层上形成源极和漏极。
其中，在半导体层的上表面制作凹凸状结构，包括：在半导体层的上表面通过压印、激光加工或光刻制作凹凸状结构。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，该液晶显示装置包括显示面板和背光，显示面板包括TFT阵列基板、彩膜基板以及之间的液晶层，其中，TFT阵列基板包括基板以及设置于基板上的TFT；TFT包括半导体层以及设置于半导体层上的源极和漏极，其中，半导体层与源极和/或漏极的接触面呈凹凸结构。
其中，半导体层与源极和漏极的接触面包括多条相交的凹槽。
其中，多条相交的凹槽包括多条第一方向延伸的凹槽以及多条第二方向延伸的凹槽，其中，第一方向延伸的凹槽和第二方向延伸的凹槽相互交错。
其中，半导体层与源极和漏极的接触面包括多个不相交的凹孔。
其中，半导体层是经过掺杂的非晶硅层。
其中，半导体层是IGZO。
其中，TFT包括依次设置于基板上的栅极、栅极绝缘层、半导体层以及源漏层，其中，源漏层包括源极和漏极。
本发明的有益效果是：区别于现有技术的情况，本发明的TFT阵列基板包括基板以及设置于基板上的TFT；TFT包括半导体层以及设置于半导体层上的源极和漏极，其中，半导体层与源极和/或漏极的接触面呈凹凸结构。通过上述方式，能够增加半导体层和金属层（源漏层）的接触面积，减小金属层与沟道之间的距离，从而减小半导体层和金属层之间的接触电阻，降低了半导体表面的肖特基势垒，提高了TFT器件的电学特性。
【附图说明】
图1是本发明TFT阵列基板一实施方式的结构示意图；
图2是本发明TFT阵列基板一实施方式中半导体层和源漏层的接触侧视示意图；
图3是本发明TFT阵列基板一实施方式中半导体层的俯视图；
图4是本发明TFT阵列基板一实施方式中半导体层的另一俯视图；
图5是本发明TFT阵列基板一实施方式中半导体层的又一俯视图；
图6是本发明TFT阵列基板的制作方法一实施方式的流程示意图；
图7是本发明液晶显示装置一实施方式的结构示意图。
【具体实施方式】
参阅图1，图1是本发明TFT阵列基板一实施方式的结构示意图，该TFT阵列基板包括基板10以及设置于基板10上的TFT。
其中，该TFT包括依次设置于基板10上的栅极11、栅极绝缘层12、半导体层13以及源漏层14，其中，源漏层14包括源极141和漏极142。
可选的，基板10可以是玻璃基板或塑料基板。
可选的，栅极11和源漏层14是金属层。
可选的，栅极绝缘层12可以是SiOx或者SiNx，也可以是SiOx和SiNx的混合物，还可以包括一层SiOx和一层SiNx。
可选的，半导体层13可以是非晶硅（A-Si）、多晶硅（P-Si）或低温多晶硅（LTPS）中的一种，也可以是经过掺杂的上述三种半导体。例如，在一种实施方式中，半导体层13包括非晶硅（A-Si）131以及在非晶硅131上形成的N+掺杂区或者P+掺杂区（图1中的标号132处）。
可选的，半导体层13还可以是IGZO（indium gallium zinc oxide，铟镓锌氧化物）。
具体地，TFT包括半导体层13以及设置于半导体层13上的源极141和漏极142，其中，半导体层13与源极141和/或漏极142的接触面呈凹凸结构。
具体参阅图2和图3，图2是本发明TFT阵列基板一实施方式中半导体层和源漏层的接触侧视示意图，图3是本发明TFT阵列基板一实施方式中半导体层的俯视图，在图3中，阴影部分表示凸起，空白部分表示凹槽。
由于半导体层13与源漏层14的接触为肖特基接触，肖特基接触是指金属和半导体材料相接触的时候，在界面处半导体的能带弯曲，形成肖特基势垒，势垒的存在导致了大的界面电阻，致使TFT的电学特性不佳。虽然通过在半导体层13上进行掺杂，会使TFT的电学特性有所改善，但依然效果不好。
在本实施方式中，由于半导体层13的上表面为凹凸结构，使源漏层14在与半导体层13接触时，其接触面积相比于平面接触更大，从而降低了半导体层13与源漏层14之间的接触电阻。
如图4所示，图4是本发明TFT阵列基板一实施方式中半导体层的另一俯视图，其中，阴影部分表示凸起，空白部分表示凹槽。
其中，半导体层13与源极和漏极的接触面包括多条相交的凹槽。
可选的，多条相交的凹槽包括多条第一方向延伸的凹槽以及多条第二方向延伸的凹槽，其中，第一方向延伸的凹槽和第二方向延伸的凹槽相互交错。
可选的，第一方向和第二方向可以是如图4所示的互相垂直的两个方向，在其他实施方式中，第一方向和第二方向可以呈0-90°之间的任意角度，且第一方向可以是与显示面板的边框呈一定角度的方向。
由于凹槽包括两个相互交错的方向的凹槽，可以增加凹槽的数量，从而更加增加半导体层和源漏层的接触面积。
如图5所示，图5是本发明TFT阵列基板一实施方式中半导体层的又一俯视图，其中，阴影部分表示凸起，空白部分表示凹孔。
其中，半导体层13与源极和漏极的接触面包括多个不相交的凹孔。
由于半导体层13的上表面包括多个凹孔，从而更加增加半导体层和源漏层的接触面积。
另外，可以理解的，在其他实施方式中，阵列基板还可以包括形成于TFT上面的像素电极、公共电极等等。
区别于现有技术，本实施方式的TFT阵列基板包括基板以及设置于基板上的TFT；TFT包括半导体层以及设置于半导体层上的源极和漏极，其中，半导体层与源极和/或漏极的接触面呈凹凸结构。通过上述方式，能够增加半导体层和金属层（源漏层）的接触面积，减小金属层与沟道之间的距离，从而减小半导体层和金属层之间的接触电阻，降低了半导体表面的肖特基势垒，提高了TFT器件的电学特性。
参阅图6，图6是本发明TFT阵列基板的制作方法一实施方式的流程示意图，该方法包括：
S61：提供一基板。
可选的，该基板可以是透明的玻璃基板或者塑料基板。
S62：在基板上依次形成栅极、栅极绝缘层、半导体层。
其中，在基板上形成栅极、栅极绝缘层和半导体层，一般采用物理气相沉积或化学气相沉积的方法。
可选的，在一实施方式中，形成半导体层的过程可以具体包括：
沉积非晶硅（A-Si），再在非晶硅上进行N+掺杂或者P+掺杂；或者
沉积非晶硅，对非晶硅进行准分子镭射退火工艺以形成多晶硅（P-Si）。其中，多晶硅包括低温多晶硅（LTPS）和高温多晶硅（HTPS）两种。
S63：在半导体层的上表面制作凹凸状结构。
其中，该步骤S63可以具体为：在半导体层的上表面通过压印、激光加工或光刻制作凹凸状结构。
S64：在半导体层上形成源极和漏极。
由于在半导体层形成源极和漏极的方式是：在半导体层上沉积一层金属，因此，金属或首先填充在半导体层上的凹凸结构中，这样就使得半导体与金属的接触面积增大了。
另外，可以理解的，在其他实施方式中，在步骤S64之后，还可以在TFT上面形成像素电极、公共电极等等。
区别于现有技术，本实施方式的TFT阵列基板的制作方法包括：提供一基板；在基板上依次形成栅极、栅极绝缘层、半导体层；在半导体层的上表面制作凹凸状结构；在半导体层上形成源极和漏极。通过上述方式，能够增加半导体层和金属层（源漏层）的接触面积，减小金属层与沟道之间的距离，从而减小半导体层和金属层之间的接触电阻，降低了半导体表面的肖特基势垒，提高了TFT器件的电学特性。
参阅图7，图7是本发明液晶显示装置一实施方式的结构示意图，该液晶显示装置包括显示面板71和背光72，显示面板71包括TFT阵列基板711、彩膜基板712以及之间的液晶层713，其中，TFT阵列基板711包括基板以及设置于基板上的TFT；TFT包括半导体层以及设置于半导体层上的源极和漏极，其中，半导体层与源极和/或漏极的接触面呈凹凸结构。
具体地，该阵列基板711是如以上各个实施方式中所述的阵列基板，其结构、制作方法以及实施是原理和步骤均可以参考以上实施方式，这里不再赘述。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种TFT阵列基板，其中，所述TFT阵列基板包括基板以及设置于所述基板上的TFT；
    所述TFT包括依次设置于所述基板上的栅极、栅极绝缘层、所述半导体层以及源漏层，其中，所述源漏层包括源极和漏极；
    其中，所述源极和所述漏极为金属；
    其中，所述半导体层与所述源极和/或所述漏极的接触面呈凹凸结构。
  2. 根据权利要求1所述的阵列基板，其中，所述半导体层与所述源极和所述漏极的接触面包括多条相交的凹槽。
  3. 根据权利要求2所述的阵列基板，其中，所述多条相交的凹槽包括多条第一方向延伸的凹槽以及多条第二方向延伸的凹槽，其中，所述第一方向延伸的凹槽和所述第二方向延伸的凹槽相互交错。
  4. 根据权利要求1所述的阵列基板，其中，所述半导体层与所述源极和所述漏极的接触面包括多个不相交的凹孔。
  5. 根据权利要求1所述的阵列基板，其中，所述半导体层是经过掺杂的非晶硅层。
  6. 根据权利要求1所述的阵列基板，其中，所述半导体层是IGZO。
  7. 一种TFT阵列基板的制作方法，其中，包括：
    提供一基板；
    在所述基板上依次形成栅极、栅极绝缘层、半导体层；
    在所述半导体层的上表面制作凹凸状结构；
    在所述半导体层上形成源极和漏极。
  8. 根据权利要求7所述的方法，其中，所述在所述半导体层的上表面制作凹凸状结构，包括：
    在所述半导体层的上表面通过压印、激光加工或光刻制作凹凸状结构。
  9. 一种液晶显示装置，其中，所述液晶显示装置包括显示面板和背光，所述显示面板包括TFT阵列基板、彩膜基板以及所述TFT阵列基板和所述彩膜基板之间的液晶层；
    所述TFT阵列基板包括基板以及设置于所述基板上的TFT；
    所述TFT包括半导体层以及设置于所述半导体层上的源极和漏极，其中，所述半导体层与所述源极和/或所述漏极的接触面呈凹凸结构。
  10. 根据权利要求9所述的液晶显示装置，其中，所述半导体层与所述源极和所述漏极的接触面包括多条相交的凹槽。
  11. 根据权利要求10所述的液晶显示装置，其中，所述多条相交的凹槽包括多条第一方向延伸的凹槽以及多条第二方向延伸的凹槽，其中，所述第一方向延伸的凹槽和所述第二方向延伸的凹槽相互交错。
  12. 根据权利要求9所述的液晶显示装置，其中，所述半导体层与所述源极和所述漏极的接触面包括多个不相交的凹孔。
  13. 根据权利要求9所述的液晶显示装置，其中，所述半导体层是经过掺杂的非晶硅层。
  14. 根据权利要求9所述的液晶显示装置，其中，所述半导体层是IGZO。
  15. 根据权利要求9所述的液晶显示装置，其中，所述TFT包括依次设置于所述基板上的栅极、栅极绝缘层、所述半导体层以及源漏层，其中，所述源漏层包括所述源极和所述漏极。
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