WO2016201729A1 - 一种阵列基板及其制作方法、液晶显示器 - Google Patents

一种阵列基板及其制作方法、液晶显示器 Download PDF

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Publication number
WO2016201729A1
WO2016201729A1 PCT/CN2015/082823 CN2015082823W WO2016201729A1 WO 2016201729 A1 WO2016201729 A1 WO 2016201729A1 CN 2015082823 W CN2015082823 W CN 2015082823W WO 2016201729 A1 WO2016201729 A1 WO 2016201729A1
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layer
sub
via hole
gate electrode
shielding layer
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PCT/CN2015/082823
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English (en)
French (fr)
Inventor
黄秋平
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深圳市华星光电技术有限公司
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Priority to US14/765,809 priority Critical patent/US20160370621A1/en
Publication of WO2016201729A1 publication Critical patent/WO2016201729A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate, a method for fabricating the same, and a liquid crystal display.
  • OLED Organic Light-Emitting Diode
  • OELD Organic Electroluminesence Display
  • organic light-emitting display technology is widely used in small and medium-sized display panels.
  • the resolution requirements of display devices are getting higher and higher, the corresponding devices are getting smaller and smaller, and the characteristics of thin film transistors are becoming higher and higher.
  • the high refinement of the display device and the high-speed response of the driving circuit require that the TFT device can quickly realize the device switching, but the current driving capability of the semiconductor layer in the existing TFT device is generally difficult to adapt to the high definition and driving circuit of the display device.
  • the development of high-speed response is generally difficult to adapt to the high definition and driving circuit of the display device.
  • the technical problem to be solved by the present invention is to provide an array substrate, a manufacturing method thereof, and a liquid crystal display, which can enhance the current driving capability of the thin film transistor and improve the display quality.
  • a technical solution adopted by the present invention is to provide an array substrate including a substrate and a light shielding layer, a buffer layer, a semiconductor layer, a gate insulating layer and a gate electrode sequentially formed on the substrate;
  • the light shielding layer includes a first sub-shield layer and a second sub-shield layer;
  • the gate electrode includes a first sub-gate electrode and a second sub-gate electrode; and the buffer layer respectively corresponds to the first sub-shield layer and the second sub-shield
  • the layer is provided with a first via hole, and the gate insulating layer is respectively provided with a second via hole corresponding to the first sub-gate electrode and the second sub-gate electrode, respectively, so that the first sub-gate electrode passes through the corresponding and connected first pass
  • the hole and the second through hole are electrically connected to the first sub-shielding layer, and the second sub-gate electrode is electrically connected to the second sub-shielding layer through the corresponding and communicating first through hole and the second through hole
  • the through hole is disposed in the gate terminal region or the pixel electrode region.
  • the array substrate further includes an interlayer insulating layer, a source/drain electrode, a passivation layer, an organic insulating layer, and a transparent electrode layer sequentially formed on the gate electrode; wherein the passivation layer is provided with a third through hole, organic A fourth via hole is disposed on the insulating layer, and the transparent electrode layer is electrically connected to the source/drain electrode through the third via hole and the fourth via hole.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: sequentially forming a light shielding layer, a buffer layer, a semiconductor layer, and a gate insulating layer on a substrate; Forming a first via hole thereon, and forming a second via hole on the gate insulating layer to expose the light shielding layer portion; forming a gate electrode on the gate insulating layer to pass the gate electrode through the connected first via hole And the second through hole is connected to the light shielding layer.
  • the step of sequentially forming a light shielding layer, a buffer layer, a semiconductor layer, and a gate insulating layer on the substrate is specifically: depositing a light shielding layer on the substrate and patterning to form a first sub-light shielding layer and a second sub-light shielding layer; Forming a buffer layer on a sub-shield layer and a second sub-shielding layer; depositing a semiconductor layer on the buffer layer and patterning to form first semiconductor islands and second portions respectively corresponding to the first sub-shielding layer and the second sub-shielding layer a semiconductor island; a gate insulating layer is formed on the first semiconductor island and the second semiconductor island.
  • the step of forming a first via hole on the buffer layer and forming the second via hole on the gate insulating layer to expose the light shielding layer portion is specifically: respectively corresponding to the first sub-light shielding layer and the second layer on the buffer layer a first via hole is disposed on the sub-shielding layer, and a second via hole is disposed on the gate insulating layer corresponding to the first sub-gate electrode and the second sub-gate electrode respectively to make the first light shielding layer and the second light shielding layer portion bare.
  • the step of forming a gate electrode on the gate insulating layer to connect the gate electrode to the light shielding layer through the connected first via hole and the second via hole is specifically: forming a gate electrode on the gate insulating layer and Graphicizing to form a first sub-gate electrode and a second sub-gate electrode; wherein the first sub-gate electrode passes through the first through hole and the second through hole and the first sub-shield disposed corresponding to the first sub-shield layer
  • the second gate electrode is electrically connected to the second sub-shielding layer through the first via hole and the second via hole disposed corresponding to the second sub-shielding layer.
  • a liquid crystal display including a display panel and a backlight source.
  • the display panel includes an array substrate, and the array substrate includes a substrate and a light shielding layer sequentially formed on the substrate. a buffer layer, a semiconductor layer, a gate insulating layer, and a gate electrode; wherein a first via hole is disposed on the buffer layer, a second via hole is disposed on the gate insulating layer, and the gate electrode passes through the first via hole and the second via The through hole is electrically connected to the light shielding layer.
  • the light shielding layer includes a first sub-shield layer and a second sub-shield layer; the gate electrode includes a first sub-gate electrode and a second sub-gate electrode; the buffer layer respectively corresponds to the first sub-shield layer and the second layer
  • the sub-shield layer is provided with a first via hole
  • the gate insulating layer is respectively provided with a second via hole corresponding to the first sub-gate electrode and the second sub-gate electrode, respectively, so that the first sub-gate electrode passes through the corresponding and connected first A through hole and a second through hole are electrically connected to the first sub-shielding layer
  • the second sub-gate electrode is electrically connected to the second sub-shielding layer through the corresponding and communicating first through hole and the second through hole.
  • the first via hole and the second via hole are both formed by photolithography and etching processes.
  • the through hole is disposed in the gate terminal region or the pixel electrode region.
  • the array substrate further includes an interlayer insulating layer, a source/drain electrode, a passivation layer, an organic insulating layer, and a transparent electrode layer sequentially formed on the gate electrode; wherein the passivation layer is provided with a third through hole, organic A fourth via hole is disposed on the insulating layer, and the transparent electrode layer is electrically connected to the source/drain electrode through the third via hole and the fourth via hole.
  • the invention has the beneficial effects that the first through hole is disposed on the buffer layer, the second through hole is disposed on the gate insulating layer, and the gate electrode passes through the connected first through hole and is different from the prior art.
  • the second via is electrically connected to the light shielding layer to form a double gate.
  • the TFT structure of the present invention forms an inversion layer region between the double gates when the voltage is applied, which can enhance the current driving capability of the thin film transistor and improve the display quality.
  • FIG. 1 is a schematic structural view of a first embodiment of an array substrate of the present invention
  • FIG. 2 is a first schematic structural view of a second embodiment of the array substrate of the present invention.
  • FIG. 3 is a second schematic structural view of a second embodiment of the array substrate of the present invention.
  • FIG. 4 is a schematic flow chart of a first embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 5 is a schematic structural view of forming a through hole in the first embodiment of the method for fabricating the array substrate of the present invention
  • FIG. 6 is a schematic flow chart of a second embodiment of a method for fabricating an array substrate of the present invention.
  • Fig. 7 is a schematic structural view of an embodiment of a liquid crystal display of the present invention.
  • the array substrate includes a substrate 110 and a light shielding layer 120, a buffer layer 130, a semiconductor layer 140, a gate insulating layer 150, and a gate sequentially formed on the substrate 110. Electrode 160.
  • a first via hole 131 is disposed on the buffer layer 130, and a second via hole 151 is disposed on the gate insulating layer 150.
  • the gate electrode 160 is electrically connected to the light shielding layer 120 through the first through hole 131 and the second through hole 151.
  • the substrate 110 is generally a glass substrate or a plastic substrate, and other transparent materials may also be used.
  • the light shielding layer 120 and the gate electrode 160 are both metallic materials such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or a laminated structure thereof.
  • the buffer layer 130 is typically a silicon oxide (SiOx) or silicon nitride (SiNx) layer formed on the semiconductor layer 140 by chemical vapor deposition.
  • the semiconductor layer 140 is formed by forming an amorphous silicon layer on the buffer layer 130 by chemical vapor deposition, converting the amorphous silicon layer into a polysilicon layer by an annealing process, and forming a predetermined pattern on the polysilicon layer by a photomask process, thereby forming a pattern.
  • Semiconductor layer 140 is formed by forming an amorphous silicon layer on the buffer layer 130 by chemical vapor deposition, converting the amorphous silicon layer into a polysilicon layer by an annealing process, and forming a predetermined pattern on the polysilicon layer by a photomask process, thereby forming a pattern.
  • Semiconductor layer 140 is formed by forming an amorphous silicon layer on the buffer layer 130 by chemical vapor deposition, converting the amorphous silicon layer into a polysilicon layer by an annealing process, and forming a predetermined pattern on the polysilicon layer by a photomask process, thereby forming a pattern.
  • the gate insulating layer 150 is typically a silicon oxide (SiOx) or silicon nitride (SiNx) layer formed on the semiconductor layer 140 by chemical vapor deposition.
  • the first via hole 131 is disposed on the buffer layer 130, and the second via hole 151 is disposed on the gate insulating layer 150, which may be performed by a photolithography and etching process. Technology, no more details here.
  • the first via hole is disposed on the buffer layer, and the second via hole is disposed on the gate insulating layer, and the gate electrode is electrically connected to the light shielding layer through the first through hole and the second through hole Sexually connected to form a double gate.
  • the TFT structure of the present invention forms an inversion layer region between the double gates when the voltage is applied, which can enhance the current driving capability of the thin film transistor and improve the display quality.
  • the array substrate includes a substrate 210 and a light shielding layer 220, a buffer layer 230, a semiconductor layer 240, a gate insulating layer 250, and a gate sequentially formed on the substrate 210.
  • An electrode 260 ; wherein a first via hole (not labeled) is disposed on the buffer layer 230, a second via hole (not labeled) is disposed on the gate insulating layer 250, and the gate electrode 260 passes through the first through hole and the second pass The hole is electrically connected to the light shielding layer 220.
  • the light shielding layer 220 includes a first sub-shield layer 221 and a second sub-shield layer 222;
  • the gate electrode 260 includes a first sub-gate electrode 261 and a second sub-gate electrode 262;
  • the first sub-shielding layer 221 and the second sub-shielding layer 222 are provided with a first via hole, and the gate insulating layer 250 is respectively disposed with a second via hole corresponding to the first sub-gate electrode 261 and the second sub-gate electrode 262, so that
  • the first sub-gate electrode 261 is electrically connected to the first sub-shield layer 221 through the corresponding and connected first via holes and the second via holes, and the second sub-gate electrode 262 passes through the corresponding and connected first via holes.
  • the second via is electrically connected to the second sub-shielding layer 222.
  • the buffer layer 230 has two first via holes corresponding to the first sub-shielding layer 221 and the second sub-shielding layer 222 respectively, and the gate insulating layer 250 has two corresponding first sub-gate electrodes respectively.
  • a second via hole corresponding to the first sub-shield layer 221 and a second via hole corresponding to the first sub-gate electrode 261, corresponding to the second sub-shield The first via of the layer 222 and the second via corresponding to the second sub-gate electrode 262 are in communication.
  • the plurality of via holes should be disposed as far as possible from the patterned semiconductor layer 240, that is, the first semiconductor island 241 and the second semiconductor island 242.
  • the array substrate includes a substrate 301, and a light shielding layer 302, a buffer layer 303, a semiconductor layer 304, a gate insulating layer 305, a gate electrode 306, and a layer sequentially formed on the substrate 301.
  • a third via hole (not labeled) is disposed on the passivation layer 309, a fourth via hole is disposed on the organic insulating layer 310, and the transparent electrode layer 311 is electrically connected to the source/drain electrode 308 through the third via hole and the fourth via hole. connection.
  • the interlayer insulating layer 307 is typically a silicon oxide (SiOx) or silicon nitride (SiNx) layer formed on the gate electrode 306 by chemical vapor deposition.
  • the source/drain electrodes 308 are generally metallic materials such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or a stacked structure thereof.
  • the passivation layer 309 is typically made of an inorganic material or an inorganic material.
  • the organic insulating layer 310 is made of an organic material or an organic material, and mainly serves as an insulating layer.
  • the transparent electrode layer 311 is generally indium tin oxide (ITO), and may be other transparent materials such as indium gallium zinc oxide (IGZO).
  • ITO indium tin oxide
  • IGZO indium gallium zinc oxide
  • the transparent electrode layer 311 functions as an anode, and an organic light-emitting layer is disposed between the cathode and the cathode, that is, an electroluminescent diode is formed.
  • a schematic flowchart of a first embodiment of a method for fabricating an array substrate according to the present invention includes:
  • Step 401 sequentially forming a light shielding layer 520, a buffer layer 530, a semiconductor layer 540, and a gate insulating layer 550 on the substrate 510;
  • Step 402 forming a first via 531 on the buffer layer 530, and forming a second via 551 on the gate insulating layer 550 to partially expose the light shielding layer 520;
  • a photoresist is coated on the surface thereof, and after baking, ultraviolet irradiation is performed by the photomask, and the polymerization reaction in the exposed portion is not easily washed away by the etching solvent. The unexposed portions are washed away to form through holes.
  • Step 403 forming a gate electrode (not shown) on the gate insulating layer 550, so that the gate electrode is connected to the light shielding layer 520 through the connected first via hole 531 and the second via hole 551.
  • a schematic flowchart of a second embodiment of a method for fabricating an array substrate according to the present invention includes:
  • Step 601 depositing a light shielding layer on the substrate and patterning to form a first sub-light shielding layer and a second sub-light shielding layer;
  • the first sub-shield layer and the second sub-shield layer are independent of each other and are not electrically connected.
  • Step 602 forming a buffer layer on the first sub-light shielding layer and the second sub-light shielding layer;
  • the buffer layer is generally formed by chemical vapor deposition, physical sputtering or the like.
  • Step 603 depositing a semiconductor layer on the buffer layer and patterning to form first semiconductor islands and second semiconductor islands respectively corresponding to the first sub-shield layer and the second sub-shielding layer;
  • the first semiconductor island is an NPN-type semiconductor
  • the second semiconductor island is a PNP-type semiconductor, wherein the first semiconductor is a lightly doped semiconductor.
  • the first semiconductor island may be a PNP type semiconductor
  • the second semiconductor island may be an NPN type semiconductor.
  • Step 604 forming a gate insulating layer on the first semiconductor island and the second semiconductor island;
  • Step 605 A first via hole is disposed on the buffer layer corresponding to the first sub-shield layer and the second sub-shield layer, and a first sub-gate electrode and a second sub-gate electrode are respectively disposed on the gate insulating layer. a second through hole for exposing the first light shielding layer and the second light shielding layer;
  • Step 606 forming a gate electrode on the gate insulating layer and patterning to form a first sub-gate electrode and a second sub-gate electrode;
  • the first sub-gate electrode is electrically connected to the first sub-shield layer through the first via hole and the second via hole disposed corresponding to the first sub-shield layer, and the second word gate electrode is disposed through the corresponding second sub-shield layer.
  • the first through hole and the second through hole are electrically connected to the second sub-shielding layer.
  • the patterning process in the above steps can be completed by photolithography and etching processes, and will not be described again here.
  • a first via hole is disposed on the buffer layer of the gate insulating layer by a photolithography and etching process, and a second via hole is disposed on the gate insulating layer to pass the two gate electrodes respectively.
  • the connected first through holes and the second through holes are electrically connected to the corresponding light shielding layer to form a double gate.
  • the TFT structure of the present invention forms an inversion layer region between the double gates when the voltage is applied, which can enhance the current driving capability of the thin film transistor and improve the display quality.
  • FIG. 7 a schematic structural diagram of an embodiment of a liquid crystal display according to the present invention includes a panel and a backlight source.
  • the display panel 710 includes a color filter substrate 711, an array substrate 712, and a liquid crystal layer 713 between the color filter substrate 711 and the array substrate 712.
  • the array substrate 712 is an array substrate according to various embodiments, and details are not described herein. .

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Abstract

一种阵列基板及其制作方法、液晶显示器，该阵列基板包括基板（110）以及依次形成在基板（110）上的遮光层（120）、缓冲层（130）、半导体层（140）、栅极绝缘层（150）以及栅极电极（160）；其中，缓冲层（130）上设置第一通孔（131），栅极绝缘层（150）上设置第二通孔（151），栅极电极（160）通过连通的第一通孔（131）和第二通孔（151）与遮光层（120）电性连接。通过上述方式，能够增强薄膜晶体管的电流驱动能力，提高显示质量。

Description

一种阵列基板及其制作方法、液晶显示器
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种阵列基板及其制作方法、液晶显示器。
【背景技术】
有机发光二极管（Organic Light-Emitting Diode，OLED），又称为有机电激光显示（Organic Electroluminesence Display，OELD）。因为具备轻薄、省电等特性，这种显示设备得到了广泛应用，OLED屏幕具备了许多LCD不可比拟的优势。
目前，有机发光显示技术广泛应用在中小尺寸显示面板上。随着半导体制程技术的提升，显示器件的分辨率要求越来越高，相应的器件越来越小，对薄膜晶体管的特性要求也越来越高。
显示器件的高精细化和驱动电路的高速响应化要求TFT器件能快速的实现器件开关，但现有的TFT器件中的半导体层的电流驱动能力一般，难以适应显示器件的高精细化和驱动电路的高速响应化发展。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及其制作方法、液晶显示器，能够增强薄膜晶体管的电流驱动能力，提高显示质量。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，阵列基板包括基板以及依次形成在基板上的遮光层、缓冲层、半导体层、栅极绝缘层以及栅极电极；遮光层包括独立设置的第一子遮光层及第二子遮光层；栅极电极包括第一子栅极电极及第二子栅极电极；缓冲层分别对应第一子遮光层和第二子遮光层设置一第一通孔，栅极绝缘层分别对应第一子栅极电极和第二子栅极电极设置一第二通孔，使第一子栅极电极通过对应的且连通的第一通孔和第二通孔与第一子遮光层电性连接，第二子栅极电极通过对应的且连通的第一通孔和第二通孔与第二子遮光层电性连接；其中，第一通孔和第二通孔均采用光刻和刻蚀工艺形成的。
其中，通孔设置于栅极端子区域或者像素电极区域。
其中，阵列基板还包括依次形成在栅极电极上的层间绝缘层、源/漏电极、钝化层、有机绝缘层以及透明电极层；其中，钝化层上设置有第三通孔，有机绝缘层上设置有第四通孔，透明电极层通过第三通孔及第四通孔与源/漏电极电性连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制造方法，方法包括：在基板上依次形成遮光层、缓冲层、半导体层以及栅极绝缘层；在缓冲层上形成第一通孔，以及在栅极绝缘层上形成第二通孔，以使遮光层部分裸露；在栅极绝缘层上形成栅极电极，以使栅极电极通过连通的第一通孔和第二通孔与遮光层连接。
其中，步骤在基板上依次形成遮光层、缓冲层、半导体层以及栅极绝缘层具体为：在基板上沉积遮光层并图形化，以形成第一子遮光层及第二子遮光层；在第一子遮光层及第二子遮光层上形成缓冲层；在缓冲层上沉积半导体层并图形化，以形成分别对应第一子遮光层及第二子遮光层的第一半导体小岛及第二半导体小岛；在第一半导体小岛及第二半导体小岛上形成栅极绝缘层。
其中，在缓冲层上形成第一通孔，以及在栅极绝缘层上形成第二通孔，以使遮光层部分裸露的步骤具体为：在缓冲层上分别对应第一子遮光层和第二子遮光层设置一第一通孔，在栅极绝缘层上分别对应第一子栅极电极和第二子栅极电极设置一第二通孔，以使第一遮光层及第二遮光层部分裸露。
其中，在栅极绝缘层上形成栅极电极，以使栅极电极通过连通的第一通孔和第二通孔与遮光层连接的步骤具体为：在栅极绝缘层上形成栅极电极并图形化，以形成第一子栅极电极及第二子栅极电极；其中，第一子栅极电极通过对应第一子遮光层设置的第一通孔及第二通孔与第一子遮光层电性连接，第二字栅极电极通过对应第二子遮光层设置的第一通孔及第二通孔与第二子遮光层电性连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示器，包括显示面板和背光光源，显示面板包括一阵列基板；阵列基板包括基板以及依次形成在基板上的遮光层、缓冲层、半导体层、栅极绝缘层以及栅极电极；其中，缓冲层上设置第一通孔，栅极绝缘层上设置第二通孔，栅极电极通过连通的第一通孔和第二通孔与遮光层电性连接。
其中，遮光层包括独立设置的第一子遮光层及第二子遮光层；栅极电极包括第一子栅极电极及第二子栅极电极；缓冲层分别对应第一子遮光层和第二子遮光层设置一第一通孔，栅极绝缘层分别对应第一子栅极电极和第二子栅极电极设置一第二通孔，使第一子栅极电极通过对应的且连通的第一通孔和第二通孔与第一子遮光层电性连接，第二子栅极电极通过对应的且连通的第一通孔和第二通孔与第二子遮光层电性连接。
其中，第一通孔和第二通孔均采用光刻和刻蚀工艺形成的。
其中，通孔设置于栅极端子区域或者像素电极区域。
其中，阵列基板还包括依次形成在栅极电极上的层间绝缘层、源/漏电极、钝化层、有机绝缘层以及透明电极层；其中，钝化层上设置有第三通孔，有机绝缘层上设置有第四通孔，透明电极层通过第三通孔及第四通孔与源/漏电极电性连接。
本发明的有益效果是：区别于现有技术的情况，本发明通过缓冲层上设置第一通孔，在栅极绝缘层上设置第二通孔，栅极电极通过连通的第一通孔和第二通孔与遮光层电性连接，以形成双栅极。通过上述方式，本发明的TFT结构在通入电压时，在双栅极之间形成反转层区域，能够增强薄膜晶体管的电流驱动能力，提高显示质量。
【附图说明】
图1是本发明阵列基板第一实施方式的结构示意图；
图2是本发明阵列基板第二实施方式的第一结构示意图；
图3是本发明阵列基板第二实施方式的第二结构示意图；
图4是本发明阵列基板的制作方法第一实施方式的流程示意图；
图5是本发明阵列基板的制作方法第一实施方式中形成通孔的结构示意图；
图6是本发明阵列基板的制作方法第二实施方式的流程示意图；
图7是本发明液晶显示器一实施方式的结构示意图。
【具体实施方式】
参阅图1，本发明阵列基板第一实施方式的结构示意图，该阵列基板包括基板110以及依次形成在基板110上的遮光层120、缓冲层130、半导体层140、栅极绝缘层150以及栅极电极160。
缓冲层130上设置第一通孔131，栅极绝缘层150上设置第二通孔151，栅极电极160通过连通的第一通孔131和第二通孔151与遮光层120电性连接。
其中，基板110一般是玻璃基板或塑料基板，也可以采用其他透明材料。
遮光层120和栅极电极160均为金属材料，例如铜（Cu）、铝（Al）、钼（Mo）、钛(Ti)或其层叠结构。
缓冲层130一般是氧化硅（SiOx）或氮化硅（SiNx）层，其通过化学气相沉积形成于半导体层140上。
半导体层140是通过化学气相沉积在缓冲层130上形成非晶硅层，并通过退火工艺将该非晶硅层转化为多晶硅层，并通过光罩制程在该多晶硅层上形成预定图案，进而形成半导体层140。
栅极绝缘层150一般是氧化硅（SiOx）或氮化硅（SiNx）层，其通过化学气相沉积形成于半导体层140上。
在本实施方式中，在缓冲层130上设置第一通孔131，以及在栅极绝缘层150上设置第二通孔151，均可以采用光刻和刻蚀的工艺进行，该工艺属于现有技术，这里不再赘述。
区别于现有技术，本实施方式通过缓冲层上设置第一通孔，在栅极绝缘层上设置第二通孔，栅极电极通过连通的第一通孔和第二通孔与遮光层电性连接，以形成双栅极。通过上述方式，本发明的TFT结构在通入电压时，在双栅极之间形成反转层区域，能够增强薄膜晶体管的电流驱动能力，提高显示质量。
参阅图2，本发明阵列基板第二实施方式的结构示意图，该阵列基板包括基板210以及依次形成在基板210上的遮光层220、缓冲层230、半导体层240、栅极绝缘层250以及栅极电极260；其中，缓冲层230上设置第一通孔（未标示），栅极绝缘层250上设置第二通孔（未标示），栅极电极260通过连通的第一通孔和第二通孔与遮光层220电性连接。
具体地，遮光层220包括独立设置的第一子遮光层221及第二子遮光层222；栅极电极260包括第一子栅极电极261及第二子栅极电极262；缓冲层230分别对应第一子遮光层221和第二子遮光层222设置一第一通孔，栅极绝缘层250分别对应第一子栅极电极261和第二子栅极电极262设置一第二通孔，使第一子栅极电极261通过对应的且连通的第一通孔和第二通孔与第一子遮光层221电性连接，第二子栅极电极262通过对应的且连通的第一通孔和第二通孔与第二子遮光层222电性连接。
也就是说，缓冲层230上有两个分别对应于第一子遮光层221和第二子遮光层222的第一通孔，栅极绝缘层250上有两个分别对应第一子栅极电极261和第二子栅极电极262的第二通孔，其中，对应第一子遮光层221的第一通孔和对应第一子栅极电极261的第二通孔连通，对应第二子遮光层222的第一通孔和对应第二子栅极电极262的第二通孔连通。
另外，该多个通孔的设置应当尽量远离图形化后的半导体层240，即第一半导体小岛241和第二半导体小岛242。
如图3所示，在本实施方式中，该阵列基板包括基板301以及依次形成在基板301上的遮光层302、缓冲层303、半导体层304、栅极绝缘层305、栅极电极306、层间绝缘层307、源/漏电极308、钝化层309、有机绝缘层310以及透明电极层311。
钝化层309上设置有第三通孔（未标示），有机绝缘层310上设置有第四通孔，透明电极层311通过第三通孔及第四通孔与源/漏电极308电性连接。
其中，层间绝缘层307一般是氧化硅（SiOx）或氮化硅（SiNx）层，其通过化学气相沉积形成于栅极电极306上。
源/漏电极308一般为金属材料，例如铜（Cu）、铝（Al）、钼（Mo）、钛(Ti)或其层叠结构。
钝化层309一般为无机材料或偏无机的材料制成。
有机绝缘层310有有机材料或偏有机的材料制成，主要起到绝缘作用。
透明电极层311一般为氧化铟锡（ITO），也可以是铟镓锌氧化物（IGZO）等其他透明材料。
在具体的实施过程中，透明电极层311作为阳极，与阴极之间设置有机发光层，即形成电致发光二极管。
参阅图4，本发明阵列基板的制作方法第一实施方式的流程示意图，该方法包括：
步骤401：在基板510上依次形成遮光层520、缓冲层530、半导体层540以及栅极绝缘层550；
步骤402：在缓冲层530上形成第一通孔531，以及在栅极绝缘层550上形成第二通孔551，以使遮光层520部分裸露；
如图5所示，在形成栅极绝缘层550后，在其表面涂覆一层光刻胶，烘烤后利用光罩紫外照射，曝光部分产生聚合反应不易被刻蚀溶剂中洗去，而未被曝光部分则会被洗去以形成通孔。
步骤403：在栅极绝缘层550上形成栅极电极（图未示），以使栅极电极通过连通的第一通孔531和第二通孔551与遮光层520连接。
参阅图6，本发明阵列基板的制作方法第二实施方式的流程示意图，该方法包括：
步骤601：在基板上沉积遮光层并图形化，以形成第一子遮光层及第二子遮光层；
其中，第一子遮光层及第二子遮光层各自独立，无电性连接。
步骤602：在第一子遮光层及第二子遮光层上形成缓冲层；
缓冲层一般采用化学气相沉积、物理溅射等方式形成。
步骤603：在缓冲层上沉积半导体层并图形化，以形成分别对应第一子遮光层及第二子遮光层的第一半导体小岛及第二半导体小岛；
在一种实施方式中，第一半导体小岛为NPN型半导体，第二半导体小岛为PNP型半导体，其中，第一半导体为轻掺杂型半导体。当然，在其他实施方式中，也可以是第一半导体小岛为PNP型半导体，第二半导体小岛为NPN型半导体。
步骤604：在第一半导体小岛及第二半导体小岛上形成栅极绝缘层；
步骤605：在缓冲层上分别对应第一子遮光层和第二子遮光层设置一第一通孔，在栅极绝缘层上分别对应第一子栅极电极和第二子栅极电极设置一第二通孔，以使第一遮光层及第二遮光层部分裸露；
该过程与前述实施方式相同，这里不再赘述。
步骤606：在栅极绝缘层上形成栅极电极并图形化，以形成第一子栅极电极及第二子栅极电极；
其中，第一子栅极电极通过对应第一子遮光层设置的第一通孔及第二通孔与第一子遮光层电性连接，第二字栅极电极通过对应第二子遮光层设置的第一通孔及第二通孔与第二子遮光层电性连接。
以上步骤中的图形化过程，均可以采用光刻和刻蚀的工艺来完成，这里不再赘述。
区别于现有技术，本实施方式通过光刻和刻蚀工艺在栅极绝缘层缓冲层上设置第一通孔，在栅极绝缘层上设置第二通孔，使两个栅极电极分别通过连通的第一通孔和第二通孔与对应的遮光层电性连接，以形成双栅极。通过上述方式，本发明的TFT结构在通入电压时，在双栅极之间形成反转层区域，能够增强薄膜晶体管的电流驱动能力，提高显示质量。
参阅图7，本发明液晶显示器一实施方式的结构示意图，该液晶显示器包括面板和背光光源。
其中，显示面板710包括彩膜基板711、阵列基板712以及该彩膜基板711和阵列基板712之间的液晶层713；该阵列基板712是如上各个实施方式所述的阵列基板，这里不再赘述。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种阵列基板，其特征在于，所述阵列基板包括基板以及依次形成在所述基板上的遮光层、缓冲层、半导体层、栅极绝缘层以及栅极电极；
    所述遮光层包括独立设置的第一子遮光层及第二子遮光层；
    所述栅极电极包括第一子栅极电极及第二子栅极电极；
    所述缓冲层分别对应所述第一子遮光层和所述第二子遮光层设置一所述第一通孔，所述栅极绝缘层分别对应所述第一子栅极电极和所述第二子栅极电极设置一所述第二通孔，使所述第一子栅极电极通过对应的且连通的所述第一通孔和所述第二通孔与所述第一子遮光层电性连接，所述第二子栅极电极通过对应的且连通的所述第一通孔和所述第二通孔与所述第二子遮光层电性连接；
    其中，所述第一通孔和所述第二通孔均采用光刻和刻蚀工艺形成的。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述通孔设置于栅极端子区域或者像素电极区域。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括依次形成在所述栅极电极上的层间绝缘层、源/漏电极、钝化层、有机绝缘层以及透明电极层；
    其中，所述钝化层上设置有第三通孔，所述有机绝缘层上设置有第四通孔，所述透明电极层通过所述第三通孔及所述第四通孔与所述源/漏电极电性连接。
  4. 一种阵列基板的制造方法，其特征在于，所述方法包括：
    在基板上依次形成遮光层、缓冲层、半导体层以及栅极绝缘层；
    在所述缓冲层上形成第一通孔，以及在所述栅极绝缘层上形成第二通孔，以使所述遮光层部分裸露；
    在所述栅极绝缘层上形成栅极电极，以使所述栅极电极通过连通的所述第一通孔和所述第二通孔与所述遮光层连接。
  5. 根据权利要求4所述的方法，其特征在于，所述步骤在基板上依次形成遮光层、缓冲层、半导体层以及栅极绝缘层具体为：
    在基板上沉积遮光层并图形化，以形成第一子遮光层及第二子遮光层；
    在所述第一子遮光层及第二子遮光层上形成缓冲层；
    在所述缓冲层上沉积半导体层并图形化，以形成分别对应所述第一子遮光层及第二子遮光层的第一半导体小岛及第二半导体小岛；
    在所述第一半导体小岛及第二半导体小岛上形成栅极绝缘层。
  6. 根据权利要求5所述的方法，其特征在于，在所述缓冲层上形成第一通孔，以及在所述栅极绝缘层上形成第二通孔，以使所述遮光层部分裸露的步骤具体为：
    在所述缓冲层上分别对应所述第一子遮光层和所述第二子遮光层设置一所述第一通孔，在所述栅极绝缘层上分别对应所述第一子栅极电极和所述第二子栅极电极设置一所述第二通孔，以使所述第一遮光层及所述第二遮光层部分裸露。
  7. 根据权利要求6所述的方法，其特征在于，在所述栅极绝缘层上形成栅极电极，以使所述栅极电极通过连通的所述第一通孔和所述第二通孔与所述遮光层连接的步骤具体为：
    在所述栅极绝缘层上形成栅极电极并图形化，以形成第一子栅极电极及第二子栅极电极；
    其中，所述第一子栅极电极通过对应所述第一子遮光层设置的所述第一通孔及所述第二通孔与所述第一子遮光层电性连接，所述第二字栅极电极通过对应所述第二子遮光层设置的所述第一通孔及所述第二通孔与所述第二子遮光层电性连接。
  8. 一种液晶显示器，包括显示面板和背光光源，其特征在于，所述显示面板包括一阵列基板；
    所述阵列基板包括基板以及依次形成在所述基板上的遮光层、缓冲层、半导体层、栅极绝缘层以及栅极电极；
    其中，所述缓冲层上设置第一通孔，所述栅极绝缘层上设置第二通孔，所述栅极电极通过连通的所述第一通孔和所述第二通孔与所述遮光层电性连接。
  9. 根据权利要求8所述的液晶显示器，其特征在于，所述遮光层包括独立设置的第一子遮光层及第二子遮光层；
    所述栅极电极包括第一子栅极电极及第二子栅极电极；
    所述缓冲层分别对应所述第一子遮光层和所述第二子遮光层设置一所述第一通孔，所述栅极绝缘层分别对应所述第一子栅极电极和所述第二子栅极电极设置一所述第二通孔，使所述第一子栅极电极通过对应的且连通的所述第一通孔和所述第二通孔与所述第一子遮光层电性连接，所述第二子栅极电极通过对应的且连通的所述第一通孔和所述第二通孔与所述第二子遮光层电性连接。
  10. 根据权利要求8所述的液晶显示器，其特征在于，所述第一通孔和所述第二通孔均采用光刻和刻蚀工艺形成的。
  11. 根据权利要求8所述的液晶显示器，其特征在于，所述通孔设置于栅极端子区域或者像素电极区域。
  12. 根据权利要求8所述的液晶显示器，其特征在于，所述阵列基板还包括依次形成在所述栅极电极上的层间绝缘层、源/漏电极、钝化层、有机绝缘层以及透明电极层；
    其中，所述钝化层上设置有第三通孔，所述有机绝缘层上设置有第四通孔，所述透明电极层通过所述第三通孔及所述第四通孔与所述源/漏电极电性连接。
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