WO2017054191A1 - 一种tft阵列基板及其制作方法 - Google Patents

一种tft阵列基板及其制作方法 Download PDF

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Publication number
WO2017054191A1
WO2017054191A1 PCT/CN2015/091284 CN2015091284W WO2017054191A1 WO 2017054191 A1 WO2017054191 A1 WO 2017054191A1 CN 2015091284 W CN2015091284 W CN 2015091284W WO 2017054191 A1 WO2017054191 A1 WO 2017054191A1
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Prior art keywords
pattern
layer
substrate
semiconductor
photoresist
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PCT/CN2015/091284
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English (en)
French (fr)
Inventor
葛世民
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深圳市华星光电技术有限公司
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Priority to US14/786,110 priority Critical patent/US20170255044A1/en
Publication of WO2017054191A1 publication Critical patent/WO2017054191A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
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    • G02F2202/00—Materials and properties
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate and a method of fabricating the same.
  • the active matrix driven LCD display technology utilizes the bipolar polarization characteristics of the liquid crystal, and controls the alignment direction of the liquid crystal molecules by applying an electric field, thereby realizing the switching effect on the traveling direction of the backlight optical path.
  • the LCD display mode can be divided into TN.
  • VA and IPS series mode refers to applying a longitudinal electric field to liquid crystal molecules
  • the IPS series mode refers to applying a transverse electric field to liquid crystal molecules.
  • the IPS series mode for the application of the transverse electric field, it can be divided into the IPS mode and the FFS mode.
  • Each pixel unit of the FFS display mode includes two upper and lower electrodes, that is, a pixel electrode and a common electrode, and the common electrode of the lower layer is flattened on the entire surface of the open area.
  • the FFS display mode has a high transmittance, wide viewing angle and low color shift, and is a widely used LCD display technology.
  • a Single-gate TFT (single-gate thin film transistor) is often used, but a Dual gate TFT (Double Gate Transistor) and Single-gate Compared with TFT (single-gate thin film transistor), it has not only high mobility, large on-state current, smaller subthreshold swing, threshold voltage (Vth) stability and uniformity, but also Better gate bias stability.
  • the traditional FFS display mode Dual-Gate The TFT array substrate manufacturing method requires more mask times, which increases the complexity of the process and the production cost.
  • the present invention provides a TFT array substrate and a method of fabricating the same, which can reduce the number of masks, improve production efficiency, and reduce production costs.
  • the present invention provides a method for fabricating a TFT array substrate, including:
  • first metal oxide semiconductor layer Forming a first metal oxide semiconductor layer on the substrate, and etching the first metal oxide semiconductor layer into the first semiconductor pattern and the second semiconductor pattern by a second mask process, and performing doping treatment to remove the first semiconductor
  • the two ends of the pattern are respectively processed into the first conductor pattern and the second conductor pattern which are disposed at intervals and the second semiconductor pattern is processed into a third conductor pattern, wherein the first semiconductor pattern remaining after the processing is located above the bottom gate electrode, a three-conductor pattern as a common electrode,
  • a photoresist pattern is formed on the metal oxide semiconductor layer, the photoresist pattern includes a first photoresist pattern corresponding to the first semiconductor pattern and a second photoresist pattern corresponding to the second semiconductor pattern, the first photoresist pattern
  • the photoresist thickness of the intermediate portion is greater than the photoresist thickness at both ends of the first photoresist pattern and greater than the photoresist thickness of the second photoresist pattern.
  • the substrate Forming a second metal oxide conductor layer on the substrate, and etching the second metal oxide conductor layer into a top gate electrode and a pixel electrode by using a fifth mask process, wherein the top gate electrode is located at the first semiconductor remaining after the process Above the pattern, the pixel electrode and the common electrode are at least partially overlapped and electrically connected to one of the source electrode and the drain electrode through the via.
  • the metal oxide semiconductor layer is an IGZO oxide semiconductor layer.
  • the second photomask process forms a photoresist pattern by using any one of a halftone mask, a gray tone mask or a single slit mask.
  • the material of the etch barrier layer is silicon oxide.
  • the invention also provides a method for fabricating a TFT array substrate, comprising:
  • the two ends of the pattern are respectively processed into the first conductor pattern and the second conductor pattern which are disposed at intervals and the second semiconductor pattern is processed into a third conductor pattern, wherein the first semiconductor pattern remaining after the processing is located above the bottom gate electrode, a three-conductor pattern as a common electrode;
  • the substrate Forming a second metal oxide conductor layer on the substrate, and etching the second metal oxide conductor layer into a top gate electrode and a pixel electrode by using a fifth mask process, wherein the top gate electrode is located at the first semiconductor remaining after the process Above the pattern, the pixel electrode and the common electrode are at least partially overlapped and electrically connected to one of the source electrode and the drain electrode through the via.
  • the metal oxide semiconductor layer is an IGZO oxide semiconductor layer.
  • the step of further forming a metal oxide semiconductor layer on the substrate, and performing the doping treatment after etching the metal oxide semiconductor layer into the first semiconductor pattern and the second semiconductor pattern by using the second mask process comprises:
  • the photoresist pattern includes a first photoresist pattern corresponding to the first semiconductor pattern and a second photoresist pattern corresponding to the second semiconductor pattern, in the middle of the first photoresist pattern
  • the photoresist thickness of the region is greater than the photoresist thickness at both ends of the first photoresist pattern and greater than the photoresist thickness of the second photoresist pattern;
  • the second photomask process forms a photoresist pattern by using any one of a halftone mask, a gray tone mask or a single slit mask.
  • the metal oxide semiconductor layer is further formed on the substrate, and the step of performing the doping treatment after the metal oxide semiconductor layer is etched into the first semiconductor pattern and the second semiconductor pattern by the second mask process and further forming on the substrate a second metal layer, and a step of etching the second metal layer into a source electrode and a drain electrode by using a third mask process, the method further comprises:
  • An etch stop layer is further formed on the substrate, and the etch stop layer is etched by a sixth mask process to form etch stop vias respectively over the first conductor pattern and the second conductor pattern.
  • the material of the etch barrier layer is silicon oxide.
  • an array substrate provided by the present invention includes: a substrate; a bottom gate electrode formed on the substrate; a semiconductor pattern formed on the substrate; a first conductor pattern disposed at two ends of the semiconductor pattern and spaced apart The two conductor pattern and the common electrode, wherein the semiconductor pattern, the first conductor pattern, the second conductor pattern, and the common electrode are formed of the same metal oxide semiconductor layer.
  • the metal oxide semiconductor layer is an IGZO oxide semiconductor layer.
  • the array substrate further includes a drain electrode above the first conductor pattern and a source electrode above the second conductor pattern.
  • the array substrate further includes an etch barrier layer, and via holes corresponding to the first conductor pattern and the second conductor pattern are respectively formed on the etch barrier layer, and the drain electrode and the source electrode are electrically connected to the semiconductor pattern through the via holes.
  • the beneficial effects of the present invention are: different from the prior art, the first metal oxide semiconductor layer is etched into the first semiconductor pattern and the second semiconductor pattern by the same photomask process, and then doped. And processing the two ends of the first semiconductor pattern into the first conductor pattern and the second conductor pattern which are disposed at intervals and processing the second semiconductor pattern into a common electrode, and the first semiconductor pattern remaining after the processing is located above the bottom gate electrode, Therefore, the manufacture of the TFT array substrate of the present invention can reduce the number of times of the mask, improve production efficiency, and reduce production cost.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate of the present invention
  • 2A to 2G are process flow diagrams of preparing a bottom gate electrode, a common electrode, a first conductor pattern, and a second conductor pattern in the first embodiment of the TFT array substrate of FIG. 1;
  • FIG. 3 is a schematic view showing a process of forming a source electrode and a drain electrode by a third photomask process of the TFT array substrate of FIG. 1;
  • FIG. 4 is a schematic view showing a process of forming a via hole in a fourth photomask process of the TFT array substrate of FIG. 1;
  • FIG. 5 is a schematic structural view of a TFT array substrate obtained by the first embodiment of the method for fabricating the TFT array substrate of FIG. 1;
  • FIG. 6 is a schematic flow chart of a second embodiment of a method for fabricating a TFT array substrate of the present invention.
  • FIG. 7 is a schematic structural view of a TFT array substrate obtained by the second embodiment of the method for fabricating the TFT array substrate of FIG. 6.
  • FIG. 7 is a schematic structural view of a TFT array substrate obtained by the second embodiment of the method for fabricating the TFT array substrate of FIG. 6.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate according to the present invention. As shown in FIG. 1 , a method for fabricating a TFT array substrate of the present embodiment includes:
  • FIG. 2A is a schematic structural view of a bottom gate electrode prepared in the first embodiment of the TFT array substrate of FIG. 1.
  • the substrate 100 serves as a substrate substrate, which may be a glass substrate, a plastic substrate or a substrate of another suitable material.
  • the substrate 100 is preferably a glass substrate having a light transmitting property.
  • a first metal layer (not shown) is deposited on the substrate 100 by physical vapor deposition (PVD), and the material of the first metal layer includes, but is not limited to, chromium, aluminum, titanium or other metal materials.
  • PVD physical vapor deposition
  • FIG. 2A Shown in FIG. 2A is a schematic structural view of the bottom gate electrode 11 which is obtained by exposing the first metal layer to the first mask.
  • S13 further forming a first metal oxide semiconductor layer on the substrate, and performing a doping process after etching the first metal oxide semiconductor layer into the first semiconductor pattern and the second semiconductor pattern by using a second mask process.
  • a substrate insulating layer 110 is first covered on the substrate 100, and a first metal oxide semiconductor layer 120 is further formed by PVD deposition on the gate insulating layer 110.
  • the gate insulating layer 110 covers the bottom gate electrode 11 and extends onto the substrate 100.
  • the gate insulating layer 110 can be formed by chemical vapor deposition.
  • the material of the gate insulating layer 110 includes but is not limited to silicon nitride, silicon oxide or nitrogen. Silicon oxide.
  • the material of the first metal oxide semiconductor layer 120 is preferably IGZO (Indium Gallium Zinc Oxide), an amorphous metal oxide containing indium, gallium and zinc, is a channel layer material used in next-generation thin film transistor technology.
  • the carrier mobility of IGZO is 20 to 30 times that of amorphous silicon. It can greatly improve the charging and discharging rate of the TFT to the pixel electrode, improve the response speed of the pixel, achieve a faster refresh rate, and at the same time, the faster response also greatly improves the line scanning rate of the pixel, so that the ultra-high resolution is in the TFT-LCD.
  • IGZO displays have higher energy efficiency levels and higher efficiency due to the reduction in the number of transistors and the improvement of the transmittance of each pixel.
  • IGZO can be produced using existing amorphous silicon production lines. With minor modifications, IGZO is more competitive than low-temperature polysilicon in terms of cost.
  • the first metal oxide semiconductor layer 120 is further covered with a photoresist layer (not shown), and the photoresist layer is exposed and developed by the second mask 20.
  • the second mask 20 is a halftone mask (Halt-tone) Mask; referred to as HTM), Gray-tone Mask (GTM) or Single Slit Mask (Single slit) Mask; SSM for short.
  • the second photomask 20 includes a light transmitting portion 201, a semi-transmissive portion 202, and an opaque portion 203. After the substrate 100 having the first metal oxide conductor layer 120 is exposed by the second mask 20, the photoresist layer is completely exposed corresponding to the region of the light transmitting portion 201 of the second mask 20, corresponding to the half of the second mask 20.
  • the area of the light transmitting portion 202 is half-exposed, and the area corresponding to the opaque portion 203 of the second mask 20 is not exposed. Therefore, the first photoresist pattern 2030 and the second photoresist pattern 2020 are respectively obtained after the exposure, half exposure, non-exposure, and development processes of the photoresist layer by the second mask 20, wherein the first photoresist pattern 2030 includes The first photoresist portion 2031 and the second photoresist portion 2032, the second photoresist pattern 2020 includes a second photoresist portion 2032. The thickness of the first photoresist portion 2031 is greater than the second photoresist portion 2032. The first photoresist pattern 2030 is formed.
  • the middle is the first photoresist portion 2031, and both ends of the first photoresist portion 2031 are photoresist patterns of the second photoresist portion 2032.
  • the first photoresist portion 2031 corresponds to the opaque portion 203 of the second reticle 20
  • the second photoresist portion 2032 corresponds to the semi-transmissive portion 202 of the second reticle 20 .
  • the region not covered by the photoresist portion is further subjected to wet etching removal.
  • the first metal oxide conductor layer not covered by the first photoresist pattern 2030 and the second photoresist pattern 2020 is removed. 120 corresponding area. Therefore, after the first metal oxide conductor layer 120 passes through the exposure development and etching process of the second mask 20, the second semiconductor pattern 122 under the second photoresist pattern 2020 and the under the first photoresist pattern 2030 are formed.
  • the first semiconductor pattern 121 is formed.
  • the first photoresist portion 2031 and the second photoresist portion 2032 are ashed using oxygen so that the second photoresist portion 2032 having a thin thickness is removed, thereby being covered by the second photoresist portion 2032.
  • a corresponding region of the first metal oxide conductor layer 120 is exposed.
  • the first photoresist portion 2031 retains a portion of the photoresist.
  • the second semiconductor pattern 122 located under the second photoresist pattern 2020 is exposed, and both ends of the first semiconductor pattern 121 under the first photoresist pattern 2030 are also exposed.
  • the first metal oxide conductor layer 120 which is not covered by the photoresist, is processed into a corresponding conductor, and the first metal oxide conductor layer 120 covered by the photoresist is still a conductor.
  • the IGZO semiconductor is passed through Plasma.
  • the treatment method is processed into a corresponding IGZO conductor.
  • the second semiconductor pattern 122 is by Plasma
  • the treatment is processed into the corresponding third conductor pattern 14, and both ends of the first semiconductor pattern 121 are processed by Plasma
  • the treatment is processed into the corresponding first conductor pattern 12 and second conductor pattern 13, and the first conductor pattern 12 and the second conductor pattern 13 are spaced apart. And part of the first metal oxide conductor layer 120 covered by the remaining photoresist portion is not Plasma Treatmen treatment.
  • the remaining photoresist of the first photoresist portion 2031 is peeled off, so that the first metal oxide conductor layer 120 of the photoresist-covered portion remaining by the first photoresist portion 2031 is retained as the semiconductor pattern 15. Therefore, both ends of the semiconductor pattern 15 are the first conductor pattern 12 and the second conductor pattern 13, respectively, the semiconductor pattern 15 corresponds to the upper side of the bottom gate electrode 11, and the third conductor pattern 14 serves as the common electrode 14 of the array substrate.
  • S14 further forming a second metal layer on the substrate, and etching the second metal layer into a source electrode and a drain electrode by using a third mask process.
  • a second metal layer (not shown) is further formed on the substrate 100, and a photoresist layer (not shown) is over the second metal layer, and a third photomask is used.
  • the drain electrode 17 above the first conductor pattern 12 and the source electrode 16 above the second conductor pattern 13 are formed, wherein
  • the process of fabricating the source electrode 16 and the drain electrode 17 by the three masks is a prior art process, and will not be described in detail herein.
  • S15 further forming a first passivation layer on the substrate, and etching the first passivation layer by using a fourth mask process to form via holes.
  • a first passivation layer 130 is further formed on the substrate 100.
  • the first passivation layer 130 covers the source electrode 16 and the drain electrode 17, and the common electrode 14 and extends onto the gate insulating layer 110.
  • the region corresponding to the first passivation layer 130 above the source electrode 16 or the drain electrode 17 is formed.
  • Hole 18 the method of forming the via holes 18 adopts the prior art method, and will not be described in detail herein.
  • S16 further forming a second metal oxide conductor layer on the substrate, and etching the second metal oxide conductor layer into a top gate electrode and a pixel electrode by using a fifth mask process.
  • FIG. 5 is a schematic structural view of a TFT array substrate obtained by the first embodiment of the method for fabricating the TFT array substrate of FIG. 1, and the embodiment of steps S16 to S17 is described with reference to FIG. 5.
  • a second transparent metal oxide conductor layer (not shown) is further formed on the first passivation layer 130 of the substrate 100.
  • the material of the second transparent metal oxide conductor layer includes but is not limited to ITO (English: Indium) Tin oxide, Chinese: indium tin oxide, ITO is a metal oxide with good electrical conductivity and transparency.
  • the second metal oxide conductor layer is exposed by a fifth mask (not shown) and developed and etched to form a top gate electrode 19 and a plurality of pixel electrodes 20.
  • the top gate electrode 19 is disposed corresponding to the bottom gate electrode 11.
  • the pixel electrode 20 and the common electrode 14 are at least partially overlapped, and one of the pixel electrodes 20 is electrically connected to one of the source electrode 16 and the drain electrode 17 through the via hole 18.
  • one pixel electrode 20 is connected to the source electrode 16 through the via hole 18, and the remaining pixel electrodes 20 are spaced apart above the common electrode 14.
  • a second passivation layer 140 on the substrate 100, the second passivation layer 140 covering the pixel electrode 20, the top gate electrode 19 and extending to the first passivation layer 130
  • the metal oxide TFT array substrate 1 of the present embodiment is BCE (English: Back Channel Etch, Chinese: Array substrate of back channel etch structure) structure.
  • the oxide TFT array substrate of the present embodiment is doped by etching the first metal oxide semiconductor layer into the first semiconductor pattern and the second semiconductor pattern by the same mask process to remove the first semiconductor pattern.
  • the terminals are respectively processed into the first conductor pattern and the second conductor pattern which are disposed at intervals and the second semiconductor pattern is processed into a common electrode, and the remaining first semiconductor pattern is disposed above the bottom gate electrode, so that the process of the array substrate can be reduced.
  • the number of masks increases productivity and reduces production costs.
  • FIG. 6 is a schematic flow chart of a second embodiment of a method for fabricating a TFT array substrate according to the present invention. As shown in FIG. 6, the manufacturing method of the TFT array substrate of this embodiment includes:
  • S23 further forming a first metal oxide semiconductor layer on the substrate, and performing a doping treatment after etching the first metal oxide semiconductor layer into the first semiconductor pattern and the second semiconductor pattern by using a second mask process.
  • S24 further forming an etch barrier layer on the substrate, and etching the etch barrier layer by a sixth mask process to form etch barrier via holes respectively located above the first conductor pattern and the second conductor pattern.
  • S25 further forming a second metal layer on the substrate, and etching the second metal layer into a source electrode and a drain electrode by using a third mask process.
  • S26 further forming a first passivation layer on the substrate, and etching the first passivation layer by using a fourth mask process to form via holes.
  • S27 further forming a second metal oxide conductor layer on the substrate, and etching the second metal oxide conductor layer into a top gate electrode and a pixel electrode by using a fifth mask process.
  • the difference between the present embodiment and the above embodiment is that the first semiconductor pattern 121 and the second semiconductor pattern are etched by using the second mask as shown in FIG. 2A to FIG. 2G. 122, after doping to form the first conductor pattern 12, the second conductor pattern 13, the common electrode 14 and the semiconductor pattern 15, the embodiment further forms an etch stop layer 150 on the substrate 100, as shown in FIG.
  • FIG. 7 is a schematic structural view of a TFL array substrate formed in the embodiment of FIG. 6.
  • the etch barrier layer 150 covers the semiconductor pattern 15 and the common electrode 14 and extends onto the gate insulating layer 110.
  • the material of the etch barrier layer 150 includes, but is not limited to, silicon oxide.
  • the etch barrier layer 150 is exposed and developed by an etching process using a sixth mask (not shown), and the etch barrier layer is exposed and etched to form an area corresponding to the first conductor pattern 12 and the second conductor pattern 13.
  • the barrier via via 22 is used to electrically connect the drain electrode 17 and the source electrode 16 to the first conductor pattern 12 and the second conductor pattern 13, respectively.
  • the function of the etch barrier layer 150 is to protect the semiconductor pattern 15, the first conductor pattern 12 and the second conductor pattern 13 from corrosion during the process of forming the source electrode 16 and the drain electrode 17. Steps S25 to S28 are similar to steps S14 to S17 of the above embodiment, and are not described herein again.
  • the TFL array substrate 2 of the present embodiment is an ESL (English: Etch stopper
  • the array substrate of the structure of the etch barrier layer is different from the array substrate 1 of the BCE structure shown in FIG. 8 in that the TFL array substrate 2 further includes an etch barrier layer 150, and the etch barrier layer 150 corresponds to The region above the first conductor pattern 12 and the second conductor pattern 13 is formed with an etch barrier via 21 such that the drain electrode 15 and the source electrode 16 located above the first conductor pattern 12 and the second conductor pattern 13 are blocked by etching.
  • the via vias 21 are electrically connected to the first conductor pattern 12 and the second conductor pattern 13, respectively.
  • the array substrate process of the present embodiment is similar to the process of the above embodiment, which can reduce the number of masks, improve production efficiency, and reduce production cost, and can also avoid forming a drain electrode by etching by providing an etch barrier layer.
  • the semiconductor pattern 15 and the first conductor pattern 12 and the second conductor pattern 13 are erroneously etched with the source electrode.
  • the TFT array substrate of the present invention is etched into the first semiconductor pattern and the second semiconductor pattern by the same mask process through the same mask process, and then doped. Both ends of the first semiconductor pattern are respectively processed into spaced apart first and second conductor patterns and the second semiconductor pattern is processed into a common electrode, and the remaining first semiconductor pattern after processing is located above the bottom gate electrode. Therefore, the method of fabricating the TFT array substrate of the present invention can reduce the number of masks, improve production efficiency, and reduce production costs.

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Abstract

一种TFT阵列基板及其制作方法，TFT阵列基板通过同一道光罩工艺将第一金属氧化物半导体层（120）蚀刻成第一半导体图案（121）及第二半导体图案（122）后进行掺杂处理，以将第一半导体图案（121）的两端分别处理成间隔设置的第一导体图案（12）和第二导体图案（13）且将第二半导体图案（122）处理成公共电极（14），并且处理后剩余的第一半导体图案（15）位于底栅电极（11）上方。上述TFT阵列基板的制作方法能够减少光罩次数，提高生产效率和降低生产成本。

Description

一种TFT阵列基板及其制作方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种TFT阵列基板及其制作方法。
【背景技术】
有源矩阵驱动的LCD显示技术利用了液晶的双极性偏振特点，通过施加电场控制液晶分子的排列方向，实现对背光源光路行进方向的开关作用。根据对液晶分子施加电场方向的不同，可以将LCD显示模式分为TN, VA及IPS系列模式。VA系列模式指对液晶分子施加纵向电场，而IPS系列模式指对液晶分子施加横向电场。而在IPS系列模式中，对于施加横向电场的不同，又可分为IPS模式和FFS模式等。其中FFS显示模式的每一个像素单元含有上下两层电极，即像素电极和公共电极，且下层的公共电极采用开口区整面平铺的方式。FFS显示模式具有高透过率，广视角以及较低的色偏等优点，是一种广泛应用的LCD显示技术。
在有源阵列显示装置中，常采用的是Single-gate TFT（单栅极薄膜晶体管），但是Dual gate TFT（双栅极晶体管）与Single-gate TFT（单栅极薄膜晶体管）相比，不仅具有较高的迁移率，较大的开态电流，更小的亚阈值摆幅，阈值电压（Vth）稳定性和均匀性好等优点，还具有更好的栅极偏压稳定性。然而，传统的FFS显示模式的Dual-Gate TFT阵列基板制造方法需要更多的光罩次数，增加了工艺的复杂性以及生产成本。
【发明内容】
有鉴于此，本发明提供一种TFT阵列基板及其制作方法，能够减少光罩次数，提高生产效率和降低生产成本。
为解决上述问题，本发明提供一种TFT阵列基板的制作方法，包括：
提供一基板；
在基板上形成第一金属层，并采用第一光罩工艺将第一金属层蚀刻成底栅电极；
在基板上进一步形成第一金属氧化物半导体层，并采用第二光罩工艺将第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理，以将第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将第二半导体图案处理成第三导体图案，其中，处理后剩余的第一半导体图案位于底栅电极的上方，第三导体图案作为公共电极，
其中，在金属氧化物半导体层上形成光阻图案，光阻图案包括对应于第一半导体图案的第一光阻图案以及对应于第二半导体图案的第二光阻图案，第一光阻图案的中间区域的光阻厚度大于第一光阻图案两端的光阻厚度且大于第二光阻图案的光阻厚度，
以第一光阻图案和第二光阻图案为掩膜将金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案，
以第一光阻图案和第二光阻图案为掩膜对第一半导体图案及第二半导体图案进行等离子处理，进而将第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将第二半导体图案处理成第三导体图案；
在基板上进一步形成刻蚀阻挡层，并采用第六光罩工艺对刻蚀阻挡层进行蚀刻形成分别位于第一导体图案和第二导体图案上方的刻蚀阻挡层过孔；
在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成源电极及漏电极，其中漏电极覆盖在第一导体图案上，源电极覆盖在第二导体图案上；
在基板上进一步形成第一钝化层，并采用第四光罩工艺对第一钝化层进行刻蚀，以形成过孔；
在基板上进一步形成第二金属氧化物导体层，并采用第五光罩工艺将第二金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，顶栅电极位于处理后剩余的第一半导体图案的上方，像素电极与公共电极至少部分重叠设置且通过过孔与源电极及漏电极中的一者电连接。
其中，金属氧化物半导体层为IGZO氧化物半导体层。
其中，第二光罩工艺采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种形成光阻图案。
其中，刻蚀阻挡层的材料为氧化硅。
本发明还提供一种TFT阵列基板的制作方法，包括：
提供一基板；
在基板上形成第一金属层，并采用第一光罩工艺将第一金属层蚀刻成底栅电极；
在基板上进一步形成第一金属氧化物半导体层，并采用第二光罩工艺将第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理，以将第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将第二半导体图案处理成第三导体图案，其中，处理后剩余的第一半导体图案位于底栅电极的上方，第三导体图案作为公共电极；
在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成源电极及漏电极，其中漏电极覆盖在第一导体图案上，源电极覆盖在第二导体图案上；
在基板上进一步形成第一钝化层，并采用第四光罩工艺对第一钝化层进行刻蚀，以形成过孔；
在基板上进一步形成第二金属氧化物导体层，并采用第五光罩工艺将第二金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，顶栅电极位于处理后剩余的第一半导体图案的上方，像素电极与公共电极至少部分重叠设置且通过过孔与源电极及漏电极中的一者电连接。
其中，金属氧化物半导体层为IGZO氧化物半导体层。
其中，在基板上进一步形成金属氧化物半导体层，并采用第二光罩工艺将金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理的步骤包括：
在金属氧化物半导体层上形成光阻图案，其中光阻图案包括对应于第一半导体图案的第一光阻图案以及对应于第二半导体图案的第二光阻图案，第一光阻图案的中间区域的光阻厚度大于第一光阻图案两端的光阻厚度且大于第二光阻图案的光阻厚度；
以第一光阻图案和第二光阻图案为掩膜将金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案；
以第一光阻图案和第二光阻图案为掩膜对第一半导体图案及第二半导体图案进行等离子处理，进而将第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将第二半导体图案处理成第三导体图案。
其中，第二光罩工艺采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种形成光阻图案。
其中，在基板上进一步形成金属氧化物半导体层，并采用第二光罩工艺将金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理的步骤与在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成源电极及漏电极的步骤之间，制作方法还包括：
在基板上进一步形成刻蚀阻挡层，并采用第六光罩工艺对刻蚀阻挡层进行蚀刻形成分别位于第一导体图案和第二导体图案上方的刻蚀阻挡层过孔。
其中，刻蚀阻挡层的材料为氧化硅。
为解决上述问题，本发明提供的一种阵列基板，包括：基板；形成在基板上的底栅电极；形成于基板上的半导体图案、位于半导体图案两端且间隔设置的第一导体图案和第二导体图案以及公共电极，其中半导体图案、第一导体图案、第二导体图案以及公共电极由同一金属氧化物半导体层形成。
其中，金属氧化物半导体层为IGZO氧化物半导体层。
其中，阵列基板进一步包括位于第一导体图案上方的漏电极、位于第二导体图案上方的源电极。
其中，阵列基板进一步包括刻蚀阻挡层，刻蚀阻挡层上分别形成有对应于第一导体图案和第二导体图案的过孔，漏电极和源电极通过过孔与半导体图案电连接。
通过上述方案，本发明的有益效果是：区别于现有技术，本发明的采用同一道光罩工艺将第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理，以将第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将第二半导体图案处理成公共电极，并且处理后剩余的第一半导体图案位于底栅电极上方，因此，本发明的TFT阵列基板的制造可减少光罩的次数，提高生产效率和降低生产成本。
【附图说明】
图1是本发明TFT阵列基板的制作方法的第一实施方式的流程示意图；
图2A至图2G是图1中TFT阵列基板的第一实施方式中制备底栅电极、公共电极、第一导体图案和第二导体图案的工艺流程图；
图3是图1中TFT阵列基板的第三光罩工艺形成源电极及漏电极的工艺示意图；
图4是图1中TFT阵列基板的第四光罩工艺形成过孔的工艺示意图；
图5是由图1中TFT阵列基板的制作方法的第一实施方式制得的TFT阵列基板的结构示意图；
图6是本发明TFT阵列基板的制作方法的第二实施方式的流程示意图；
图7是图6中TFT阵列基板的制作方法的第二实施方式制得的TFT阵列基板的结构示意图。
【具体实施方式】
为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚、明白，以下结合附图和实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参看图1，图1是本发明TFT阵列基板的制作方法的第一实施方式的流程示意图，如图1所示，本实施方式的TFT阵列基板的制作方法包括：
S11：提供一基板。
S12：在基板上形成第一金属层，并采用第一光罩工艺将第一金属层蚀刻成底栅电极。
请参看图2A，图2A为图1中TFT阵列基板的第一实施方式中制得的底栅电极结构示意图。其中，基板100作为衬底基板，其可以为玻璃基板、塑料基板或其他合适材质的基板。在本实施方式中，基板100优选为具有透光的特性的玻璃基板。
其中，采用物理气相沉积法（简称PVD）在基板100上沉积第一金属层（图未示），第一金属层的材料包括但不限于为铬、铝、钛或其他金属材料。图2A中所示的是由第一金属层经第一光罩曝光显示蚀刻后制得的底栅电极11的结构示意图。
S13：在基板上进一步形成第一金属氧化物半导体层，并采用第二光罩工艺将第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理。
如图2B所示，先在基板100上覆盖一层栅绝缘层110，并进一步在栅绝缘层110上通过PVD法沉积形成第一金属氧化物半导体层120。其中，栅绝缘层110覆盖底栅电极11并延伸到基板100上，该栅绝缘层110可以采用化学气相沉积法形成，栅绝缘层110的材质包括但不限于为氮化硅、氧化硅或氮氧化硅。第一金属氧化物半导体层120的材料优选为IGZO（Indium Gallium Zinc Oxide），IGZO是一种含有铟、镓和锌的非晶金属氧化物，是用于新一代薄膜晶体管技术中的沟道层材料，IGZO的载流子迁移率是非晶硅的20~30倍，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在TFT-LCD中成为可能，另外，由于晶体管数量减少和提高了每个像素的透光率，IGZO显示器具有更高的能效水平，而且效率更高，并且IGZO可以利用现有的非晶硅生产线生产，只需稍加改动，因此在成本方面IGZO比低温多晶硅更具有竞争力。
请继续参看图2C，进一步在第一金属氧化物半导体层120覆盖一层光阻层（图未示），采用第二光罩20对光阻层进行曝光显影。第二光罩20为半色调掩膜（Halt-tone Mask；简称HTM）、灰色调掩膜(Gray-tone Mask；简称GTM)或单狭缝掩膜（Single slit Mask；简称SSM）中的任一种。第二光罩20包括透光部201、半透光部202及不透光部203。采用第二光罩20对具有第一金属氧化物导体层120的基板100进行曝光后，光阻层对应第二光罩20的透光部201的区域完全曝光，对应第二光罩20的半透光部202的区域半曝光，对应第二光罩20的不透光部203的区域不曝光。因此，在采用第二光罩20对光阻层进行曝光、半曝光、不曝光及显影的制程后相应获得第一光阻图案2030和第二光阻图案2020，其中第一光阻图案2030包括第一光阻部2031和第二光阻部2032，第二光阻图案2020包括第二光阻部2032，第一光阻部2031的厚度大于第二光阻部2032，第一光阻图案2030为中间是第一光阻部2031，第一光阻部2031的两端是第二光阻部2032的光阻图案。第一光阻部2031对应于第二光罩20的不透光部203，第二光阻部2032对应于第二光罩20的半透光部202。
如图2D所示，进一步对没有被光阻部覆盖的区域进行湿刻去除，本实施方式中指去掉没有被第一光阻图案2030和第二光阻图案2020覆盖的第一金属氧化物导体层120对应的区域。因此，第一金属氧化物导体层120经过第二光罩20的曝光显影及蚀刻工艺后，形成了位于第二光阻图案2020下方的第二半导体图案122及位于第一光阻图案2030下方的第一半导体图案121。
如图2E所示，使用氧气对第一光阻部2031和第二光阻部2032进行灰化，以使得厚度较薄的第二光阻部2032被去掉，从而被第二光阻部2032覆盖的第一金属氧化物导体层120对应的区域裸露出来。第一光阻部2031保留部分光阻。本实施方式中，位于第二光阻图案2020下方的第二半导体图案122被裸露出来，而位于第一光阻图案2030下方的第一半导体图案121的两端也被裸露出来。
请参看图2F，使用氦气或氩气进行等离子处理（英文为：Plasma treatment），使得没有被光阻覆盖的第一金属氧化物导体层120被处理成相应的导体，而还有光阻覆盖的第一金属氧化物导体层120依然还是导体。本实施方式中指将IGZO半导体通过Plasma treatment法处理成相应的IGZO导体。其中，第二半导体图案122被Plasma treatment处理成相应的第三导体图案14，第一半导体图案121的两端被Plasma treatment处理成相应的第一导体图案12和第二导体图案13，第一导体图案12和第二导体图案13间隔设置。而被余下的光阻部覆盖的部分第一金属氧化物导体层120未被Plasma treatmen处理。
请参看图2G，将第一光阻部2031余下的光阻剥离去除，从而使得被第一光阻部2031余下的光阻覆盖部分的第一金属氧化物导体层120被保留为半导体图案15。因此，半导体图案15的两端分别为第一导体图案12和第二导体图案13，半导体图案15对应于底栅电极11的上方，第三导体图案14作为阵列基板的公共电极14。
S14：在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成源电极及漏电极。
如图3所示，在基板100上进一步形成第二金属层（图未示），并在第二金属层上方覆盖一层光阻层（图未示），采用第三光罩（图未示）对第二金属层上的光阻层进行曝光，并进行显影蚀刻的制程后，形成位于第一导体图案12上方漏电极17及位于第二导体图案13上方的源电极16，其中，采用第三光罩制作源电极16及漏电极17的工艺采用的是现有技术的工艺，在此不再过多的赘述。
S15：在基板上进一步形成第一钝化层，并采用第四光罩工艺对第一钝化层进行刻蚀，以形成过孔。
如图4所示，进一步在基板100上形成第一钝化层130，第一钝化层130覆盖源电极16及漏电极17、公共电极14并延伸到栅绝缘层110上。采用第四光罩（图未示）对第一钝化层130进行曝光、显影及蚀刻等制程后，以使对应于源电极16或漏电极17上方的第一钝化层130的区域形成过孔18。其中，形成过孔18的方法采用的是现有技术的方法，在此不作过多的赘述。
S16：在基板上进一步形成第二金属氧化物导体层，并采用第五光罩工艺将第二金属氧化物导体层蚀刻成顶栅电极和像素电极。
S17：在基板上进一步形成第二钝化层。
请参看图5，图5是由图1中TFT阵列基板的制作方法的第一实施方式制得的TFT阵列基板的结构示意图，结合图5说明步骤S16至S17的实施方式。在基板100的第一钝化层130上进一步形成第二透明金属氧化物导体层（图未示），第二透明金属氧化物导体层的材料包括但不限于为ITO（英文为：Indium tin oxide，中文为：氧化铟锡），ITO是一种具有良好的导电性和透明性的金属氧化物。
采用第五光罩（图未示）对第二金属氧化物导体层进行曝光，并进行显影蚀刻后，形成顶栅电极19和多个像素电极20。其中，顶栅电极19与底栅电极11对应设置。像素电极20与公共电极14至少部分重叠设置，且其中一个像素电极20通过过孔18与源电极16及漏电极17中的一者电连接。图5中所示的是一个像素电极20通过过孔18与源电极16连接，其余的像素电极20间隔排列在公共电极14的上方。并在基板100上进一步形成第二钝化层140，第二钝化层140覆盖像素电极20、顶栅电极19并延伸到第一钝化层130上
其中，由第二透明金属氧化物导体层制作像素电极20和顶栅电极19并覆盖第二钝化层130采用的是现有的技术方法，在此不再过多的赘述。本实施方式的金属氧化物TFT阵列基板1为BCE（英文为：Back Channel Etch，中文为：背沟道刻蚀结构）结构的阵列基板。
综上，本实施方式的氧化物TFT阵列基板通过同一道光罩工艺将第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理，以将第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将第二半导体图案处理成公共电极，并且处理后剩余的第一半导体图案位于底栅电极上方，从而可以减少阵列基板的制程中的光罩次数，提高生产效率和降低生产成本。
请参看图6，图6是本发明TFT阵列基板的制作方法的第二实施方式的流程示意图。如图6所示，本实施方式的TFT阵列基板的制作方法包括：
S21：提供一基板。
S22：在基板上形成第一金属层，并采用第一光罩工艺将第一金属层蚀刻成底栅电极。
S23：在基板上进一步形成第一金属氧化物半导体层，并采用第二光罩工艺将第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理。
S24：在基板上进一步形成刻蚀阻挡层，并采用第六光罩工艺对刻蚀阻挡层进行蚀刻形成分别位于第一导体图案和第二导体图案上方的刻蚀阻挡层过孔。
S25：在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成源电极及漏电极。
S26：在基板上进一步形成第一钝化层，并采用第四光罩工艺对第一钝化层进行刻蚀，以形成过孔。
S27：在基板上进一步形成第二金属氧化物导体层，并采用第五光罩工艺将第二金属氧化物导体层蚀刻成顶栅电极和像素电极。
S28：在基板上进一步形成第二钝化层。
其中，请结合图1至图5一并参考，本实施方式与上述实施方式的区别在于，图2A至图2G所示的在采用第二光罩蚀刻出第一半导体图案121及第二半导体图案122，并进行掺杂形成第一导体图案12、第二导体图案13、公共电极14及半导体图案15后，本实施方式还在基板100上进一步形成刻蚀阻挡层150，如图7所示，图7是图6的实施方式中形成的TFL阵列基板的结构示意图。其中，刻蚀阻挡层150覆盖半导体图案15、公共电极14并延伸到栅绝缘层110上，刻蚀阻挡层150的材料包括但不限于为氧化硅。采用第六光罩（图未示）对刻蚀阻挡层150进行曝光显影并进行蚀刻工艺，将刻蚀阻挡层对应于第一导体图案12及第二导体图案13的区域进行曝光蚀刻形成刻蚀阻挡层过孔22，刻蚀阻挡层过孔22用于使漏电极17和源电极16分别与第一导体图案12及第二导体图案13电连接。其中，刻蚀阻挡层150的作用是使得在形成源电极16和漏电极17的工艺制程中保护半导体图案15、第一导体图案12及第二导体图案13不被腐蚀。步骤S25至步骤S28至上述实施方式的步骤S14至步骤S17类似，在此不再赘述。
本实施方式的TFL阵列基板2为ESL（英文为：Etch stopper layer；中文为：刻蚀阻挡层）结构的阵列基板，与图8所示的BCE结构的阵列基板1的区别在于，TFL阵列基板2还包括刻蚀阻挡层150，刻蚀阻挡层150对应于第一导体图案12及第二导体图案13上方的区域形成有刻蚀阻挡层过孔21，使得位于第一导体图案12及第二导体图案13上方的漏电极15和源电极16通过刻蚀阻挡层过孔21分别与第一导体图案12及第二导体图案13电连接。
综上，本实施方式的阵列基板制程工艺与上述实施方式的工艺类似，其可以减少光罩的次数，提高生产效率和降低生产成本，并且通过设置刻蚀阻挡层还可以避免在蚀刻形成漏电极和源电极时误腐蚀半导体图案15和第一导体图案12及第二导体图案13。
综上所述，区域别于现有技术，本发明的TFT阵列基板通过同一道光罩工艺将第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理，以将第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将第二半导体图案处理成公共电极，并且处理后剩余的第一半导体图案位于底栅电极上方。从而本发明的TFT阵列基板的制作方法能够减少光罩次数，提高生产效率和降低生产成本。
以上参照附图说明了本发明的优选实施例，并非因此局限本发明的权利范围。本领域技术人员不脱离本发明的范围和实质内所作的任何修改、等同替换和改进，均应在本发明的权利范围之内。

Claims (14)

  1. 一种TFT阵列基板的制作方法，其中，所述制作方法包括：
    提供一基板；
    在所述基板上形成第一金属层，并采用第一光罩工艺将所述第一金属层蚀刻成底栅电极；
    在所述基板上进一步形成第一金属氧化物半导体层，并采用第二光罩工艺将所述第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理，以将所述第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将所述第二半导体图案处理成第三导体图案，其中，处理后剩余的所述第一半导体图案位于所述底栅电极的上方，所述第三导体图案作为公共电极，
    其中，在所述金属氧化物半导体层上形成光阻图案，所述光阻图案包括对应于所述第一半导体图案的第一光阻图案以及对应于所述第二半导体图案的第二光阻图案，所述第一光阻图案的中间区域的光阻厚度大于所述第一光阻图案两端的光阻厚度且大于所述第二光阻图案的光阻厚度，
    以所述第一光阻图案和所述第二光阻图案为掩膜将所述金属氧化物半导体层蚀刻成所述第一半导体图案及第二半导体图案，
    以所述第一光阻图案和所述第二光阻图案为掩膜对所述第一半导体图案及第二半导体图案进行等离子处理，进而将所述第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将所述第二半导体图案处理成第三导体图案；
    在所述基板上进一步形成刻蚀阻挡层，并采用第六光罩工艺对所述刻蚀阻挡层进行蚀刻形成分别位于所述第一导体图案和第二导体图案上方的刻蚀阻挡层过孔；
    在所述基板上进一步形成第二金属层，并采用第三光罩工艺将所述第二金属层蚀刻成源电极及漏电极，其中所述漏电极覆盖在所述第一导体图案上，所述源电极覆盖在所述第二导体图案上；
    在所述基板上进一步形成第一钝化层，并采用第四光罩工艺对所述第一钝化层进行刻蚀，以形成过孔；
    在所述基板上进一步形成第二金属氧化物导体层，并采用第五光罩工艺将所述第二金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，所述顶栅电极位于处理后剩余的所述第一半导体图案的上方，所述像素电极与所述公共电极至少部分重叠设置且通过所述过孔与所述源电极及漏电极中的一者电连接。
  2. 根据权利要求1所述的制作方法，其中，所述金属氧化物半导体层为IGZO氧化物半导体层。
  3. 根据权利要求1所述的制作方法，其中，所述第二光罩工艺采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种形成所述光阻图案。
  4. 根据权利要求1所述的制作方法，其中，所述刻蚀阻挡层的材料为氧化硅。
  5. 一种TFT阵列基板的制作方法，其中，所述制作方法包括：
    提供一基板；
    在所述基板上形成第一金属层，并采用第一光罩工艺将所述第一金属层蚀刻成底栅电极；
    在所述基板上进一步形成第一金属氧化物半导体层，并采用第二光罩工艺将所述第一金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理，以将所述第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将所述第二半导体图案处理成第三导体图案，其中，处理后剩余的所述第一半导体图案位于所述底栅电极的上方，所述第三导体图案作为公共电极；
    在所述基板上进一步形成第二金属层，并采用第三光罩工艺将所述第二金属层蚀刻成源电极及漏电极，其中所述漏电极覆盖在所述第一导体图案上，所述源电极覆盖在所述第二导体图案上；
    在所述基板上进一步形成第一钝化层，并采用第四光罩工艺对所述第一钝化层进行刻蚀，以形成过孔；
    在所述基板上进一步形成第二金属氧化物导体层，并采用第五光罩工艺将所述第二金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，所述顶栅电极位于处理后剩余的所述第一半导体图案的上方，所述像素电极与所述公共电极至少部分重叠设置且通过所述过孔与所述源电极及漏电极中的一者电连接。
  6. 根据权利要求5所述的制作方法，其中，所述金属氧化物半导体层为IGZO氧化物半导体层。
  7. 根据权利要求5所述的制作方法，其中，所述在所述基板上进一步形成金属氧化物半导体层，并采用第二光罩工艺将所述金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理的步骤包括：
    在所述金属氧化物半导体层上形成光阻图案，其中所述光阻图案包括对应于所述第一半导体图案的第一光阻图案以及对应于所述第二半导体图案的第二光阻图案，所述第一光阻图案的中间区域的光阻厚度大于所述第一光阻图案两端的光阻厚度且大于所述第二光阻图案的光阻厚度；
    以所述第一光阻图案和所述第二光阻图案为掩膜将所述金属氧化物半导体层蚀刻成所述第一半导体图案及第二半导体图案；
    以所述第一光阻图案和所述第二光阻图案为掩膜对所述第一半导体图案及第二半导体图案进行等离子处理，进而将所述第一半导体图案的两端分别处理成间隔设置的第一导体图案和第二导体图案且将所述第二半导体图案处理成第三导体图案。
  8. 根据权利要求7所述的制作方法，其中，所述第二光罩工艺采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种形成所述光阻图案。
  9. 根据权利要求5所述的制作方法，其中，所述在所述基板上进一步形成金属氧化物半导体层，并采用第二光罩工艺将所述金属氧化物半导体层蚀刻成第一半导体图案及第二半导体图案后进行掺杂处理的步骤与所述在所述基板上进一步形成第二金属层，并采用第三光罩工艺将所述第二金属层蚀刻成源电极及漏电极的步骤之间，所述制作方法还包括：
    在所述基板上进一步形成刻蚀阻挡层，并采用第六光罩工艺对所述刻蚀阻挡层进行蚀刻形成分别位于所述第一导体图案和第二导体图案上方的刻蚀阻挡层过孔。
  10. 根据权利要求9所述的制作方法，其中，所述刻蚀阻挡层的材料为氧化硅。
  11. 一种TFT阵列基板，其中，所述阵列基板包括：
    基板；
    形成在所述基板上的底栅电极；
    形成于所述基板上的半导体图案、位于所述半导体图案两端且间隔设置的第一导体图案和第二导体图案以及公共电极，其中所述半导体图案、第一导体图案、第二导体图案以及公共电极由同一金属氧化物半导体层形成。
  12. 根据权利要求11所述的阵列基板，其中，所述金属氧化物半导体层为IGZO氧化物半导体层。
  13. 根据权利要求11所述的阵列基板，其中，所述阵列基板进一步包括位于所述第一导体图案上方的漏电极、位于所述第二导体图案上方的源电极。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板进一步包括刻蚀阻挡层，所述刻蚀阻挡层上分别形成有对应于所述第一导体图案和第二导体图案的过孔，所述漏电极和所述源电极通过所述过孔与所述半导体图案电连接。
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