CN105629598B - Ffs模式的阵列基板及制作方法 - Google Patents

Ffs模式的阵列基板及制作方法 Download PDF

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CN105629598B
CN105629598B CN201610141337.3A CN201610141337A CN105629598B CN 105629598 B CN105629598 B CN 105629598B CN 201610141337 A CN201610141337 A CN 201610141337A CN 105629598 B CN105629598 B CN 105629598B
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layer
electrode
region
insulating layer
pixel electrode
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CN105629598A (zh
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葛世民
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to CN201610141337.3A priority Critical patent/CN105629598B/zh
Priority to US15/116,514 priority patent/US20170373101A1/en
Priority to PCT/CN2016/078755 priority patent/WO2017152451A1/zh
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Abstract

本发明提供一种FFS模式的阵列基板及制作方法，该FFS模式的阵列基板包括基层，该基层设置有栅极以及沟道半导体层；第二绝缘层，其沉积于所述基层上，该第二绝缘层上形成有将该沟道半导体层露出的第一过孔以及第二过孔；像素电极层，其沉积于所述第二绝缘层上，所述像素电极层上设置有像素电极；源极以及漏极，该源极以及漏极设置于所述像素电极层之上；第三绝缘层，其设置于源极、漏极、像素电极以及第二绝缘层上。本发明具有缩短工艺流程、减少光罩次数的有益效果。

Description

FFS模式的阵列基板及制作方法
技术领域
本发明涉及显示领域，特别是涉及一种曲面液晶显示面板及曲面液晶显示装置。
背景技术
有源矩阵驱动的LCD显示技术利用了液晶的双极性偏振特点，通过施加电场控制液晶分子的排列方向，实现对背光源光路行进方向的开关控制。根据对液晶分子施加电场方向的不同，可以将LCD显示模式分为TN系列模式,VA系列模式及IPS系列模式。VA系列模式指对液晶分子施加纵向电场，而IPS系列模式指对液晶分子施加横向电场。而在IPS系列模式中，对于施加横向电场的不同，又可分为IPS模式和FFS模式等。其中FFS显示模式的每一个像素单元含有上下两层电极，即像素电极和公共电极，且下层的公共电极采用开口区整面平铺的方式。FFS显示模式具有高透过率，广视角以及较低的色偏等优点，是一种广泛应用的LCD显示技术。
为了提高氧化物TFT的稳定性，刻蚀阻挡层(ESL)结构的TFT结构被广泛采用，该结构可以有效降低外界环境因素与源漏电极的刻蚀损伤对背沟道的影响。然而，ESL结构的传统FFS显示模式阵列基板制造方法需要更多的光罩次数，增加了工艺的复杂性以及生产成本。
发明内容
本发明的目的在于提供一种FFS模式的阵列基板及其制作方法；以解决现有技术中ESL结构的传统FFS显示模式阵列基板制造方法需要更多的光罩次数，增加了工艺的复杂性以及生产成本的技术问题。
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种FFS模式的阵列基板的制作方法，其特征在于，包括以下步骤：
形成一基层，该基层设置有栅极以及沟道半导体层；
在基层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔；
在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
去除第一光阻层，并除去位于像素电极上的第一金属层；
在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层。
在本发明所述的FFS模式的阵列基板的制作方法中，所述形成一基层的步骤包括：
在玻璃基板上形成栅极；
在玻璃基板以及栅极上依次沉积第一绝缘层以及半导体层，该半导体层设置有沟道区域、公共电极区域以及位于公共电极区域与沟道区域之间的第三间隔区域；
在该半导体层上涂布第二光阻层，将该第二光阻层上与所述第三间隔区域正对区域的光阻去除；
对所述半导体层进行刻蚀，以在半导体层的沟道区域形成所述沟道半导体层，在该半导体层的公共电极区域形成待掺杂半导体层；
去除待掺杂半导体层上的第二光阻层，并对该待掺杂半导体层进行掺杂以形成公共电极层；
去除该沟道半导体层上的第二光阻层；
其中，所述第二绝缘层沉积于该沟道半导体层、公共电极层以及第一绝缘层上。
在本发明所述的FFS模式的阵列基板的制作方法中，所述沟道半导体层设置有两个分别与所述第一过孔以及第二过孔对应的掺杂区域，所述去除该沟道半导体层上的第二光阻层的步骤包括：
将所述沟道半导体层的两个掺杂区域上的第二光阻层去除，并对该两个掺杂区域进行掺杂，以将该沟道半导体层位于该两个掺杂区域的半导体转换为导体，然后去除所述沟道半导体层上剩余的第二光阻层。
在本发明所述的FFS模式的阵列基板的制作方法中，所述形成一基层的步骤包括：
在玻璃基板上依次沉积公共电极层以及第二金属层，第二金属层设有栅极区域，公共电极层设有公共电极区域、TFT区域以及位于公共电极区域与TFT区域之间的第四间隔区域；
在第二金属层上涂布第三光阻层，将第三光阻层上与第四间隔区域正对区域的光阻除去；
对第二金属层以及公共电极层进行刻蚀，以在该公共电极层的公共电极区域形成公共电极，在第二金属层的栅极区域形成栅极；
将公共电极上的第三光阻层以及第二金属层依次除去，将栅极上的第三光阻层除去；
在公共电极、栅极以及玻璃基板上沉积第一绝缘层，在该第一绝缘层上形成所述沟道半导体层；
其中，所述第二绝缘层沉积于所述沟道半导体层以及第一绝缘层之上。
在本发明所述的FFS模式的阵列基板的制作方法中，所述第二绝缘层以及所述第三绝缘层均包括氮化硅和/或二氧化硅。
在本发明所述的FFS模式的阵列基板的制作方法中，所述沟道半导体层包括铟镓锌氧化物。
本发明还提供了一种FFS模式的阵列基板，包括：
基层，该基层设置有栅极以及沟道半导体层；
第二绝缘层，其沉积于所述基层上，该第二绝缘层上形成有将该沟道半导体层露出的第一过孔以及第二过孔；
像素电极层，其沉积于所述第二绝缘层上，所述像素电极层上设置有像素电极；
源极以及漏极，该源极以及漏极设置于所述像素电极层之上；
第三绝缘层，其设置于源极、漏极、像素电极以及第二绝缘层上。
在本发明所述的FFS模式的阵列基板中，所述基层还包括：
玻璃基板，所述栅极设置于该玻璃基板上；
第一绝缘层，其设置于该玻璃基板以及栅极上；
半导体层，其设置于所述第一绝缘层上，所述半导体层包括沟道区域以及公共电极区域，在所述半导体层的沟道区域形成所述沟道半导体层，在所述半导体层的公共电极区域的半导体掺杂形成公共电极层；
所述第二绝缘层设置于该沟道半导体层、公共电极层以及第一绝缘层上。
在本发明所述的FFS模式的阵列基板中，所述基层还包括：
玻璃基板；
公共电极层，其设置于玻璃基板上，所述栅极设置于所述公共电极层之上；
第一绝缘层，其设置于公共电极层、栅极以及玻璃基板上；
所述沟道半导体层设置于所述第一绝缘层上并位于所述栅极上方，所述第二绝缘层沉积于所述沟道半导体层以及第一绝缘层之上。
在本发明所述的FFS模式的阵列基板中，所述沟道半导体层包括铟镓锌氧化物。
本实施例中，通过将源极和漏极设置在像素电极层之上，从而使得在制作过程中，可以通过一道光罩同时形成该源极、漏极以及像素电极，具有缩短工艺流程，提高生产效率的有益效果。
附图说明
图1为本发明的FFS模式的阵列基板的第一优选实施例的结构示意图；
图2为本发明的FFS模式的阵列基板的第二优选实施例的结构示意图；
图3为本发明的FFS模式的阵列基板的制作方法的第一优选实施例中的流程图；
图4A-图4I为本发明FFS模式的阵列基板的制作方法的第一优选实施例中的具体制作示意图；
图5A-图5J为本发明FFS模式的阵列基板的制作方法的第一优选实施例中的具体制作示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的FFS模式的阵列基板的优选实施例的结构示意图。本优选实施例的一种FFS模式的阵列基板，包括：玻璃基板11、栅极12、半导体层(图1中未标号)、第一绝缘层14、第二绝缘层20、像素电极层30、源极41、漏极42以及第三绝缘层50。其中，该玻璃基板11、栅极12、半导体层(图1中未标号)以及第一绝缘层14组成基层。
具体地，该栅极12设置于该玻璃基板11上。该第一绝缘层14设置于玻璃基板11以及栅极12上，该半导体层设置于该第一绝缘层14上。在本实施例中，该半导体层设置有沟道区域、公共电极区域以及位于该沟道区域和公共电极区域之间的第三间隔区域(未标号)，该沟道区域形成薄膜晶体管的沟道半导体层13，该沟道半导体层13位于栅极12上方。该公共电极区域的半导体层通过掺杂形成公共电极层15，该第三间隔区域的半导体层通过光刻工艺除去。
该第二绝缘层20设置于该第一绝缘层14、公共电极层15以及沟道半导体层13之上。该第二绝缘层20上通过光刻形成有将该沟道半导体层13漏出的第一过孔以及第二过孔。该像素电极层30设置于该第二绝缘层20之上，该像素电极层30设置有位于薄膜晶体管区域的接触部30a以及位于该薄膜晶体管区域一侧的多个像素电极，该接触部30a通过该第一过孔以及第二过孔与沟道半导体层13接触。该源极41以及漏极42均设置于该像素电极层30的接触部30a上，并分别通过接触部30a与沟道半导体层13接触。该第三绝缘层50设置于第二绝缘层20、源极41、漏极42以及像素电极层30之上。
其中，该半导体层采用铟镓锌氧化物，也既是沟道半导体层13采用铟镓锌氧化物，当然其并不限于此。
该第一绝缘层14采用氮化硅和/或二氧化硅制成，其主要用于将栅极12与公共电极层15绝缘开。该第一绝缘层14的厚度为100纳米至300纳米。
该第二绝缘层20采用氮化硅和/或二氧化硅制成，其主要用于将该像素电极层30和公共电极层15绝缘开。该第二绝缘层20的厚度为50纳米至150纳米。
该第三绝缘层50采用氮化硅制成，在本实施例中其为平坦层，主要用于保护该像素电极、源极41、漏极42。
该像素电极层30为氧化铟锡透明电极层或氧化铟锌透明电极层，其厚度为10纳米至100纳米。
进一步地，在本实施例中，该沟道半导体层13上还设置有两个分别与第一过孔以及第二过孔对应的掺杂区域，在该沟道半导体层13的掺杂区域进行掺杂从而将该区域的半导体转换为导体，从而具有降低沟道半导体层13的阻抗的作用。
本实施例中，通过将源极41和漏极42设置在像素电极层30之上，从而使得在制作过程中，可以通过一道光罩同时形成该源极41、漏极42以及像素电极，具有缩短工艺流程，提高生产效率的有益效果。
进一步地，通过将该沟道半导体层13以及公共电极层15设置在同一层，可以通过一道光罩形成，并通过在该半导体层的公共电极区域掺杂形成该公共电极层15，进一步缩短了工艺流程，并提高了生成效率。
请参照图2，图2为本发明的FFS模式的阵列基板的第二优选实施例的结构示意图。本优选实施例的FFS模式的阵列基板包括：玻璃基板11、栅极12、沟道半导体层13、公共电极层15、第一绝缘层14、第二绝缘层20、像素电极层30、源极41、漏极42以及第三绝缘层50。其中，该玻璃基板11、栅极12、沟道半导体层13、公共电极层15、第一绝缘层14组成基层。
具体地，该公共电极层15设置于玻璃基本11上，该栅极12设置于该公共电极层15上，该第一绝缘层14设置于该玻璃基板11、该公共电极层15以及该栅极12之上，该沟道半导体层13设置于该第一绝缘层14上并位于栅极12上方。第二绝缘层20设置于该第一绝缘层14以及沟道半导体层13上。该第二绝缘层20上通过光刻形成有将该沟道半导体层13漏出的第一过孔以及第二过孔。该像素电极层30设置于该第二绝缘层20之上，该像素电极层30设置有位于薄膜晶体管区域的接触部30a以及位于该薄膜晶体管区域一侧的多个像素电极，该接触部30a通过该第一过孔以及第二过孔与沟道半导体层13接触。该第三绝缘层50设置于第二绝缘层20、源极41、漏极42以及像素电极层30之上。
其中，该沟道半导体层13采用铟镓锌氧化物，当然其并不限于此。
该第一绝缘层14采用氮化硅和/或二氧化硅制成，其主要用于将栅极12与公共电极层15绝缘开。该第一绝缘层14的厚度为100纳米至300纳米。
该第二绝缘层20采用氮化硅和/或二氧化硅制成，其主要用于将该像素电极层30和公共电极层15绝缘开。该第二绝缘层20的厚度为50纳米至150纳米。
该第三绝缘层50采用氮化硅制成，在本实施例中其为平坦层，主要用于保护该像素电极、源极41、漏极42。
该像素电极层30为氧化铟锡透明电极层或氧化铟锌透明电极层，其厚度为10纳米至100纳米。
本实施例中，通过将源极41和漏极42设置在像素电极层30之上，从而使得在制作过程中，可以通过一道光罩同时形成该源极41、漏极42以及像素电极，具有缩短工艺流程，提高生产效率的有益效果。
进一步地，通过将该栅极12设置在该像素电极层30上，可以通过一道光罩形成，从而使得在制作过程中，可以通过一道光罩同时形成该栅极12和该像素电极层30，具有缩短工艺流程，提高生产效率的有益效果。
请参照图3，图3是本发明第一优选实施例中的FFS模式的阵列基板的流程图，该方法包括以下步骤：
S301，形成一基层，该基层设置有栅极以及沟道半导体层；
S302，在基层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔；
S303，在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
S304，在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
S305，在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
S306，对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
S307，去除第一光阻层，并除去位于像素电极上的第一金属层；
S308，在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层。
下面结合图4A-图4I对各个步骤进行详细说明。
在步骤S301中，其具体包括以下子步骤：
S31，在玻璃基板上形成栅极；
S32，在玻璃基板以及栅极上依次沉积第一绝缘层以及半导体层，该半导体层设置有沟道区域、公共电极区域以及位于公共电极区域与沟道区域之间的第三间隔区域；
S33，在该半导体层上涂布第二光阻层，将该第二光阻层上与所述第三间隔区域正对区域的光阻去除；
S34，对所述半导体层进行刻蚀，以在半导体层的沟道区域形成所述沟道半导体层，在该半导体层的公共电极区域形成待掺杂半导体层；
S35，去除待掺杂半导体层上的第二光阻层，并对该待掺杂半导体层进行掺杂以形成公共电极层；
S36，去除该沟道半导体层上的第二光阻层；
其中，所述第二绝缘层沉积于该沟道半导体层、公共电极层以及第一绝缘层上。
在该步骤S31中，该栅极13的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，其采用物理气相沉积法沉积形成。如图4A所示，转至步骤S32。
在步骤S32中，该第一绝缘层14采用氮化硅和/或二氧化硅并采用化学气相沉积法沉积形成制成，其主要用于将栅极12与公共电极层15绝缘开。该第一绝缘层14的厚度为100纳米至300纳米。该半导体层1315采用铟镓锌氧化物并采用物理气相沉积法沉积形成。其上分为沟道区域1A、公共电极区域1B以及位于公共电极区域1B与沟道区域1A之间的第三间隔区域1C。如图4B所示，转至步骤S33。
在步骤S33中，采用半色调掩膜工艺或灰色调掩膜工艺，对该第二光阻层100进行处理，使得将该第二光阻层100上与第三间隔区域正对的区域的光阻去除。如图4C所示，转至步骤S34。
在步骤S34中，对该半导体层1315进行刻蚀时可以采用干法也可采用湿法。在步骤S35中，对该待掺杂半导体层进行掺杂以形成公共电极层15时，可以采用氢气或者氦气进行PLASMATREATMENT工艺。如图4D所示，转至步骤S36。
在步骤S36中，在去除该该沟道半导体层13上的第二光阻层100时，可以将光阻氧化的方法。如图4E所示，转至步骤S302。
在步骤S302中，在基层的沟道半导体层、公共电极层以及第一绝缘层上沉积第二绝缘层时，采用氮化硅和/或二氧化硅制成，其主要用于将该像素电极层30和公共电极层15绝缘开。该第二绝缘层20的厚度为50纳米至150纳米。该第一过孔20a以及过孔20b分别将沟道半导体层13露出。如图4F所示，转至步骤S303。
在步骤S303中，该像素电极层30为氧化铟锡透明电极层或氧化铟锌透明电极层，其厚度为10纳米至100纳米。在步骤S304中，该第一金属层40采用物理气相沉淀形成。如图4G所示，转至步骤S305。
在步骤S305中，采用半色调掩膜工艺或灰色调掩膜工艺，对该第二光阻层进行处理将该第二光阻层上与该第三间隔区域正对区域的光阻去除。
在步骤S306中，对第一金属层40和像素电极层30进行刻蚀时，可以采用湿法刻蚀，以在第一金属层40的源极区域和漏极区域分别形成源极41和漏极42，在像素电极层30的像素电极区域形成像素电极。
在步骤S307中，去除第一光阻层时可以采用将其氧化然后去除的方式，去除该像素电极上的第一金属层40时，可以采用本领域的常规技术，不赘述。去除该第一金属层后，形成如图4H所示的结构，转至步骤S308。
在步骤S308中，该第三绝缘层50采用氮化硅制成，在本实施例中其为平坦层，主要用于保护该像素电极、源极41、漏极42。如图4I所示。
进一步地，该沟道半导体层13设置有两个分别与第一过孔20a以及第二过孔20b对应的掺杂区域，该步骤S36包括：
将沟道半导体层的两个掺杂区域上的第二光阻层去除，并对该两个掺杂区域进行掺杂，以将该沟道半导体层位于该两个掺杂区域的半导体转换为导体，然后去除沟道半导体层上剩余的第二光阻层。通过该步骤可以减小沟道半导体层的阻抗。
本实施例中，通过将源极41和漏极42设置在像素电极层30之上，从而使得在制作过程中，可以通过一道光罩同时形成该源极41、漏极42以及像素电极，具有缩短工艺流程，提高生产效率的有益效果。
进一步地，通过将该沟道半导体层13以及公共电极层15设置在同一层，可以通过一道光罩形成，并通过在该半导体层的公共电极区域掺杂形成该公共电极层15，进一步缩短了工艺流程，并提高了生成效率。
在本发明第二优选实施例中的FFS模式的阵列基板的制作方法包括以下步骤：
S301，形成一基层，该基层设置有栅极以及沟道半导体层；
S302，在基层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔；
S303，在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
S304，在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
S305，在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
S306，对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
S307，去除第一光阻层，并除去位于像素电极上的第一金属层；
S308，在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层。
其中，该步骤S301具体包括以下步骤：
S351，在玻璃基板上依次沉积公共电极层以及第二金属层，第二金属层设有栅极区域，公共电极层设有公共电极区域、TFT区域以及位于公共电极区域与TFT区域之间的第四间隔区域；
S352，在第二金属层上涂布第三光阻层，将第三光阻层上与第四间隔区域正对区域的光阻除去；
S353，对第二金属层以及公共电极层进行刻蚀，以在该公共电极层的公共电极区域形成公共电极，在第二金属层的栅极区域形成栅极；
S354，将公共电极上的第三光阻层以及第二金属层依次除去，将栅极上的第三光阻层除去；
S355，在公共电极、栅极以及玻璃基板上沉积第一绝缘层，在该第一绝缘层上形成所述沟道半导体层；
其中，该玻璃基板11、栅极12、沟道半导体层13、公共电极层15、第一绝缘层14组成基层。第二绝缘层20沉积于沟道半导体层13以及第一绝缘层14之上。
下面结合图5A-图5J对各个步骤进行详细说明。
在步骤S351中，该公共电极层15为氧化铟锡透明电极层或氧化铟锌透明电极层，其采用物理气相沉淀形成。其厚度为10纳米至100纳米。该第二金属层12采用物理气相沉淀形成，材料为钼、钛、铝、铜中的一种或多种的堆栈组合。如图5A所示，转至步骤S352。
在步骤S352中，采用半色调掩膜工艺或灰色调掩膜工艺，对该第三光阻层300进行处理，将第三光阻层上与第四间隔区域正对区域的光阻除去。如图5B所示，转至步骤S353。
在步骤S353中，对第二金属层120以及公共电极层15进行刻蚀时，可以采用湿法刻蚀，以在该公共电极层15的公共电极区域形成公共电极，在第二金属层120的栅极区域形成栅极12。如图5C所示，转至步骤S354。
在步骤S354中，将公共电极上的第三光阻层去除时可以采用先氧化后去除的方式，如图5D所示。将公共电极层上的第二金属层去除时，可以采用刻蚀。如图5E所示，转至步骤S355。
在步骤S355中，在公共电极、栅极以及玻璃基板上沉积第一绝缘层时采用化学气相沉淀，该第一绝缘层14采用氮化硅和/或二氧化硅并采用化学气相沉积法沉积形成制成。该沟道半导体层13采用铟镓锌氧化物并采用物理气相沉积法沉积形成。如图5G所示，转至步骤S302。
在步骤S302中，在基层的沟道半导体层13以及第一绝缘层14上沉积第二绝缘层20时，采用氮化硅和/或二氧化硅制成，其主要用于将该像素电极层30和公共电极层15绝缘开。该第二绝缘层20的厚度为50纳米至150纳米。该第一过孔20a以及过孔20b分别将沟道半导体层13露出。如图5H所示，转至步骤S303。
在步骤S303中，该像素电极层30为氧化铟锡透明电极层或氧化铟锌透明电极层，其厚度为10纳米至100纳米。
在步骤S304中，该第一金属层采用物理气相沉淀形成。转至步骤S305。
在步骤S305中，采用半色调掩膜工艺或灰色调掩膜工艺，对该第一光阻层进行处理将该第一光阻层上与该第三间隔区域正对区域的光阻去除。
在步骤S306中，对第一金属层40和像素电极层30进行刻蚀时，可以采用湿法刻蚀，以在第一金属层40的源极区域和漏极区域分别形成源极41和漏极42，在像素电极层30的像素电极区域形成像素电极。如图5I所示，转至步骤S307。
在步骤S307中，去除第一光阻层时可以采用将其氧化然后去除的方式，去除该像素电极上的第一金属层时，可以采用本领域的常规技术，不赘述。转至步骤S308。
在步骤S308中，该第三绝缘层50采用氮化硅制成，在本实施例中其为平坦层，主要用于保护该像素电极、源极41、漏极42。如图5J所示。
本实施例中，通过将源极41和漏极42设置在像素电极层30之上，从而使得在制作过程中，可以通过一道光罩同时形成该源极41、漏极42以及像素电极，具有缩短工艺流程，提高生产效率的有益效果。
进一步地，通过将该栅极12设置在该像素电极层30上，可以通过一道光罩形成，从而使得在制作过程中，可以通过一道光罩同时形成该栅极12和该像素电极层30，具有缩短工艺流程，提高生产效率的有益效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (6)

1.一种FFS模式的阵列基板的制作方法，其特征在于，包括以下步骤：
形成一基层，该基层设置有栅极以及沟道半导体层；
在基层上沉积第二绝缘层，在第二绝缘层上形成将该沟道半导体层露出的第一过孔以及第二过孔；
在第二绝缘层上沉积像素电极层，该像素电极层设置有多个像素电极区域，以及位于相邻两个像素电极区域之间的第一间隔区域；
在像素电极层上沉积第一金属层，该第一金属层设置有源极区域、漏极区域，以及位于源极区域和漏极区域之间的第二间隔区域；
在第一金属层上涂布第一光阻层，将第一光阻层上与第一间隔区域和第二间隔区域正对区域的光阻去除；
对第一金属层和像素电极层进行刻蚀，以在第一金属层的源极区域和漏极区域分别形成源极和漏极，在像素电极层的像素电极区域形成像素电极；
去除第一光阻层，并除去位于像素电极上的第一金属层；
在源极、漏极、像素电极以及第二绝缘层上沉积第三绝缘层；
其中所述形成一基层的步骤包括：
在玻璃基板上依次沉积公共电极层以及第二金属层，第二金属层设有栅极区域，公共电极层设有公共电极区域、TFT区域以及位于公共电极区域与TFT区域之间的第四间隔区域；
在第二金属层上涂布第三光阻层，将第三光阻层上与第四间隔区域正对区域的光阻除去；
对第二金属层以及公共电极层进行刻蚀，以在该公共电极层的公共电极区域形成公共电极，在第二金属层的栅极区域形成栅极；
将公共电极上的第三光阻层以及第二金属层依次除去，将栅极上的第三光阻层除去；
在公共电极、栅极以及玻璃基板上沉积第一绝缘层，在该第一绝缘层上形成所述沟道半导体层；
其中所述第二绝缘层沉积于所述沟道半导体层以及第一绝缘层之上。
2.根据权利要求1所述的FFS模式的阵列基板的制作方法，其特征在于，所述沟道半导体层设置有两个分别与所述第一过孔以及第二过孔对应的掺杂区域，所述去除该沟道半导体层上的第二光阻层的步骤包括：
将所述沟道半导体层的两个掺杂区域上的第二光阻层去除，并对该两个掺杂区域进行掺杂，以将该沟道半导体层位于该两个掺杂区域的半导体转换为导体，然后去除所述沟道半导体层上剩余的第二光阻层。
3.根据权利要求1所述的FFS模式的阵列基板的制作方法，其特征在于，所述第二绝缘层以及所述第三绝缘层均包括氮化硅和/或二氧化硅。
4.根据权利要求1所述的FFS模式的阵列基板的制作方法，其特征在于，所述沟道半导体层包括铟镓锌氧化物。
5.一种FFS模式的阵列基板，其特征在于，包括：
基层，该基层设置有栅极以及沟道半导体层；
第二绝缘层，其沉积于所述基层上，该第二绝缘层上形成有将该沟道半导体层露出的第一过孔以及第二过孔；
像素电极层，其沉积于所述第二绝缘层上，所述像素电极层上设置有像素电极；
源极以及漏极，该源极以及漏极设置于所述像素电极层之上；
第三绝缘层，其设置于源极、漏极、像素电极以及第二绝缘层上；
其中所述基层还包括：
玻璃基板；
公共电极层，其设置于玻璃基板上，所述栅极设置于所述公共电极层之上；
第一绝缘层，其设置于公共电极层、栅极以及玻璃基板上；
所述沟道半导体层设置于所述第一绝缘层上并位于所述栅极上方，所述第二绝缘层沉积于所述沟道半导体层以及第一绝缘层之上。
6.根据权利要求5所述的FFS模式的阵列基板，其特征在于，其特征在于，所述沟道半导体层包括铟镓锌氧化物。
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