WO2016201778A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2016201778A1
WO2016201778A1 PCT/CN2015/087493 CN2015087493W WO2016201778A1 WO 2016201778 A1 WO2016201778 A1 WO 2016201778A1 CN 2015087493 W CN2015087493 W CN 2015087493W WO 2016201778 A1 WO2016201778 A1 WO 2016201778A1
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electrode
layer
metal
line
metal line
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PCT/CN2015/087493
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to the field of display technologies, and in particular to an array substrate and a method of fabricating the same.
  • liquid crystal displays have become the most common display devices.
  • IPS In-Plane Switching
  • FFS Fringe Field Switching
  • amorphous metal oxide semiconductors Compared with amorphous silicon semiconductors, amorphous metal oxide semiconductors have higher mobility and mobility of 10 cm 2 /V ⁇ s or more, so they are widely used in high resolution, high refresh rate display devices. .
  • a patterning process is usually required six times. Therefore, the prior art has a technical problem that the manufacturing process is too complicated.
  • An object of the present invention is to provide an array substrate and a method of manufacturing the same to solve the technical problem that the existing manufacturing process is too complicated.
  • the present invention provides an array substrate including a plurality of sub-pixel units formed on a substrate, each of the sub-pixel units including a thin film transistor, a pixel electrode, and a common electrode;
  • the pixel electrode is formed on the base substrate
  • a drain of the thin film transistor is formed on the pixel electrode, and a source of the thin film transistor is in the same layer as the drain;
  • a semiconductor layer of the thin film transistor is formed on the source and the drain;
  • the pixel electrode, the source, the drain, and the semiconductor layer are covered with a gate insulating layer;
  • the gate of the thin film transistor and the common electrode are formed on the gate insulating layer, wherein the gate is a transparent electrode and is in the same layer as the common electrode.
  • the semiconductor layer is an oxide semiconductor material.
  • the array substrate further includes scan lines and data lines
  • the data line is located in the same layer as the source and the drain;
  • the scan line includes a first metal line and a connection electrode
  • the first metal line and the data line are in the same layer, and the connection electrode and the gate are in the same layer;
  • the gate insulating layer is provided with a first via hole, and the connection electrode is connected to the first metal line through the first via hole.
  • the array substrate further includes a common electrode line, the common electrode line includes a second metal line, and the second metal line and the data line are located in the same layer;
  • the gate insulating layer is provided with a second via hole, and the common electrode is connected to the second metal line through the second via hole.
  • the scan line further includes a third metal line
  • the third metal line is formed on the connection electrode and directly above the first metal line.
  • the common electrode line further includes a fourth metal line
  • the fourth metal line is formed on the common electrode and directly above the second metal line.
  • the invention also provides a method for manufacturing an array substrate, comprising:
  • the first patterning process patterning with a halftone mask to form a pixel electrode, and a source, a drain, a data line, a first metal line, and a second metal line;
  • the second patterning process patterning with a mask to form a semiconductor layer
  • a third patterning process patterning with a mask to form a gate insulating layer, the gate insulating layer having a first via and a second via;
  • a fourth patterning process patterning with a mask to form a gate electrode, a common electrode, and a connection electrode, wherein the connection electrode is connected to the first metal line through the first via hole, and the common electrode passes through the The second via is connected to the second metal line.
  • the first patterning process specifically includes:
  • the remaining photoresist is stripped.
  • a third metal line and a fourth metal line are further formed;
  • the third metal line is formed on the connection electrode and located directly above the first metal line;
  • the fourth metal line is formed on the common electrode and directly above the second metal line.
  • the fourth patterning process specifically includes:
  • the remaining photoresist is stripped.
  • the gate of the thin film transistor is a transparent electrode and is located in the same layer as the common electrode, so that the gate electrode and the common electrode can be simultaneously formed in the same patterning process.
  • the pixel electrode and the source and drain of the thin film transistor in the array substrate may be sequentially formed in the same patterning process by using a halftone mask. Therefore, in the technical solution provided by the present invention, the array substrate can be fabricated by four patterning processes, thereby solving the technical problem that the manufacturing process of the existing array substrate is too complicated.
  • FIG. 1 is a schematic plan view of an array substrate according to Embodiment 1 of the present invention.
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • Figure 3 is a cross-sectional view taken along line B-B of Figure 1;
  • FIG. 4 is a schematic plan view of the method for fabricating an array substrate according to an embodiment of the present invention after a first patterning process
  • FIG. 5 is a schematic plan view of a method for fabricating an array substrate according to an embodiment of the present invention after a second patterning process
  • FIG. 6 is a schematic plan view of a method for fabricating an array substrate according to an embodiment of the present invention after a third patterning process
  • FIG. 7 is a schematic plan view of an array substrate according to Embodiment 2 of the present invention.
  • Figure 8 is a cross-sectional view taken along line A-A of Figure 7;
  • Figure 9 is a cross-sectional view taken along line B-B of Figure 7.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • Embodiments of the present invention provide an array substrate that can be applied to a liquid crystal display device with high resolution and high refresh rate.
  • the array substrate includes a plurality of sub-pixel units formed on the base substrate. As shown in FIGS. 1, 2, and 3, each of the sub-pixel units includes a thin film transistor 101, a pixel electrode 102, and a common electrode 103.
  • the pixel electrode 102 is located on the first transparent electrode layer and is directly formed on the base substrate 100.
  • the drain electrode 1011 of the thin film transistor 101 is formed on the pixel electrode 102 and is in direct contact with the pixel electrode, and the source 1012 and the drain electrode 1011 of the thin film transistor 101 are both located in the first metal layer.
  • the semiconductor layer 1013 of the thin film transistor 101 is formed on the source 1012 and the drain 1011, and is connected between the source 1012 and the drain 1011.
  • the semiconductor layer 1013 is preferably an amorphous metal oxide semiconductor, and specifically may be a material such as ZnO, InZnO, ZnSnO, GaInZnO, or ZrInZnO.
  • the pixel electrode 102, the source electrode 1012, the drain electrode 1011, and the semiconductor layer 1013 are covered with a gate insulating layer 104, and the gate electrode 1014 of the thin film transistor 101 and the common electrode 103 are formed on the gate insulating layer 104.
  • the gate electrode 1014 is a transparent electrode and is located in the same layer as the common electrode 103, that is, the second transparent electrode layer.
  • the array substrate further includes scan lines and data lines corresponding to each of the sub-pixel units.
  • the data line 110 is located in the same layer as the source 1012 and the drain 1011, that is, the data line 110 is also located in the first metal layer.
  • the scan line includes a first metal line 120 and a connection electrode 105, and a plurality of first metal lines 120 in the same row are connected
  • the electrodes 105 are connected as one scanning line.
  • the first metal line 120 and the data line 110 are located in the same layer, that is, the first metal line 120 is also located in the first metal layer.
  • the connection electrode 105 is located in the same layer as the gate electrode 1014, that is, the connection electrode 105 is also located in the second transparent electrode layer, and the connection electrode 105 and the gate electrode 1014 are connected as a whole.
  • the gate insulating layer 104 is provided with a first via 1061, and the connecting electrode 105 is connected to the first metal line 120 through the first via 1061.
  • the array substrate further includes a common electrode line, and the common electrode line is mainly composed of the second metal line 130.
  • the second metal line 130 is located in the same layer as the data line 110, that is, the second metal line 130 is also located in the first metal layer.
  • the gate insulating layer 104 is provided with a second via 1062, and the common electrode 103 is connected to the second metal line 130 through the second via 1062. Since the common electrodes 103 in the respective sub-pixel units of the same row are in communication with each other, the plurality of second metal lines 130 located in the same row may be connected by the common electrode 103 as one common electrode line. As can be seen from FIG. 1, in order to increase the contact area of the common electrode 103 and the second metal line 130, the shape of the second via 1062 is substantially the same as that of the second metal line 130.
  • the embodiment of the invention further provides a method for manufacturing an array substrate, which can be fabricated by using four patterning processes, and the specific steps are as follows:
  • the first patterning process patterning with a halftone mask to form a pixel electrode, and a source, a drain, a data line, a first metal line, and a second metal line. Specifically include:
  • the first transparent electrode layer may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), and the thickness may be 100 between.
  • the first metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), etc., and the thickness may be 3000 between.
  • the photoresists of the corresponding regions of the source, the drain, the data line, the first metal line and the second metal line are all retained, the photoresist of the corresponding region of the pixel electrode is partially removed, and the photoresist of the remaining regions is completely removed. Remove.
  • S13 etching the first metal layer and the first transparent electrode layer to form a source, a drain, a data line, a first metal line, and a second metal line.
  • Each of the portions formed above is a two-layer structure composed of a first metal layer and a first transparent electrode layer.
  • the shape of the pixel electrode is also formed at this time, but the pixel electrode is still covered with the first metal layer.
  • the photoresist in the corresponding region of the pixel electrode is completely removed by the ashing process.
  • the photoresist of the corresponding regions of the source, the drain, the data line, the first metal line and the second metal line is also partially removed.
  • the pixel electrode is formed by etching away the first metal layer covered on the pixel electrode.
  • the pixel electrode 102, the source 1012, the drain 1011, the data line 110, the first metal line 120, and the second metal line 130 can be formed.
  • the second patterning process patterning is performed using a mask to form a semiconductor layer. Specifically include:
  • an amorphous metal oxide semiconductor film which may be made of ZnO, InZnO, ZnSnO, GaInZnO, ZrInZnO, etc., and the thickness may be 200 between.
  • the semiconductor layer 1013 of the thin film transistor 101 can be formed through the second patterning process described above.
  • the third patterning process patterning with a mask to form a gate insulating layer.
  • the gate insulating layer is provided with a first via hole and a second via hole. Specifically include:
  • a gate insulating layer on the basis of completing the second patterning process, which may be silicon oxide (SiOx), silicon nitride (SiNx) or a mixture of the two, and the thickness may be 2000 between.
  • the photoresist of the corresponding regions of the first via and the second via is removed, and the photoresist of the remaining regions remains.
  • S33 etching the gate insulating layer to form a first via hole and a second via hole of the gate insulating layer.
  • the first via 1061 and the second via 1062 of the gate insulating layer can be formed through the third patterning process described above.
  • the fourth patterning process patterning with a mask to form a gate, a common electrode, and a connection electrode.
  • the connection electrode is connected to the first metal line through the first via hole
  • the common electrode is connected to the second metal line through the second via hole.
  • S43 etching the second transparent electrode layer to form a gate electrode, a common electrode, and a connection electrode. And, the connection electrode is connected to the first metal line through the first via hole, and the common electrode is connected to the second metal line through the second via hole.
  • the array substrate provided by the embodiment of the present invention can be formed through the fourth patterning process.
  • the gate electrode 1014 of the thin film transistor 101 is a transparent electrode, and is located in the same layer as the common electrode 103, so that the gate electrode 1014 and the common electrode 103 can be in the fourth patterning process.
  • Medium synchronization is formed.
  • the pixel electrode 102 in the array substrate and the source 1012 and the drain 1011 of the thin film transistor 101 may be sequentially formed in the first patterning process by using a halftone mask. Therefore, in the technical solution provided by the embodiment of the present invention, the array substrate can be fabricated by four patterning processes, thereby solving the technical problem that the manufacturing process of the existing array substrate is too complicated.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • This embodiment is basically the same as the first embodiment, except that in the embodiment, the second transparent electrode layer is further covered with the second metal layer.
  • the second metal layer can serve as a part of the scan line, increasing the thickness of the scan line, thereby increasing the cross-sectional area of the scan line to reduce the resistance of the scan line.
  • the second metal layer may also serve as a part of the common electrode line, increasing the thickness of the common electrode line, thereby increasing the cross-sectional area of the common electrode line to reduce the resistance of the common electrode line.
  • the second metal layer has both of the above uses.
  • the scan line further includes a third metal line 140 on the second metal layer.
  • the third metal line 140 is formed on the connection electrode 105 and directly above the first metal line 120.
  • the common electrode line further includes a fourth metal line 150 located on the second metal layer, and the fourth metal line 150 is formed on the common electrode 103 and located directly above the second metal line 130.
  • the gate electrode 1014 is also covered with a second metal layer.
  • the method for fabricating the array substrate provided by the embodiment of the present invention also requires only four patterning processes, wherein the first patterning process to the third patterning process are the same as in the first embodiment.
  • the third metal line and the fourth metal line are further formed. Specifically include:
  • S401 sequentially forming a second transparent electrode layer and a second metal layer on the gate insulating layer.
  • the material and thickness of the second transparent electrode layer may be the same as those of the first transparent electrode layer.
  • the material and thickness of the second metal layer may be the same as the first metal layer.
  • S402 Applying a photoresist on the second metal layer and performing exposure using a halftone mask.
  • the photoresist of the gate, the third metal line (the pattern of the connection electrode and the third metal line are the same) and the corresponding region of the fourth metal line are all retained, and the photoresist of the corresponding area of the common electrode is partially removed, and the remaining regions are removed. The photoresist is completely removed.
  • S403 etching the second metal layer and the second transparent electrode layer to form a gate electrode, a connection electrode, and a third metal Line and fourth metal line.
  • the gate is covered with a second metal layer, and the connection electrode is connected to the first metal line through the first via.
  • the third metal line is located directly above the first metal line and the connection electrode, and is the same as the pattern of the connection electrode.
  • the fourth metal line is located directly above the second metal line and coincides with the common electrode portion.
  • the shape of the common electrode is also formed at this time, but the second electrode is still covered on the common electrode.
  • the photoresist in the corresponding region of the common electrode is completely removed by the ashing process.
  • the photoresist of the corresponding regions of the gate, the third metal line and the fourth metal line is also partially removed.
  • S405 etching the second metal layer to form a common electrode.
  • the common electrode is formed by etching away the second metal layer covered on the common electrode.
  • the array substrate provided by the embodiment of the present invention can be formed through the fourth patterning process.
  • the array substrate can be fabricated by four patterning processes, thereby solving the technical problem that the manufacturing process of the existing array substrate is too complicated.
  • the second metal layer is further utilized to increase the thickness of the scan line and the common electrode line, thereby increasing the cross-sectional area of the scan line and the common electrode line. Therefore, compared with the first embodiment, the resistance of the scan line and the common electrode line in the embodiment is lower, and the transmission effect of the electrical signal is better.

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Abstract

一种阵列基板及其制造方法，该阵列基板包括形成于衬底基板（100）上的多个子像素单元，每个子像素单元中包括薄膜晶体管（101）、像素电极（102）和公共电极（103）；薄膜晶体管的源极（1012）、漏极（1011）、半导体层（1013）及像素电极（102）上覆盖有栅极绝缘层（104）；薄膜晶体管的栅极（1014）和公共电极（103）形成于栅极绝缘层（104）上，栅极为透明电极，且与公共电极位于同一图层，解决了现有的制造工艺过于复杂的技术问题。

Description

阵列基板及其制造方法
本申请要求享有2015年6月16日提交的名称为“阵列基板及其制造方法”的中国专利申请CN201510334313.5的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种阵列基板及其制造方法。
背景技术
随着显示技术的发展，液晶显示器已经成为最为常见的显示装置。
平面转换(In-Plane Switching，简称IPS)技术及边缘场开关(Fringe Field Switching，简称FFS)技术均以水平方向的电场驱动液晶，具有宽视角，高亮度，高对比度，快速响应等优点。随着当前液晶显示器的分辨率、刷新率不断提高，每个子像素单元中的薄膜晶体管(Thin Film Transistor，简称TFT)的开启时间也在不断减少。以传统的非晶硅作为薄膜晶体管的有源层，将不能保证子像素单元在短时间内充入足够的电压。
非晶金属氧化物半导体相比于非晶硅半导体，具有更高的迁移率，其迁移率可达到10cm2/V·s以上，因此被广泛应用于高分辨率、高刷新率的显示装置中。但是，目前采用氧化物薄膜晶体管的阵列基板的制造过程中通常需要六次构图工艺，因此现有技术存在制造工艺过于复杂的技术问题。
发明内容
本发明的目的在于提供一种阵列基板及其制造方法，以解决现有的制造工艺过于复杂的技术问题。
本发明提供一种阵列基板，包括形成于衬底基板上的多个子像素单元，每个所述子像素单元中包括薄膜晶体管、像素电极和公共电极；
所述像素电极形成于所述衬底基板上；
所述薄膜晶体管的漏极形成于所述像素电极上，所述薄膜晶体管的源极与所述漏极位于同一图层；
所述薄膜晶体管的半导体层形成于所述源极和所述漏极上；
所述像素电极、所述源极、所述漏极和所述半导体层上覆盖有栅极绝缘层；
所述薄膜晶体管的栅极和所述公共电极形成于所述栅极绝缘层上，其中，所述栅极为透明电极，且与所述公共电极位于同一图层。
优选的是，所述半导体层为氧化物半导体材料。
进一步的是，该阵列基板还包括扫描线和数据线；
所述数据线与所述源极、所述漏极位于同一图层；
所述扫描线包括第一金属线和连接电极；
所述第一金属线与所述数据线位于同一图层，所述连接电极与所述栅极位于同一图层；
所述栅极绝缘层开设有第一过孔，所述连接电极通过所述第一过孔与所述第一金属线相连。
进一步的是，该阵列基板还包括公共电极线，所述公共电极线包括第二金属线，所述第二金属线与所述数据线位于同一图层；
所述栅极绝缘层开设有第二过孔，所述公共电极通过所述第二过孔与所述第二金属线相连。
进一步的是，所述扫描线还包括第三金属线；
所述第三金属线形成于所述连接电极上，且位于所述第一金属线正上方。
进一步的是，所述公共电极线还包括第四金属线；
所述第四金属线形成于所述公共电极上，且位于所述第二金属线正上方。
本发明还提供一种阵列基板的制造方法，包括：
第一次构图工艺：利用半色调掩膜版进行构图，形成像素电极，以及源极、漏极、数据线、第一金属线和第二金属线；
第二次构图工艺：利用掩膜版进行构图，形成半导体层；
第三次构图工艺：利用掩膜版进行构图，形成栅极绝缘层，所述栅极绝缘层开设有第一过孔和第二过孔；
第四次构图工艺：利用掩膜版进行构图，形成栅极、公共电极和连接电极，所述连接电极通过所述第一过孔与所述第一金属线相连，所述公共电极通过所述第二过孔与所述第二金属线相连。
优选的是，所述第一次构图工艺，具体包括：
在衬底基板上依次形成第一透明电极层和第一金属层；
在所述第一金属层上涂敷光刻胶，并利用半色调掩膜版进行曝光；
对所述第一金属层和所述第一透明电极层进行蚀刻，形成源极、漏极、数据线、第一金属线和第二金属线；
对光刻胶进行灰化；
对所述第一金属层进行蚀刻，形成像素电极；
剥离剩余的光刻胶。
进一步的是，在所述第四次构图工艺中，还形成第三金属线和第四金属线；
所述第三金属线形成于所述连接电极上，且位于所述第一金属线正上方；
所述第四金属线形成于所述公共电极上，且位于所述第二金属线正上方。
优选的是，所述第四次构图工艺，具体包括：
在栅极绝缘层上依次形成第二透明电极层和第二金属层；
在所述第二金属层上涂敷光刻胶，并利用半色调掩膜版进行曝光；
对所述第二金属层和所述第二透明电极层进行蚀刻，形成栅极、连接电极、第三金属线和第四金属线；
对光刻胶进行灰化；
对所述第二金属层进行蚀刻，形成公共电极；
剥离剩余的光刻胶。
本发明带来了以下有益效果：本发明提供的阵列基板中，薄膜晶体管的栅极为透明电极，并且与公共电极位于同一图层，使栅极和公共电极可以在同一次构图工艺中同步形成。另外，该阵列基板中的像素电极和薄膜晶体管的源极、漏极也可以利用半色调掩膜版，在同一次构图工艺中依次形成。因此本发明提供的技术方案中，通过四次构图工艺就能够制成阵列基板，从而解决了现有的阵列基板的制造工艺过于复杂的技术问题。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是本发明实施例一提供的阵列基板的平面示意图；
图2是图1中沿A-A线的剖面图；
图3是图1中沿B-B线的剖面图；
图4是本发明实施例提供的阵列基板的制造方法中经第一次构图工艺后的平面示意图；
图5是本发明实施例提供的阵列基板的制造方法中经第二次构图工艺后的平面示意图；
图6是本发明实施例提供的阵列基板的制造方法中经第三次构图工艺后的平面示意图；
图7是本发明实施例二提供的阵列基板的平面示意图；
图8是图7中沿A-A线的剖面图；
图9是图7中沿B-B线的剖面图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一：
本发明实施例提供一种阵列基板，可应用于高分辨率、高刷新率的液晶显示装置。该阵列基板包括形成于衬底基板上的多个子像素单元，如图1、图2和图3所示，每个子像素单元中包括薄膜晶体管101、像素电极102和公共电极103。
像素电极102位于第一透明电极层，直接形成于衬底基板100上。薄膜晶体管101的漏极1011形成于像素电极102上，且与像素电极直接接触，薄膜晶体管101的源极1012和漏极1011均位于第一金属层。
薄膜晶体管101的半导体层1013形成于源极1012和漏极1011上，并连接在源极1012与漏极1011之间。本实施例中，半导体层1013优选为非晶金属氧化物半导体，具体可以是ZnO、InZnO、ZnSnO、GaInZnO、ZrInZnO等材料。
像素电极102、源极1012、漏极1011和半导体层1013上覆盖有栅极绝缘层104，薄膜晶体管101的栅极1014和公共电极103形成于栅极绝缘层104上。其中，栅极1014为透明电极，且与公共电极103位于同一图层，即第二透明电极层。
该阵列基板还包括与每个子像素单元相对应的扫描线和数据线。
数据线110与源极1012、漏极1011位于同一图层，即数据线110也位于第一金属层。
扫描线包括第一金属线120和连接电极105，位于同一行的多个第一金属线120由连 接电极105连接为一条扫描线。第一金属线120与数据线110位于同一图层，即第一金属线120也位于第一金属层。连接电极105与栅极1014位于同一图层，即连接电极105也位于第二透明电极层，并且连接电极105和栅极1014连接为一个整体。栅极绝缘层104开设有第一过孔1061，连接电极105通过第一过孔1061与第一金属线120相连。
该阵列基板还包括公共电极线，公共电极线主要由第二金属线130构成。第二金属线130与数据线110位于同一图层，即第二金属线130也位于第一金属层。
栅极绝缘层104开设有第二过孔1062，公共电极103通过第二过孔1062与第二金属线130相连。因为同一行的各个子像素单元中的公共电极103是互相连通的，所以位于同一行的多个第二金属线130可以由公共电极103连接为一条公共电极线。从图1中可以看出，为增加公共电极103与第二金属线130的接触面积，第二过孔1062的形状基本与第二金属线130相同。
本发明实施例还相应的提供一种阵列基板的制造方法，可通过四次构图工艺制成上述阵列基板，具体步骤如下：
第一次构图工艺：利用半色调掩膜版进行构图，形成像素电极，以及源极、漏极、数据线、第一金属线和第二金属线。具体包括：
S11：在衬底基板上依次形成第一透明电极层和第一金属层。
其中，第一透明电极层可采用氧化铟锡(ITO)或氧化铟锌(IZO)等材料，厚度可以在100至
Figure PCTCN2015087493-appb-000001
之间。第一金属层可采用铬(Cr)、钼(Mo)、铝(Al)、铜(Cu)等材料，厚度可以在3000至
Figure PCTCN2015087493-appb-000002
之间。
S12：在第一金属层上涂敷光刻胶，并利用半色调掩膜版进行曝光。
曝光后，源极、漏极、数据线、第一金属线和第二金属线对应区域的光刻胶全部保留，像素电极对应区域的光刻胶被部分去除，其余区域的光刻胶被全部去除。
S13：对第一金属层和第一透明电极层进行蚀刻，形成源极、漏极、数据线、第一金属线和第二金属线。
以上形成的各个部分均为第一金属层和第一透明电极层组成的双层结构。另外，此时像素电极的形状也已形成，但像素电极上仍覆盖有第一金属层。
S14：对光刻胶进行灰化。
利用灰化工艺，将像素电极对应区域的光刻胶全部去除。同时，源极、漏极、数据线、第一金属线和第二金属线对应区域的光刻胶也会被部分去除。
S15：对第一金属层进行蚀刻，形成像素电极。
将像素电极上覆盖的第一金属层蚀刻掉，即可形成像素电极。
S16：剥离剩余的光刻胶。
如图4所示，经过上述第一次构图工艺，即可形成像素电极102、源极1012、漏极1011、数据线110、第一金属线120和第二金属线130。
第二次构图工艺：利用掩膜版进行构图，形成半导体层。具体包括：
S21：在完成第一次构图工艺的基础上，沉积一层非晶金属氧化物半导体薄膜，可以采用ZnO、InZnO、ZnSnO、GaInZnO、ZrInZnO等材料，厚度可以在200至
Figure PCTCN2015087493-appb-000003
之间。
S22：在半导体薄膜上涂敷光刻胶，并利用掩膜版进行曝光。
曝光后，仅保留薄膜晶体管的半导体层对应区域的光刻胶，其余区域的光刻胶被去除。
S23：对半导体薄膜进行蚀刻，形成薄膜晶体管的半导体层。
S24：剥离剩余的光刻胶。
如图5所示，经过上述第二次构图工艺，即可形成薄膜晶体管101的半导体层1013。
第三次构图工艺：利用掩膜版进行构图，形成栅极绝缘层。其中，栅极绝缘层开设有第一过孔和第二过孔。具体包括：
S31：在完成第二次构图工艺的基础上，形成一层栅极绝缘层，可以采用氧化硅(SiOx)、氮化硅(SiNx)或二者的混合物，厚度可以在2000至
Figure PCTCN2015087493-appb-000004
之间。
S32：在栅极绝缘层上涂敷光刻胶，并利用掩膜版进行曝光。
曝光后，去除第一过孔和第二过孔对应区域的光刻胶，其余区域的光刻胶保留。
S33：对栅极绝缘层进行蚀刻，形成栅极绝缘层的第一过孔和第二过孔。
S34：剥离剩余的光刻胶。
如图6所示，经过上述第三次构图工艺，即可形成栅极绝缘层的第一过孔1061和第二过孔1062。
第四次构图工艺：利用掩膜版进行构图，形成栅极、公共电极和连接电极。其中，连接电极通过第一过孔与第一金属线相连，公共电极通过第二过孔与第二金属线相连。具体包括：
S41：在完成第三次构图工艺的基础上，形成第二透明电极层，其材料、厚度可以与第一透明电极层相同。
S42：在第二透明电极层上涂敷光刻胶，并利用掩膜版进行曝光。
曝光后，仅保留栅极、公共电极和连接电极对应区域的光刻胶，其余区域的光刻胶被去除。
S43：对第二透明电极层进行蚀刻，形成栅极、公共电极和连接电极。并且，连接电极通过第一过孔与第一金属线相连，公共电极通过第二过孔与第二金属线相连。
S44：剥离剩余的光刻胶。
如图1所示，经过上述第四次构图工艺，即可形成本发明实施例提供的阵列基板。
本发明实施例提供的阵列基板及其制造方法中，薄膜晶体管101的栅极1014为透明电极，并且与公共电极103位于同一图层，使栅极1014和公共电极103可以在第四次构图工艺中同步形成。另外，该阵列基板中的像素电极102和薄膜晶体管101的源极1012、漏极1011也可以利用半色调掩膜版，在第一次构图工艺中依次形成。因此本发明实施例提供的技术方案中，通过四次构图工艺就能够制成阵列基板，从而解决了现有的阵列基板的制造工艺过于复杂的技术问题。
实施例二：
本实施例与实施例一基本相同，其不同点在于，本实施例中，在第二透明电极层上还覆盖有第二金属层。该第二金属层可以作为扫描线的一部分，增加扫描线的厚度，进而增加扫描线的横截面积，以降低扫描线的电阻。或者，该第二金属层也可以作为公共电极线的一部分，增加公共电极线的厚度，进而增加公共电极线的横截面积，以降低公共电极线的电阻。
本实施例中，第二金属层同时兼具上述两种用途。如图7、图8和图9所示，扫描线还包括位于第二金属层的第三金属线140，第三金属线140形成于连接电极105上，且位于第一金属线120正上方。同时，公共电极线还包括位于第二金属层的第四金属线150，第四金属线150形成于公共电极103上，且位于第二金属线130正上方。另外，本实施例中，栅极1014上方也覆盖有第二金属层。
本发明实施例提供的阵列基板的制造方法也只需四次构图工艺，其中第一次构图工艺至第三次构图工艺与实施例一相同。
本实施例提供的阵列基板的制造方法，在第四次构图工艺中，还形成第三金属线和第四金属线。具体包括：
S401：在栅极绝缘层上依次形成第二透明电极层和第二金属层。
第二透明电极层的材料、厚度可以与第一透明电极层相同。第二金属层的材料、厚度可以与第一金属层相同。
S402：在第二金属层上涂敷光刻胶，并利用半色调掩膜版进行曝光。
曝光后，栅极、第三金属线(连接电极与第三金属线的图案相同)和第四金属线对应区域的光刻胶全部保留，公共电极对应区域的光刻胶被部分去除，其余区域的光刻胶被全部去除。
S403：对第二金属层和第二透明电极层进行蚀刻，形成栅极、连接电极、第三金属 线和第四金属线。
其中，栅极上方覆盖有第二金属层，连接电极通过第一过孔与第一金属线相连。第三金属线位于第一金属线、连接电极的正上方，并且与连接电极的图案相同。第四金属线位于第二金属线的正上方，并且与公共电极部分重合。另外，此时公共电极的形状也已形成，但公共电极上仍覆盖有第二金属层。
S404：对光刻胶进行灰化。
利用灰化工艺，将公共电极对应区域的光刻胶全部去除。同时，栅极、第三金属线和第四金属线对应区域的光刻胶也会被部分去除。
S405：对第二金属层进行蚀刻，形成公共电极。
将公共电极上覆盖的第二金属层蚀刻掉，即可形成公共电极。
S406：剥离剩余的光刻胶。
如图7所示，经过上述第四次构图工艺，即可形成本发明实施例提供的阵列基板。
本发明实施例提供的阵列基板及其制造方法中，通过四次构图工艺就能够制成阵列基板，从而解决了现有的阵列基板的制造工艺过于复杂的技术问题。此外，本实施例中还利用第二金属层，增加了扫描线和公共电极线的厚度，进而增加了扫描线和公共电极线的横截面积。因此，相比于实施例一，本实施例中扫描线和公共电极线的电阻更低，其电信号的传输效果更好。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括形成于衬底基板上的多个子像素单元，每个所述子像素单元中包括薄膜晶体管、像素电极和公共电极；
    所述像素电极形成于所述衬底基板上；
    所述薄膜晶体管的漏极形成于所述像素电极上，所述薄膜晶体管的源极与所述漏极位于同一图层；
    所述薄膜晶体管的半导体层形成于所述源极和所述漏极上；
    所述像素电极、所述源极、所述漏极和所述半导体层上覆盖有栅极绝缘层；
    所述薄膜晶体管的栅极和所述公共电极形成于所述栅极绝缘层上，其中，所述栅极为透明电极，且与所述公共电极位于同一图层。
  2. 根据权利要求1所述的阵列基板，其中，所述半导体层为氧化物半导体材料。
  3. 根据权利要求2所述的阵列基板，其中，所述氧化物半导体材料具体为ZnO、InZnO、ZnSnO、GaInZnO或ZrInZnO。
  4. 根据权利要求1所述的阵列基板，其中，所述半导体层的厚度在200至
    Figure PCTCN2015087493-appb-100001
    之间。
  5. 根据权利要求1所述的阵列基板，其中，所述像素电极的材料为氧化铟锡或氧化铟锌。
  6. 根据权利要求1所述的阵列基板，其中，栅极绝缘层的材料为氧化硅和氮化硅中的至少一种。
  7. 根据权利要求1所述的阵列基板，其中，还包括扫描线和数据线；
    所述数据线与所述源极、所述漏极位于同一图层；
    所述扫描线包括第一金属线和连接电极；
    所述第一金属线与所述数据线位于同一图层，所述连接电极与所述栅极位于同一图层；
    所述栅极绝缘层开设有第一过孔，所述连接电极通过所述第一过孔与所述第一金属线相连。
  8. 根据权利要求7所述的阵列基板，其中，还包括公共电极线，所述公共电极线包括第二金属线，所述第二金属线与所述数据线位于同一图层；
    所述栅极绝缘层开设有第二过孔，所述公共电极通过所述第二过孔与所述第二金属线相连。
  9. 根据权利要求8所述的阵列基板，其中，所述数据线、所述第一金属线和所述第 二金属线的材料为铬、钼、铝或铜。
  10. 根据权利要求8所述的阵列基板，其中，所述扫描线还包括第三金属线；
    所述第三金属线形成于所述连接电极上，且位于所述第一金属线正上方。
  11. 根据权利要求8所述的阵列基板，其中，所述公共电极线还包括第四金属线；
    所述第四金属线形成于所述公共电极上，且位于所述第二金属线正上方。
  12. 一种阵列基板的制造方法，包括：
    第一次构图工艺：利用半色调掩膜版进行构图，形成像素电极，以及源极、漏极、数据线、第一金属线和第二金属线；
    第二次构图工艺：利用掩膜版进行构图，形成半导体层；
    第三次构图工艺：利用掩膜版进行构图，形成栅极绝缘层，所述栅极绝缘层开设有第一过孔和第二过孔；
    第四次构图工艺：利用掩膜版进行构图，形成栅极、公共电极和连接电极，所述连接电极通过所述第一过孔与所述第一金属线相连，所述公共电极通过所述第二过孔与所述第二金属线相连。
  13. 根据权利要求12所述的方法，其中，所述半导体层为氧化物半导体材料。
  14. 根据权利要求13所述的方法，其中，所述氧化物半导体材料具体为ZnO、InZnO、ZnSnO、GaInZnO或ZrInZnO。
  15. 根据权利要求12所述的方法，其中，所述半导体层的厚度在200至
    Figure PCTCN2015087493-appb-100002
    之间。
  16. 根据权利要求12所述的方法，其中，所述像素电极的材料为氧化铟锡或氧化铟锌。
  17. 根据权利要求12所述的方法，其中，栅极绝缘层的材料为氧化硅和氮化硅中的至少一种。
  18. 根据权利要求12所述的方法，其中，所述第一次构图工艺，具体包括：
    在衬底基板上依次形成第一透明电极层和第一金属层；
    在所述第一金属层上涂敷光刻胶，并利用半色调掩膜版进行曝光；
    对所述第一金属层和所述第一透明电极层进行蚀刻，形成源极、漏极、数据线、第一金属线和第二金属线；
    对光刻胶进行灰化；
    对所述第一金属层进行蚀刻，形成像素电极；
    剥离剩余的光刻胶。
  19. 根据权利要求12所述的方法，其中，在所述第四次构图工艺中，还形成第三金 属线和第四金属线；
    所述第三金属线形成于所述连接电极上，且位于所述第一金属线正上方；
    所述第四金属线形成于所述公共电极上，且位于所述第二金属线正上方。
  20. 根据权利要求19所述的方法，其中，所述第四次构图工艺，具体包括：
    在栅极绝缘层上依次形成第二透明电极层和第二金属层；
    在所述第二金属层上涂敷光刻胶，并利用半色调掩膜版进行曝光；
    对所述第二金属层和所述第二透明电极层进行蚀刻，形成栅极、连接电极、第三金属线和第四金属线；
    对光刻胶进行灰化；
    对所述第二金属层进行蚀刻，形成公共电极；
    剥离剩余的光刻胶。
PCT/CN2015/087493 2015-06-16 2015-08-19 阵列基板及其制造方法 WO2016201778A1 (zh)

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CN106711159B (zh) * 2017-03-28 2019-09-03 上海天马微电子有限公司 阵列基板和阵列基板的制作方法
CN107170764B (zh) * 2017-07-26 2020-06-05 上海天马微电子有限公司 阵列基板、阵列基板的制造方法、显示面板和显示装置
CN113658912B (zh) * 2021-07-09 2024-04-16 深圳莱宝高科技股份有限公司 阵列基板制造方法、阵列基板、电子纸器件及其制造方法
CN113658913B (zh) * 2021-07-09 2024-05-31 深圳莱宝高科技股份有限公司 阵列基板制造方法、阵列基板、电子纸器件及其制造方法
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