WO2013127200A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2013127200A1
WO2013127200A1 PCT/CN2012/084849 CN2012084849W WO2013127200A1 WO 2013127200 A1 WO2013127200 A1 WO 2013127200A1 CN 2012084849 W CN2012084849 W CN 2012084849W WO 2013127200 A1 WO2013127200 A1 WO 2013127200A1
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Prior art keywords
gate
layer
electrode
thin film
pattern
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PCT/CN2012/084849
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English (en)
French (fr)
Inventor
张学辉
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京东方科技集团股份有限公司
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Priority to US13/824,605 priority Critical patent/US9905787B2/en
Publication of WO2013127200A1 publication Critical patent/WO2013127200A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Transistors are used as switching devices and driving devices for controlling and driving flat panel displays such as liquid crystal displays, electroluminescent displays, and the like.
  • flat panel displays such as liquid crystal displays, electroluminescent displays, and the like.
  • thin film transistors having a bottom gate bottom contact configuration and a bottom gate top contact configuration are widely used in an array substrate of a liquid crystal display.
  • the gate 1 of the thin film transistor of the bottom gate bottom contact configuration is prepared on the substrate 3.
  • the upper surface of the gate 1 is the gate insulating layer 4, and the source and drain electrodes 2 are on the gate insulating layer 4 and the semiconductor film. Between 5.
  • the boundary of the source-drain electrodes 2 of such a structure affects the deposition of the semiconductor thin film 5, so that the order of molecular alignment of the semiconductor thin film 5 is lowered, thereby affecting the transport of carriers, thereby degrading the performance of the device and affecting the quality of the array substrate.
  • the gate electrode 1 of the thin film transistor of the bottom gate top contact configuration is also prepared on the substrate 3.
  • the upper surface of the gate electrode 1 is a gate insulating layer 4, and the semiconductor film 5 is prepared on the gate insulating layer 4.
  • Upper, the long metal electrode is regenerated on the semiconductor film 5 to form the source/drain electrode 2.
  • the fabrication process of the source-drain electrode 2 of this structure is greatly limited. When the source-drain electrode 2 is prepared, damage to the organic semiconductor film that has been arranged in order is generally caused by thermal evaporation, which is difficult to produce. .
  • the existing array substrate of the thin film transistor with the bottom gate bottom contact configuration and the bottom gate top contact configuration requires multiple photolithography masks in the preparation process, and the preparation process is cumbersome and the production cost is high. Summary of the invention
  • Embodiments of the present invention provide an array substrate and a method of fabricating the same, in which a thin film transistor with a top gate bottom contact configuration is used in the array substrate, which reduces the difficulty of production of the array substrate and improves the quality of the array substrate. Moreover, the array substrate is simplified. Manufacturing process reduces production costs.
  • An embodiment of the present invention provides an array substrate, including: a substrate, and a gate line, a data line, a thin film transistor, and a pixel electrode on the substrate, wherein the thin film transistor is a thin film transistor having a top gate bottom contact configuration, a gate of the top gate bottom contact configuration thin film transistor is connected to the gate line, A source is connected to the data line, and a drain is connected to the pixel electrode.
  • the drain of the thin film transistor is composed of upper and lower electrodes, and the lower electrode and the pixel electrode are integrated.
  • the source electrode and the drain electrode of the thin film transistor of the top gate bottom contact configuration are composed of upper and lower electrodes, and the semiconductor of the thin film transistor in which the lower electrode and the top gate are in contact with each other One end of the layer contact is slightly longer than the upper layer electrode.
  • the data lines include two layers of upper and lower conductive materials, which are respectively the same as those of the source and drain electrodes and the pixel electrodes of the thin film transistor of the top gate bottom contact configuration.
  • the thin film transistor of the top gate bottom contact configuration is an organic thin film transistor of a top gate bottom contact configuration.
  • Embodiments of the present invention provide a method for fabricating an array substrate, including:
  • a pattern including a source/drain electrode, a pixel electrode, and a data line on the substrate by a first patterning process
  • a pattern including a semiconductor layer, a gate insulating layer, a gate, and a gate line on the substrate on which the first patterning process is completed by a second patterning process;
  • a pattern including a passivation layer and a passivation layer via hole is formed on the substrate on which the second patterning process is completed by a third patterning process.
  • the pattern including the source/drain electrodes, the pixel electrodes, and the data lines formed on the substrate by the first patterning process includes:
  • the pattern forming the semiconductor layer, the gate insulating layer, the gate, and the gate line on the substrate on which the first patterning process is completed by the second patterning process includes: Forming a semiconductor material layer, an insulating material layer, and a metal material layer on the substrate on which the first patterning process is completed;
  • the semiconductor material layer is an organic semiconductor material.
  • Embodiments of the present invention provide a display device including the array substrate as described above.
  • FIG. 1 is a schematic view of a thin film transistor of a bottom gate bottom contact configuration in the prior art
  • FIG. 2 is a schematic view of a thin film transistor of a bottom gate top contact configuration in the prior art
  • FIG. 3 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic plan view of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic view showing deposition of a conductive material in an embodiment of the present invention
  • 7 is a schematic view showing exposure and development using a halftone mask in an embodiment of the present invention
  • FIG. 8 is a schematic view showing etching of a conductive material in an embodiment of the present invention
  • FIG. 9 is a schematic view of an ashing photoresist in an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of forming an upper layer pattern of a source/drain electrode according to an embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional view showing a source/drain electrode layer formed in an embodiment of the present invention.
  • FIG. 12 is a schematic plan view showing a source/drain electrode layer formed in an embodiment of the present invention.
  • FIG. 13 is a schematic view showing deposition of a material on a source/drain electrode layer in an embodiment of the present invention.
  • FIG. 14 is a schematic diagram of an etching process according to an embodiment of the present invention.
  • Figure 15 is a schematic view showing the removal of the remaining photoresist in the embodiment of the present invention.
  • 16 is a schematic cross-sectional view showing a passivation layer formed in an embodiment of the present invention.
  • Figure 17 is a schematic plan view showing the formation of a passivation layer in an embodiment of the present invention.
  • Pixel electrode 15 semiconductor material 16, insulating material
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining a plurality of pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element And a pixel electrode for controlling the arrangement of the liquid crystals.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • Embodiments of the present invention provide an array substrate.
  • the array substrate includes: a substrate 11, and a gate line 130, a data line 110, a thin film transistor and a pixel electrode 19 on the substrate 11, and the thin film transistor is a top-gate bottom contact structure film.
  • the transistor 14, the gate of the thin film transistor 14 of the top gate bottom contact configuration (ie, the gate electrode pattern 57) is connected to the gate line 130, the source 39 is connected to the data line 110, and the drain 40 is The pixel electrodes 19 are connected.
  • the drain electrode 40 of the thin film transistor is composed of upper and lower electrodes, and the lower electrode and the pixel electrode 19 are integrated. This structure can achieve better electrical contact between the drain electrode 40 and the pixel electrode 19. Of course, the two may not be an integrated structure, and will not be described here.
  • the source electrode 39 and the drain electrode 40 of the thin film transistor of the top gate bottom contact configuration are composed of upper and lower electrodes, and the lower electrode and the top gate are in contact with the semiconductor of the thin film transistor.
  • One end of the layer 55 contact is slightly longer than the upper layer electrode so as to be in direct contact with the semiconductor layer 55.
  • the source electrode 39 is composed of upper and lower electrodes, and the lower electrode (ie, the source electrode underlayer pattern 36)
  • the end portion in contact with the semiconductor layer 55 is slightly longer than the portion of the upper layer electrode (i.e., the source electrode upper layer pattern 33) so as to be in direct contact with the semiconductor layer 55.
  • the extended region is for making the source-drain electrode pattern of the top-gate contact-structured organic thin film transistor sufficiently in contact with the semiconductor layer pattern of the top-gate contact-structured organic thin film transistor, and thus The technique increases the contact area between the semiconductor layer and the source and drain electrodes in the thin film transistor, and can also adjust the size of the area according to actual needs to achieve different performance effects.
  • the data line 110 includes two layers of conductive materials, which are respectively the same material as the source and drain electrodes of the thin film transistor and the pixel electrode 19 of the top gate bottom contact configuration, and thus the data line
  • the source and drain electrodes and the pixel electrode of the thin film transistor may be formed together in one patterning process.
  • the gate line 130 retains the material of the semiconductor layer 55 and the material of the gate insulating layer 56, so the gate line 130 can be formed together with the semiconductor layer 55, the gate insulating layer 56, and the gate electrode 57 of the above-described thin film transistor in one patterning process. .
  • the organic thin film transistor 14, the pixel electrode 19, the gate line 130, and the data line 110 in the top gate bottom contact configuration are covered with a passivation layer 18, and the gate signal 130 and the external signal region of the data line 110 (ie, The gate line PAD area 120 and the data line PAD area) are covered without a passivation layer.
  • the top gate bottom contact configuration thin film transistor 14 is an organic thin film transistor of a top gate bottom contact configuration, that is, the active layer is not using, for example, a silicon semiconductor (eg, amorphous silicon, polysilicon, etc.) or an oxide semiconductor. (for example, IGZO, etc.), but formed using an organic semiconductor material (for example, phthalocyanine or the like).
  • a silicon semiconductor eg, amorphous silicon, polysilicon, etc.
  • oxide semiconductor for example, IGZO, etc.
  • organic semiconductor material for example, phthalocyanine or the like
  • a common electrode line (not shown) may be further included, and the common electrode line may be disposed in the same layer as the data line, or may be disposed in the same layer as the gate line.
  • the common electrode line may also include the above two upper and lower conductive materials, which can reduce the resistance of the common electrode line and improve the signal transmission capability of the common electrode line.
  • the common electrode line is used to form a storage capacitor in the TN (Twisted Nematic) type, and is in the ADS (ADvanced Super Dimension Switch) or FFS (Fringe Field Switching) structure. Medium is mainly used to conduct common voltage.
  • the array substrate provided by the embodiment of the invention uses a thin film transistor with a top gate bottom contact configuration, which facilitates the order growth of the semiconductor film on the drain-source electrode of the thin film transistor and the channel region, and reduces the production difficulty of the array substrate;
  • the thin film transistor of the top gate bottom contact configuration the source-drain electrode structure of the two-layer electrode is used to increase the contact area between the source/drain electrode and the semiconductor layer, and the top gate bottom connection is improved.
  • the performance of the touch-type thin film transistor improves the performance of the array substrate.
  • the embodiment of the invention provides a method for manufacturing an array substrate. As shown in FIG. 5, the method includes the following steps.
  • the source and drain electrodes of the thin film transistor of the top gate bottom contact configuration and the pixel electrode and the data line of the array substrate are formed in the first patterning process, and in the second patterning
  • the gate line of the array substrate and the semiconductor layer, the gate insulating layer and the gate of the thin film transistor are formed in the process, and finally the passivation layer is formed by a patterning process, and the fabrication of the array substrate is completed using only three patterning processes, compared with the prior art.
  • the manufacturing method reduces the use frequency of the patterning process while ensuring the performance of the array substrate, thereby reducing the damage of the semiconductor film by the patterning process, and at the same time simplifying the process steps and reducing the production cost.
  • an example of forming a pattern including a source/drain electrode, a pixel electrode, and a data line on the substrate by the first patterning process is as follows.
  • a transparent conductive material 12 and a metal material 13 are sequentially formed on the substrate 11.
  • a transparent conductive film and a metal film are sequentially sputtered on the glass substrate.
  • the transparent conductive film is formed, for example, using indium tin oxide (ITO); the metal film can be formed using a single layer film or a composite film of a conductive material such as aluminum, aluminum alloy, or copper.
  • the photoresist 21 is exposed and developed with a halftone or gray tone mask to form a fully-retained region 211, a partially-retained region 212, and a completely removed region 213.
  • the photoresist in the fully-retained region 211 is substantially retained after development, and a source-drain electrode pattern and a data line pattern for forming an organic thin film transistor of the top-gate bottom contact configuration; the partial retention region 212
  • the photoresist in the portion is partially retained after development, for forming the pixel electrode pattern and half The conductor contact region; the photoresist in the completely removed region 213 is substantially removed after development.
  • the semiconductor contact region is configured to sufficiently contact a source drain electrode pattern of the top gate bottom contact configuration organic thin film transistor with a semiconductor layer pattern of the top gate bottom contact configuration organic thin film transistor.
  • the transparent conductive material 12 and the metal material 13 of the completely removed region 213 are removed by an etching process to form a pixel electrode pattern 38, a data line pattern 110, and used to form the source.
  • the underlying (ie, lower) pattern of the source and drain electrodes of the electrode and drain electrode patterns that is, the source electrode underlayer pattern 36 and the drain electrode underlayer pattern 37, the data line layer pattern 110b and the data line under layer pattern 110a collectively form the data line pattern 110. .
  • the data line 110 includes two layers of upper and lower conductive materials, and the two layers of the conductive material are respectively connected to the top gate bottom of the thin film transistor source and drain electrodes and pixels.
  • the material of the electrode 19 is the same, and this structure does not affect the transmission performance of the data line.
  • the photoresist 21 except for the portion of the remaining region is removed by an ashing process while the photoresist in the photoresist completely remaining region 22 is thinned.
  • the metal material of the portion of the remaining region 212 is removed by an etching process to expose the pixel electrode 19, and the upper layer pattern of the source electrode and the drain electrode is formed, that is, the source electrode upper layer pattern 33 and the drain electrode upper layer pattern. 34.
  • the source electrode and the drain electrode upper layer pattern and the source/drain electrode bottom layer pattern together form a source/drain electrode pattern of the top gate bottom contact configuration thin film transistor, that is, the source electrode upper layer pattern 33 and the source electrode bottom layer pattern 36 form a thin film.
  • the source electrode pattern of the transistor, that is, the drain electrode upper layer pattern 34 and the drain electrode underlayer pattern 37 form a drain electrode pattern of the thin film transistor; wherein the lower layer electrode of the drain electrode and the pixel electrode are integrated.
  • the source electrode underlayer pattern 36 is longer than the source electrode upper layer pattern 33-portion, and the grown portion is a semiconductor contact region for the organic film of the top gate bottom contact configuration.
  • the source electrode pattern of the transistor is in sufficient contact with the semiconductor layer pattern of the organic thin film transistor of the top gate bottom contact configuration, and the contact area of the semiconductor layer and the source/drain electrode in the thin film transistor is increased relative to the prior art, and Need to adjust the size of the area to increase production flexibility.
  • the remaining photoresist is removed, and the source/drain electrode layer, that is, the source 39, the drain 40, and the pixel electrode of the organic thin film transistor having the top gate bottom contact configuration formed on the substrate.
  • the pattern 38 and the data line 110, and Fig. 12 is a plan view of the array substrate (one pixel unit).
  • the first time is completed by the second patterning process
  • a pattern including a semiconductor layer, a gate insulating layer, a gate electrode, and a gate line on a substrate of a patterning process is as follows.
  • a semiconductor material layer 15, an insulating material layer 16, and a gate metal material layer 17 are sequentially formed (e.g., deposited, sputtered, etc.) on the source/drain electrode layer.
  • the semiconductor material layer 15 is formed, for example, using an amorphous silicon or an oxide semiconductor material;
  • the insulating material layer 16 is formed using, for example, silicon oxide, silicon nitride, or silicon oxynitride;
  • the gate metal material layer 17 is made of, for example, aluminum, aluminum alloy, or copper.
  • a single layer film or a composite film of a conductive material is formed.
  • a layer of photoresist is coated on the gate metal material layer 17. Exposing and developing the photoresist to form a photoresist retention region 22 and a removal region, the retention region 22 corresponding to an area for forming a pattern including a semiconductor layer, a gate insulating layer, a gate, and a gate line .
  • the material and the metal material form a pattern of the semiconductor layer pattern 55, the gate insulating layer pattern 56, and the gate pattern 57 of the thin film transistor including the gate line pattern 130 and the top gate bottom contact configuration.
  • the gate line 130 is formed together with the semiconductor layer 55, the gate insulating layer 56, and the gate electrode 57 of the thin film transistor in one patterning process, the gate line 130 is composed of three layers of materials.
  • the three-layer material is the same as the material of the semiconductor layer 55 of the organic thin film transistor 14 in the top gate bottom contact configuration, the material of the gate insulating layer 56, and the material of the gate electrode 57. This structure does not affect the transmission performance of the gate line. , no further processing is required.
  • the remaining photoresist is removed to form a gate electrode layer, that is, a source electrode 39, a drain electrode 40, a semiconductor layer 55, a gate insulating layer 56, and a gate electrode of a thin film transistor having a top gate bottom contact configuration. 57, and the gate line 130 and the data line 110 of the array substrate.
  • a passivation layer 18 and a passivation layer via hole are formed on the gate electrode layer by a third patterning process.
  • a passivation layer material is deposited on the source/drain electrode layer formed as described above, and the passivation layer is formed, for example, of silicon oxide, silicon nitride, silicon oxynitride or an organic insulating material. Then, a layer of photoresist is applied, exposed, developed using a mask, and then etched to form a passivation layer 18.
  • the external signal region 120 (gate line PAD region) of the gate line 130 and the external signal region (data line PAD region) of the data line 110 do not cover the passivation layer 18 (i.e., passivation layer via holes are formed). This completes the fabrication of the array substrate.
  • the method for fabricating the array substrate provided by the embodiment of the present invention, by using a gray tone or halftone mask, creatively forms a thin film transistor of a top gate bottom contact configuration in the first patterning process.
  • a source/drain electrode and a pixel electrode and a data line of the array substrate, the source and drain electrodes are divided into two layers, and the bottom layer is long from the upper layer, so that the source/drain electrode pattern and the top gate bottom are in contact with the semiconductor layer of the organic thin film transistor.
  • the pattern contact area is increased, and the gate line of the array substrate and the semiconductor layer, the gate insulating layer and the gate of the thin film transistor are formed in the second patterning process, and finally the passivation layer is formed by a patterning process, and only three patterning processes are used.
  • the fabrication of the array substrate is completed, and the manufacturing method of the prior art reduces the number of times of the patterning process while ensuring the performance of the array substrate, thereby reducing the damage of the semiconductor film by the patterning process, and at the same time simplifying the process steps and reducing the process steps. Cost of production.
  • Embodiments of the present invention also provide a display device using the above array substrate.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any display product or component.

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Abstract

本发明提供一种阵列基板及其制造方法和显示装置，可降低阵列基板生产难度，简化了阵列基板的制造工艺，降低了生产成本。该阵列基板包括：位于基板上的顶栅底接触构型的薄膜晶体管，薄膜晶体管的栅极与栅线连接，源极与数据线连接，漏极与像素电极连接。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制造方法和显示装置。 背景技术
晶体管作为开关器件与驱动器件用于控制与驱动平板显示器， 例如液晶 显示器、 场致发光显示器等。 目前， 在液晶显示器的阵列基板中被广泛应用 的是底栅底接触构型和底栅顶接触构型的薄膜晶体管。
如图 1所示， 底栅底接触构型的薄膜晶体管的栅极 1制备在基板 3上， 栅极 1的上面是栅极绝缘层 4, 源漏电极 2在栅极绝缘层 4与半导体薄膜 5 之间。 这种结构的源漏电极 2的边界会影响半导体薄膜 5的沉积， 使得半导 体薄膜 5的分子排列有序度降低， 从而影响其载流子的传输， 使器件性能降 低， 进而影响阵列基板质量。
如图 2所示， 底栅顶接触构型的薄膜晶体管的栅极 1也同样制备在基板 3上，栅极 1的上面是栅极绝缘层 4,半导体薄膜 5制备在栅极绝缘层 4之上， 在半导体薄膜 5上再生长金属电极形成源漏电极 2。 这种结构的源漏电极 2 的制作工艺受到很大的限制， 制备源漏电极 2时会对已经排列有序的有机半 导体薄膜造成损伤， 一般只能通过热蒸发的方式形成， 生产难度较高。
现有的釆用底栅底接触构型和底栅顶接触构型的薄膜晶体管的阵列基板 在制备过程中需要进行多次光刻掩膜， 制备过程繁瑣， 生产成本较高。 发明内容
本发明的实施例提供了一种阵列基板及其制造方法， 在阵列基板中釆用 顶栅底接触构型的薄膜晶体管，降低阵列基板生产难度，提高阵列基板质量； 而且， 简化了阵列基板的制造工艺， 降低了生产成本。
本发明实施例提供一种阵列基板， 包括： 基板， 以及位于所述基板上的 栅线、 数据线、 薄膜晶体管和像素电极， 所述薄膜晶体管为顶栅底接触构型 的薄膜晶体管， 所述顶栅底接触构型的薄膜晶体管的栅极与所述栅线连接， 源极与所述数据线连接， 漏极与所述像素电极连接。
在阵列基板之中， 例如， 所述薄膜晶体管的漏极由上下两层电极组成， 下层电极与所述像素电极为一体结构。
在阵列基板之中， 例如， 所述顶栅底接触构型的薄膜晶体管的源电极和 漏电极都由上下两层电极组成， 且所述下层电极与顶栅底接触构型的薄膜晶 体管的半导体层接触的一端略长出于所述上层电极。
在阵列基板之中， 例如， 所述数据线包括上下两层导电材料， 所述两层 导电材料分别和所述顶栅底接触构型的薄膜晶体管的源漏电极和像素电极的 材料相同。
在阵列基板之中， 例如， 所述顶栅底接触构型的薄膜晶体管为顶栅底接 触构型的有机薄膜晶体管。
本发明实施例提供一种阵列基板的制造方法， 包括：
通过第一次构图工艺在基板上形成包括源漏电极、 像素电极和数据线的 图形；
通过第二次构图工艺在完成所述第一次构图工艺的基板上形成包括半导 体层、 栅极绝缘层、 栅极和栅线的图形；
通过第三次构图工艺在完成所述第二次构图工艺的基板上形成包括钝化 层和钝化层过孔的图形。
该制造方法之中， 例如， 所述通过第一次构图工艺在基板上形成包括源 漏电极、 像素电极和数据线的图形包括：
在所述基板上依次形成透明导电材料和金属材料；
在所述金属材料上涂布一层光刻胶；
釆用半色调或灰色调掩模板对所述光刻胶进行曝光和显影， 形成完全保 留区域、 部分保留区域以及完全去除区域， 所述完全保留区域用于形成薄膜 晶体管的源漏电极图形和所述数据线图形， 所述部分保留区域用于形成所述 像素电极图形和半导体接触区域， 所述半导体接触区域用于使薄膜晶体管的 源漏电极图形与所述薄膜晶体管的半导体层图形充分接触；
通过刻蚀工艺去掉所述完全去除区域的所述透明导电材料和金属材料， 形成包括像素电极图形、 数据线图形和用于形成所述源电极、 漏电极图形的 源漏电极下层图形； 通过灰化工艺去掉除所述部分保留区域的光刻胶；
通过刻蚀工艺去掉所述部分保留区域的金属材料， 露出像素电极， 同时 形成源电极与漏电极的上层图形， 所述源电极与漏电极的上层图形和所述源 漏电极下层图形共同构成薄膜晶体管的源漏电极图形， 所述漏电极的下层电 极与所述像素电极为一体结构；
去掉剩余的光刻胶。
该制造方法之中， 例如， 所述通过第二次构图工艺在完成所述第一次构 图工艺的基板上形成包括半导体层、 栅极绝缘层、 栅极和栅线的图形包括： 在所述完成所述第一次构图工艺的基板上依次形成半导体材料层、 绝缘 材料层和金属材料层；
在所述金属材料层上涂布一层光刻胶；
对所述光刻胶进行曝光和显影， 形成光刻胶保留区域和去除区域， 所述 保留区域对应于用于形成包括半导体层、 栅极绝缘层、 栅极和栅线的图形的 区域；
通过刻蚀工艺去掉所述去除区域的所述半导体材料、 绝缘材料和金属材 料， 形成包括半导体层、 栅极绝缘层、 栅极和栅线的图形；
去掉剩余的光刻胶。
该制造方法之中， 例如， 所述半导体材料层为有机半导体材料。
本发明实施例提供一种显示装置， 包括如上所述的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中底栅底接触构型的薄膜晶体管的示意图；
图 2为现有技术中底栅顶接触构型的薄膜晶体管的示意图；
图 3为本发明实施例中阵列基板的切面示意图；
图 4为本发明实施例中阵列基板的平面示意图；
图 5为本发明实施例中阵列基板的制造方法流程图；
图 6为本发明实施例中沉积导电材料的示意图； 图 7为本发明实施例中釆用半色调掩模板进行曝光和显影的示意图； 图 8为本发明实施例中刻蚀导电材料的示意图；
图 9为本发明实施例中灰化光刻胶的示意图；
图 10为本发明实施例中形成源漏电极上层图形的示意图；
图 11为本发明实施例中形成源漏电极层的切面示意图；
图 12为本发明实施例中形成源漏电极层的平面示意图；
图 13为本发明实施例中在源漏电极层上沉积材料的示意图；
图 14为本发明实施例中刻蚀过程示意图；
图 15为本发明实施例中去掉剩余的光刻胶的示意图；
图 16为本发明实施例中形成钝化层的切面示意图；
图 17为本发明实施例中形成钝化层的平面示意图。
附图标记
11、 基板 12、 透明导电材料 13、 金属材料
19、 像素电极 15、 半导体材料 16、 绝缘材料
17、 栅极金属材料 130、 栅线 110、 数据线
38、 像素电极图形 14、 顶栅底接触构型的薄膜晶体管 18、 钝化层
21、 光刻胶 22、 保留区域 211、 完全保留区域
212 、 部分保留区域 213、 完全去除区域 39、 源极
40、 漏极 55、 半导体层 56、 绝缘层
57、 栅电极 33、 源电极上层图形 34、 漏电极上层图形
36、 源电极底层图形 37、 漏电极底层图形 110b、 数据线上层图形
110a, 数据线底层图形 120、 栅线外接信号区域 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的多个像素单元， 每个像素单元包括作为 开关元件的薄膜晶体管和用于控制液晶的排列的像素电极。 例如， 每个像素 的薄膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应的数据线 电连接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下面的描述 主要针对单个或多个像素单元进行， 但是其他像素单元可以相同地形成。
实施例一
本发明实施例提供了一种阵列基板。 如图 3、 4所示， 该阵列基板包括： 基板 11 , 以及位于所述基板 11上的栅线 130、 数据线 110、 薄膜晶体管和像 素电极 19,薄膜晶体管为顶栅底接触构型的薄膜晶体管 14,所述顶栅底接触 构型的薄膜晶体管 14的栅极 (即栅电极图形 57 )与所述栅线 130连接， 源 极 39与所述数据线 110连接， 漏极 40与所述像素电极 19连接。
进一步地，该薄膜晶体管的漏极 40由上下两层电极组成，下层电极与像 素电极 19为一体结构。这一结构可以实现漏极 40与像素电极 19更加良好的 电接触。 当然， 二者也可以并非一体结构， 此处不赘述。
进一步的， 在本发明实施例中， 顶栅底接触构型的薄膜晶体管的源电极 39和漏电极 40都由上下两层电极组成， 且下层电极与顶栅底接触构型的薄 膜晶体管的半导体层 55接触的一端略长出于上层电极,从而可直接与半导体 层 55接触。
如源电极 39由上下两层电极组成， 下层电极 (即源电极底层图形 36 ) 在与半导体层 55接触的一端略长出于上层电极（即源电极上层图形 33 ) — 部分，从而可直接与半导体层 55接触。该长出的一段区域用于使所述顶栅底 接触构型的有机薄膜晶体管的源漏电极图形与所述顶栅底接触构型的有机薄 膜晶体管的半导体层图形充分接触， 因此相对于现有技术增加了薄膜晶体管 中半导体层与源漏电极的接触面积， 并且还可根据实际需要调整该区域的大 小， 达到不同的性能效果。
进一步的， 在本实施例中， 数据线 110包括上下两层导电材料， 该两层 导电材料分别和顶栅底接触构型的薄膜晶体管源漏电极和像素电极 19 的材 料相同， 因此该数据线可与薄膜晶体管的源漏电极和像素电极在一次构图工 艺中一起形成。 栅线 130保留有半导体层 55的材料以及栅极绝缘层 56的材 料， 因此该栅线 130可与上述薄膜晶体管的半导体层 55、 栅极绝缘层 56以 及栅电极 57在一次构图工艺中一起形成。
进一步的， 在顶栅底接触构型的有机薄膜晶体管 14、像素电极 19、栅线 130和数据线 110上覆盖有一层钝化层 18, 且栅线 130和数据线 110的外接 信号区域 (即栅线 PAD区域 120和数据线 PAD区域）无钝化层覆盖。
可替换的，所述顶栅底接触构型的薄膜晶体管 14为顶栅底接触构型的有 机薄膜晶体管， 即有源层不是使用例如硅半导体（例如非晶硅、 多晶硅等） 或氧化物半导体 (例如 IGZO等）， 而是使用有机半导体材料 (例如酞菁等） 来形成。
本发明实施例中， 还可包括公共电极线（图中未示出） ， 该公共电极线 可以与数据线同层设置， 还可以与栅线同层设置。 当与数据线同层设置时， 公共电极线也可包括上述的上下两层导电材料， 这样可以减小公共电极线的 电阻，提高公共电极线的信号传导能力。公共电极线在 TN( Twisted Nematic, 扭曲向列）型当中用于形成存储电容，而在 ADS ( ADvanced Super Dimension Switch, 高级超维场转换技术）或 FFS ( Fringe Field Switching, 边缘场开关 技术）结构中， 主要是用于传导公共电压。
本发明实施例提供的阵列基板， 釆用顶栅底接触构型的薄膜晶体管， 有 利于半导体薄膜在薄膜晶体管漏源电极上以及沟道区域内的有序生长， 降低 阵列基板的生产难度； 同时， 在顶栅底接触构型的薄膜晶体管中， 使用两层 电极的源漏电极结构， 增大源漏电极与半导体层的接触面积， 提高顶栅底接 触构型的薄膜晶体管的性能， 进而提高阵列基板的性能。
实施例二
本发明实施例提供一种阵列基板的制造方法， 如图 5所示， 该方法包括 如下步骤。
101、通过第一次构图工艺在基板上形成包括源漏电极、像素电极和数据 线的图形；
102、通过第二次构图工艺在完成所述第一次构图工艺的基板上形成包括 半导体层、 栅极绝缘层、 栅极和栅线的图形；
103、通过第三次构图工艺在完成所述第二次构图工艺的基板上形成包括 钝化层和钝化层过孔的图形。
本发明实施例提供的阵列基板的制造方法， 在第一次构图工艺中就形成 顶栅底接触构型的薄膜晶体管的源漏电极以及阵列基板的像素电极和数据 线，并且在第二次构图工艺中形成阵列基板的栅线和薄膜晶体管的半导体层、 栅极绝缘层和栅极， 最后再利用构图工艺形成钝化层， 仅使用三次构图工艺 就完成阵列基板的制造， 相对于现有技术的制造方法在保证阵列基板性能的 同时降低了构图工艺的使用次数,进而减小了构图工艺对半导体薄膜的损伤， 同时又简化了工艺步骤， 降低了生产成本。
进一步的， 在本发明实施例中， 通过第一次构图工艺在基板上形成包括 源漏电极、 像素电极和数据线的图形的一个示例为如下所述。
首先， 如图 6所示， 在所述基板 11上依次形成透明导电材料 12和金属 材料 13。
可替换的， 在本发明实施例中， 在玻璃基板上依次溅射一层透明导电薄 膜和一层金属薄膜。 该透明导电薄膜例如使用铟锡氧化物 (ITO)形成； 该金属 薄膜可以使用铝、 铝合金、 铜等导电材料的单层膜或复合膜形成。
然后， 在所述金属材料 13上涂布一层光刻胶， 涂布方法可为旋涂。 如图 7所示，釆用半色调或灰色调掩模板对所述光刻胶 21进行曝光和显 影， 形成完全保留区域 211、部分保留区域 212以及完全去除区域 213。 所述 完全保留区域 211中的光刻胶在显影之后基本保留， 用于形成所述顶栅底接 触构型的有机薄膜晶体管的源漏电极图形和所述数据线图形； 所述部分保留 区域 212中的光刻胶在显影之后部分保留， 用于形成所述像素电极图形和半 导体接触区域； 所述完全去除区域 213中的光刻胶在显影之后基本去除。 所 述半导体接触区域用于使所述顶栅底接触构型的有机薄膜晶体管的源漏电极 图形与所述顶栅底接触构型的有机薄膜晶体管的半导体层图形充分接触。
进一步的， 如图 8所示， 通过刻蚀工艺去掉所述完全去除区域 213的所 述透明导电材料 12和金属材料 13 , 形成包括像素电极图形 38、 数据线图形 110 和用于形成所述源电极、 漏电极图形的源漏电极底层（即下层） 图形， 即源电极底层图形 36、 漏电极底层图形 37 , 所述数据线上层图形 110b和所 述数据线底层图形 110a共同形成数据线图形 110。 由于数据线与薄膜晶体管 的源漏电极在一次构图工艺中一起形成， 所以数据线 110包括上下两层导电 材料， 该两层导电材料分别和顶栅底接触构型的薄膜晶体管源漏电极和像素 电极 19的材料相同， 这种结构并不影响数据线的传输性能。
如图 9所示， 通过灰化工艺去掉除所述部分保留区域的光刻胶 21 , 同时 光刻胶完全保留区域 22中的光刻胶被减薄。
进一步的，如图 10所示，通过刻蚀工艺去掉所述部分保留区域 212的金 属材料， 露出像素电极 19, 同时形成源电极与漏电极上层图形， 即源电极上 层图形 33、漏电极上层图形 34,所述源电极与漏电极上层图形和所述源漏电 极底层图形共同形成顶栅底接触构型的薄膜晶体管的源漏电极图形， 即源电 极上层图形 33和源电极底层图形 36形成薄膜晶体管的源电极图形， 即漏电 极上层图形 34和漏电极底层图形 37形成薄膜晶体管的漏电极图形； 其中， 漏电极的下层电极与所述像素电极为一体结构。
在本发明实施例中， 源电极底层图形 36多长出于源电极上层图形 33— 部分， 该长出部分即为半导体接触区域， 该区域用于使所述顶栅底接触构型 的有机薄膜晶体管的源电极图形与所述顶栅底接触构型的有机薄膜晶体管的 半导体层图形充分接触， 相对于现有技术增加了薄膜晶体管中半导体层与源 漏电极的接触面积， 并且， 可根据实际需要调整该区域的大小， 提高生产灵 活性。
如图 11和图 12所示， 去掉剩余的光刻胶， 所述源漏电极层， 即在基板 上形成了顶栅底接触构型的有机薄膜晶体管的源极 39、漏极 40、像素电极图 形 38和数据线 110, 图 12为该阵列基板 (一个像素单元） 的平面图。
进一步的， 在本发明实施例中， 通过第二次构图工艺在完成所述第一次 构图工艺的基板上形成包括半导体层、 栅极绝缘层、 栅极和栅线的图形的一 个示例如下所述。
如图 13所示， 在所述源漏电极层上依次形成（如沉积、 溅射等）半导体 材料层 15、绝缘材料层 16和栅极金属材料层 17。该半导体材料层 15例如使 用非晶硅或氧化物半导体材料形成； 绝缘材料层 16例如使用氧化硅、氮化硅 或氧氮化硅形成； 栅极金属材料层 17例如使用铝、铝合金、铜等导电材料的 单层膜或复合膜形成。
在所述栅极金属材料层 17上涂布一层光刻胶。对所述光刻胶进行曝光和 显影， 形成光刻胶保留区域 22和去除区域， 所述保留区域 22对应于用于形 成包括半导体层、 栅极绝缘层、 栅极和栅线的图形的区域。 材料和金属材料， 形成包括栅线图形 130以及顶栅底接触构型的薄膜晶体管 的半导体层图形 55、 栅极绝缘层图形 56和栅极图形 57的图形。
进一步的， 在本发明实施例中， 由于栅线 130与上述薄膜晶体管的半导 体层 55、栅极绝缘层 56以及栅电极 57在一次构图工艺中一起形成， 所以栅 线 130由三层材料组成， 该三层材料分别和顶栅底接触构型的有机薄膜晶体 管 14的半导体层 55的材料、 栅极绝缘层 56的材料以及栅电极 57的材料相 同， 这种结构并不影响栅线的传输性能， 无需进行进一步的处理。
如图 15所示， 去掉剩余的光刻胶， 形成栅电极层， 即形成顶栅底接触构 型的薄膜晶体管的源电极 39、 漏电极 40、 半导体层 55、 栅极绝缘层 56和栅 极 57, 以及阵列基板的栅线 130和数据线 110。
进一步， 如图 16和 17所示， 通过第三次构图工艺在所述栅电极层上形 成钝化层 18和钝化层过孔。
在上述形成的源漏电极层上沉积钝化层材料，该钝化层例如釆用氧化硅、 氮化硅、 氧氮化硅或者有机绝缘材料形成。 然后， 在该涂布一层光刻胶， 使 用掩模板进行曝光、 显影， 然后进行刻蚀， 形成钝化层 18。 在栅线 130外接 信号区域 120 (栅线 PAD区域）和数据线 110外接信号区域（数据线 PAD 区域）不覆盖钝化层 18 (即形成钝化层过孔）。至此即完成阵列基板的制造。
本发明实施例提供的阵列基板的制造方法， 通过使用灰色调或半色调掩 模板， 创造性的在第一次构图工艺中就形成顶栅底接触构型的薄膜晶体管的 源漏电极以及阵列基板的像素电极和数据线， 源漏电极分为两层， 其底层长 出于其上层， 使得源漏电极图形与所述顶栅底接触构型的有机薄膜晶体管的 半导体层图形接触面积增加， 并且在第二次构图工艺中形成阵列基板的栅线 和薄膜晶体管的半导体层、 栅极绝缘层和栅极， 最后再利用构图工艺形成钝 化层， 仅使用三次构图工艺就完成阵列基板的制造， 相对于现有技术的制造 方法在保证阵列基板性能的同时降低了构图工艺的使用次数， 进而减小了构 图工艺对半导体薄膜的损伤， 同时又简化了工艺步骤， 降低了生产成本。
本发明实施例还提供一种显示装置， 使用了上述的阵列基板。 所述显示 装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数 码相框、 手机、 平板电脑等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括： 基板， 以及位于所述基板上的栅线、 数据线、 薄膜晶体管和像素电极， 其中， 所述薄膜晶体管为顶栅底接触构型的薄膜晶 体管， 所述顶栅底接触构型的薄膜晶体管的栅极与所述栅线连接， 源极与所 述数据线连接， 漏极与所述像素电极连接。
2、根据权利要求 1所述的阵列基板， 其中， 所述薄膜晶体管的漏极由上 下两层电极组成， 下层电极与所述像素电极为一体结构。
3、根据权利要求 1或 2所述的阵列基板， 其中， 所述顶栅底接触构型的 薄膜晶体管的源电极和漏电极都由上下两层电极组成， 且所述下层电极与顶 栅底接触构型的薄膜晶体管的半导体层接触的一端略长出于所述上层电极。
4、根据权利要求 1或 2所述的阵列基板， 其中， 所述数据线包括上下两 层导电材料， 所述两层导电材料分别和所述顶栅底接触构型的薄膜晶体管的 源漏电极和像素电极的材料相同。
5、根据权利要求 1或 2所述的阵列基板， 其中， 所述顶栅底接触构型的 薄膜晶体管为顶栅底接触构型的有机薄膜晶体管。
6、 一种阵列基板的制造方法， 包括：
通过第一次构图工艺在基板上形成包括源漏电极、 像素电极和数据线的 图形；
通过第二次构图工艺在完成所述第一次构图工艺的基板上形成包括半导 体层、 栅极绝缘层、 栅极和栅线的图形；
通过第三次构图工艺在完成所述第二次构图工艺的基板上形成包括钝化 层和钝化层过孔的图形。
7、根据权利要求 6所述的方法， 其中， 所述通过第一次构图工艺在基板 上形成包括源漏电极、 像素电极和数据线的图形包括：
在所述基板上依次形成透明导电材料和金属材料；
在所述金属材料上涂布一层光刻胶；
釆用半色调或灰色调掩模板对所述光刻胶进行曝光和显影， 形成完全保 留区域、 部分保留区域以及完全去除区域， 所述完全保留区域用于形成薄膜 晶体管的源漏电极图形和所述数据线图形， 所述部分保留区域用于形成所述 像素电极图形和半导体接触区域， 所述半导体接触区域用于使薄膜晶体管的 源漏电极图形与所述薄膜晶体管的半导体层图形充分接触；
通过刻蚀工艺去掉所述完全去除区域的所述透明导电材料和金属材料， 形成包括像素电极图形、 数据线图形和用于形成所述源电极、 漏电极图形的 源漏电极下层图形；
通过灰化工艺去掉除所述部分保留区域的光刻胶；
通过刻蚀工艺去掉所述部分保留区域的金属材料， 露出像素电极， 同时 形成源电极与漏电极的上层图形， 所述源电极与漏电极的上层图形和所述源 漏电极下层图形共同构成薄膜晶体管的源漏电极图形， 所述漏电极的下层电 极与所述像素电极为一体结构；
去掉剩余的光刻胶。
8、根据权利要求 6所述的方法， 其中， 所述通过第二次构图工艺在完成 所述第一次构图工艺的基板上形成包括半导体层、 栅极绝缘层、 栅极和栅线 的图形包括：
在所述完成所述第一次构图工艺的基板上依次形成半导体材料层、 绝缘 材料层和金属材料层；
在所述金属材料层上涂布一层光刻胶；
对所述光刻胶进行曝光和显影， 形成光刻胶保留区域和去除区域， 所述 保留区域对应于用于形成包括半导体层、 栅极绝缘层、 栅极和栅线的图形的 区域；
通过刻蚀工艺去掉所述去除区域的所述半导体材料、 绝缘材料和金属材 料， 形成包括半导体层、 栅极绝缘层、 栅极和栅线的图形；
去掉剩余的光刻胶。
9、根据权利要求 8所述的方法， 其中， 所述半导体材料层为有机半导体 材料。
10、 一种显示装置， 包括权利要求 1~5任一项所述的阵列基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015086621A1 (en) * 2013-12-10 2015-06-18 Plastic Logic Limnited Source/drain conductors for transistor devices

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102655155B (zh) 2012-02-27 2015-03-11 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置
CN103022147A (zh) * 2012-12-07 2013-04-03 京东方科技集团股份有限公司 阵列基板及其制备方法、薄膜晶体管及显示装置
CN103021942B (zh) 2012-12-14 2015-08-12 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
KR102040812B1 (ko) * 2013-02-12 2019-11-06 삼성디스플레이 주식회사 액정 표시 장치
KR101844284B1 (ko) 2013-10-07 2018-04-02 엘지디스플레이 주식회사 표시장치 및 그의 제조방법
US9653608B2 (en) 2013-12-23 2017-05-16 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display device and thin film transistor
CN103681514B (zh) * 2013-12-23 2016-01-27 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
JP6369098B2 (ja) * 2014-04-01 2018-08-08 凸版印刷株式会社 薄膜トランジスタの製造方法
CN105047610B (zh) * 2015-09-07 2018-10-12 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107731882A (zh) * 2017-11-07 2018-02-23 深圳市华星光电半导体显示技术有限公司 一种有机薄膜晶体管阵列基板及其制备方法、显示装置
KR102248402B1 (ko) 2018-04-19 2021-05-04 엘지디스플레이 주식회사 전계발광 표시장치 및 그 제조방법
CN109545750B (zh) * 2018-10-08 2020-03-27 深圳市华星光电半导体显示技术有限公司 薄膜晶体管基板的制作方法及其薄膜晶体管基板
CN109545803B (zh) * 2018-12-29 2020-10-13 武汉华星光电技术有限公司 阵列基板及其制作方法
CN110993625B (zh) * 2019-12-20 2022-09-02 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板、显示装置
CN113741102A (zh) * 2020-05-28 2021-12-03 合肥鑫晟光电科技有限公司 阵列基板、显示面板及制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101105615A (zh) * 2006-06-29 2008-01-16 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
US20090111198A1 (en) * 2007-10-23 2009-04-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090174835A1 (en) * 2008-01-04 2009-07-09 Samsung Electronics Co., Ltd. Liquid crystal display and method of fabricating the same to have tft's with pixel electrodes integrally extending from one of the source/drain electrodes
CN202025170U (zh) * 2011-04-22 2011-11-02 京东方科技集团股份有限公司 一种显示屏及显示装置
CN102655155A (zh) * 2012-02-27 2012-09-05 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020038482A (ko) * 2000-11-15 2002-05-23 모리시타 요이찌 박막 트랜지스터 어레이, 그 제조방법 및 그것을 이용한표시패널
KR100870701B1 (ko) * 2002-12-17 2008-11-27 엘지디스플레이 주식회사 액정표시장치용 어레이기판과 그 제조방법
JP4167085B2 (ja) * 2003-02-07 2008-10-15 株式会社 日立ディスプレイズ 液晶表示装置
TWI222546B (en) * 2003-05-28 2004-10-21 Au Optronics Corp TFT LCD and manufacturing method thereof
KR101124569B1 (ko) * 2005-06-09 2012-03-15 삼성전자주식회사 식각액, 이를 이용하는 배선 형성 방법 및 박막 트랜지스터기판의 제조 방법
KR101256544B1 (ko) 2006-08-24 2013-04-19 엘지디스플레이 주식회사 유기 박막트랜지스터 액정표시장치 및 그 제조방법
KR101291318B1 (ko) * 2006-11-21 2013-07-30 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조방법
JP4618337B2 (ja) * 2008-06-17 2011-01-26 ソニー株式会社 表示装置およびその製造方法、ならびに半導体装置およびその製造方法
CN101894807B (zh) * 2009-05-22 2012-11-21 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
JP5642447B2 (ja) * 2009-08-07 2014-12-17 株式会社半導体エネルギー研究所 半導体装置
WO2011040213A1 (en) * 2009-10-01 2011-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN102637636A (zh) * 2011-08-24 2012-08-15 京东方科技集团股份有限公司 有机薄膜晶体管阵列基板及其制作方法和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101105615A (zh) * 2006-06-29 2008-01-16 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
US20090111198A1 (en) * 2007-10-23 2009-04-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090174835A1 (en) * 2008-01-04 2009-07-09 Samsung Electronics Co., Ltd. Liquid crystal display and method of fabricating the same to have tft's with pixel electrodes integrally extending from one of the source/drain electrodes
CN202025170U (zh) * 2011-04-22 2011-11-02 京东方科技集团股份有限公司 一种显示屏及显示装置
CN102655155A (zh) * 2012-02-27 2012-09-05 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015086621A1 (en) * 2013-12-10 2015-06-18 Plastic Logic Limnited Source/drain conductors for transistor devices
CN105917482A (zh) * 2013-12-10 2016-08-31 弗莱克因艾伯勒有限公司 用于晶体管装置的源极/漏极导体
US9911854B2 (en) 2013-12-10 2018-03-06 Flexenable Limited Source/drain conductors for transistor devices
GB2521138B (en) * 2013-12-10 2019-01-02 Flexenable Ltd Source/Drain Conductors for Transistor Devices

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