WO2015143818A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2015143818A1
WO2015143818A1 PCT/CN2014/084405 CN2014084405W WO2015143818A1 WO 2015143818 A1 WO2015143818 A1 WO 2015143818A1 CN 2014084405 W CN2014084405 W CN 2014084405W WO 2015143818 A1 WO2015143818 A1 WO 2015143818A1
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Prior art keywords
layer
electrode
source
drain electrode
oxidation
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PCT/CN2014/084405
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English (en)
French (fr)
Inventor
崔承镇
牛菁
孙双
张方振
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京东方科技集团股份有限公司
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Priority to US14/436,773 priority Critical patent/US20160181278A1/en
Publication of WO2015143818A1 publication Critical patent/WO2015143818A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • TFTiCD Thin Film Transistor-Liquid Crystal Display
  • the main structure of the TFT-LCD is a liquid crystal panel including an array substrate and a color filter substrate disposed on the cartridge, and a liquid crystal molecular layer filled between the array substrate and the color filter substrate.
  • a data line, a » line, and a plurality of pixel units defined by the data line and the » line are formed on the array substrate, and each of the pixel units includes a Thin Film Transistor (TFT) and a pixel electrode.
  • TFT Thin Film Transistor
  • the gate electrode of the TFT is electrically connected to the gate line
  • the source electrode is electrically connected to the data line
  • the drain electrode is electrically connected to the pixel electrode.
  • the liquid crystal panel further includes a common electrode between which an electric field that drives deflection of the liquid crystal molecules is generated.
  • the display principle of the TFT-LCD is as follows: The scanning signal is sequentially input to each gate line through the gate line driving circuit, and the TFT of each row is turned on line by line. When the TFT of a row is in an open state, a pixel voltage is input to each column of data lines through the data line driving circuit, and the pixel voltage is applied to the pixel electrode through the source electrode, thereby controlling a driving electric field between the common electrode and the pixel electrode. , driving liquid crystal molecules to deflect, to achieve a certain gray scale display.
  • the metal of the source and drain electrodes is usually copper Cu to reduce the resistance of the data line.
  • Cii is easily oxidized. If the pixel electrode is fabricated after the drain electrode is fabricated, copper oxide is formed on the surface of the drain electrode, resulting in The electrical connection between the drain electrode and the pixel electrode is poor, resulting in poor display of the pixel unit, which seriously affects the display of ⁇ ⁇
  • the present invention provides an array substrate and a method for fabricating the same, which are used to solve the problem that after the drain electrode is fabricated, when the pixel electrode is fabricated, copper oxide is formed on the surface of the drain electrode, resulting in poor electrical connection between the drain electrode and the pixel electrode.
  • the pixel unit is poorly displayed, which seriously affects the display quality.
  • the present invention also provides a display device using the above array substrate to improve the display quality of the product.
  • an embodiment of the present invention provides an array substrate including a data line, a gate line, and a plurality of pixel units defined by the data line and the gate line, each of the pixel units including a thin film transistor and a pixel electrode.
  • the pixel electrode is electrically connected to the drain electrode, wherein the drain electrode comprises a source/drain metal layer and an oxidation resistant conductive layer, and the pixel electrode is in electrical contact with the oxidation resistant conductive layer.
  • Another embodiment of the present invention also provides a display device that picks up a column substrate as described above.
  • Another embodiment of the present invention further provides a method for fabricating an array substrate, comprising: forming a source/drain electrode film layer on a base substrate, patterning the source/drain electrode film layer, and forming a data line and a thin film transistor.
  • the drain electrode of the thin film transistor when the drain electrode of the thin film transistor is a source-drain metal which is easily oxidized, the drain electrode provided through the thin film transistor includes a source/drain metal layer and an oxidation-resistant conductive layer, the pixel electrode and the anti-oxidation conductive layer Layer electrical contact, electrical connection, can ensure the electrical connection of the pixel electrode and the drain electrode is good, improve the display quality of the display.
  • the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only Han is a part of the embodiments of the present invention. For those skilled in the art, other i-pictures can be obtained according to these figures without any creative labor.
  • FIG. 1 is a schematic structural view of an array substrate in an embodiment of the present invention.
  • Figure 2 is a cross-sectional view taken along line A A of Figure 1;
  • FIG. 3 is a schematic view showing the preparation process of the array substrate in the embodiment of the present invention.
  • FIG. 4 is a schematic view showing a process of preparing an array substrate in an embodiment of the present invention.
  • FIG. 5 is a schematic view showing the preparation process of the array substrate in the embodiment of the present invention.
  • FIG. 6 is a schematic view showing the preparation process of the array substrate in the embodiment of the present invention.
  • the data line of the thin film transistor array substrate adopts a source-drain metal (such as copper) which is easily oxidized
  • a source-drain metal such as copper
  • another patterning process is passed over the drain electrode.
  • a metal oxide is formed on the surface of the drain electrode formed on the same source/drain electrode film layer as the data line, resulting in poor electrical connection between the drain electrode and the pixel electrode.
  • an array substrate and a method of fabricating the same are provided, wherein a drain electrode of a thin film transistor includes a source/drain metal layer and an anti-oxidation conductive layer, the pixel electrode and the anti-oxidation The conductive layer is electrically contacted to realize electrical connection, and the electrical connection between the pixel electrode and the drain electrode can be ensured, and the display quality of the display is improved.
  • the pattern of the two conductive film layers is indirectly contacted by an electrical connection structure such as a wire or a via filled with a conductive medium.
  • the electrical contact of the patterns of the two conductive film layers is used to achieve electrical connection between the two.
  • the pattern of a certain film layer on the array substrate is located above the pattern of the other film layer, which means that the certain film layer precedes the other layer.
  • a film layer is formed on the substrate of the array substrate.
  • the pattern of a certain film layer on the array substrate The underlying pattern of another film layer means that the other film layer is formed on the base substrate of the array substrate before the certain film layer.
  • a column substrate which includes a data line 20, an » line 10, and a plurality of pixel units defined by the data line 20 and the gate line 10, each of the pixel units including a thin film.
  • the pixel electrode 5 is located above the drain electrode 4 of the thin film transistor and is electrically connected to the drain electrode 4. Specifically, after the drain electrode 4 is formed by one patterning process, the pixel electrode 5 is formed by another patterning process over the drain electrode 4.
  • the drain electrode 4 of the thin film transistor includes a source/drain metal layer 4 and an anti-oxidation conductive layer 42.
  • the anti-oxidation conductive layer 42 is disposed, so that the pixel electrode 5 is electrically contacted with the anti-oxidation conductive layer 42 to ensure the pixel.
  • the electrical connection between the electrode 5 and the drain electrode 4 is good.
  • the pixel electrode 5 can also be in electrical contact with the anti-oxidation conductive layer 42 and the source/drain metal layer 41.
  • the material of the anti-oxidation conductive layer 42 may be a metal or a metal alloy having low resistivity and being less susceptible to oxidation, such as one or more of MoNb, MoW or MoTi.
  • the source/drain metal layer 41 may overlap the anti-oxidation conductive layer 42 to expose a portion of the anti-oxidation conductive layer 42 to facilitate the pixel electrode 5 located above the drain electrode 4 and the anti-oxidation conductive layer.
  • the surface of 42 is in direct contact and electrically connected.
  • the source/drain metal layer 41 and the anti-oxidation conductive layer 42 can be simultaneously formed by one patterning process to simplify the manufacturing process and reduce the production cost. It is also possible to form the oxidation-resistant conductive layer 42 by one patterning process first, and then form the source/drain metal layer 4i by another patterning process.
  • the pattern overlap of a certain film layer involved in the present invention above the pattern of another film layer means: another film layer and a certain film layer sequentially formed on the substrate substrate, and There is no other film layer between one film layer and another film layer, at least a part of the pattern of the one film layer is in contact with only a part of the pattern of the other film layer, thereby exposing part of the other film The pattern of the film layer.
  • the source/drain metal layer 41 may also be located under the oxidation-resistant conductive layer 42 and simultaneously form the source-drain metal layer 41 and the oxidation-resistant conductive layer 42 by one patterning process, which is formed immediately after the formation of the source-drain electrode layer.
  • the anti-oxidation conductive film layer can effectively prevent the surface of the source and drain metal layer 41 Oxidized.
  • the anti-oxidation conductive layer 42 may correspond to the position of the source/drain metal layer 41 and be located in the region where the source/drain metal layer 41 is located (the boundary of the oxidation-resistant conductive layer 42 may be located at the boundary of the source/drain metal layer 41). Correspondingly, it may also be located inside the boundary of the source/drain metal layer 41).
  • the source electrode 3ffi in this embodiment includes a source/drain metal layer and an anti-oxidation conductive layer
  • the data line 20 also includes a source and drain. a metal layer and an anti-oxidation conductive layer.
  • ADS (or AD-SDS, Advanced Super Dimension Switch, advanced super-dimensional field conversion technology) is mainly produced by the edge of the slit pixel electrode in the same plane (that is, the slit having different extending directions on the pixel electrode)
  • the electric field and the electric field generated between the slit pixel electrode layer and the plate-like common electrode layer form a multi-dimensional electric field, so that all the aligned liquid crystal molecules between the slit pixel electrodes in the liquid crystal cell and directly above the pixel electrode can be rotated, thereby improving the liquid crystal operation.
  • Advanced super-dimensional field conversion technology can improve the picture quality of the display device, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura.
  • the TFT array substrate in this embodiment specifically includes:
  • the base substrate 10 is specifically a transparent glass substrate or a quartz substrate;
  • the village material of the active layer pattern 2 may be amorphous silicon or an oxide semiconductor
  • An etch stop layer 12 is formed over the active layer pattern 2, and a via hole above the active layer pattern 2 is formed on the etch stop layer 12;
  • the source electrode 3, the drain electrode 4 and the data line 20 are formed over the etch barrier layer 12, and the source electrode 3 and the drain electrode 4 are disposed in contact with the active layer pattern 2 through via holes on the etch barrier layer 12, the active layer
  • the portion of the pattern 2 between the source electrode 3 and the drain electrode 4 forms a channel of the thin film transistor.
  • the drain electrode 4 includes a source/drain metal layer 41 and an oxidation-resistant conductive layer 42.
  • the source/drain metal layer 41 is overlapped over the oxidation-resistant conductive layer 42 to expose a portion of the oxidation-resistant conductive layer 42.
  • Source electrode 3 also includes source and drain a metal layer and an anti-oxidation conductive layer
  • the data line 20 also includes a source-drain metal layer and an anti-oxidation conductive layer
  • a pixel electrode 5 formed over the drain electrode 4, the pixel electrode 5 overlapping the source-drain metal layer 41 and anti-oxidation Above the conductive layer 42;
  • the common electrode 6 formed above the passivation layer 15 corresponding to the position of the pixel electrode 5 includes a plurality of slits.
  • a display device which adopts the array substrate in the fif embodiment 1. Since the data line of the thin film transistor array substrate adopts a source-drain metal having a low conductivity but is easily oxidized, such as copper, the pixel can be lowered. The transmission resistance of the voltage, at the same time, improves the display quality of the display device by ensuring good electrical connection between the drain electrode and the pixel electrode.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
  • an embodiment of the present invention further provides a method for manufacturing the array substrate in the first embodiment, the manufacturing method comprising:
  • the step of forming a drain electrode of the thin film transistor further comprises: forming an anti-oxidation conductive layer a film layer, a patterning process of forming the oxidation resistant conductive film layer to form an oxidation resistant conductive layer, wherein the drain electrode comprises a source/drain metal layer and an oxidation resistant conductive layer, the pixel electrode and the anti-oxidation layer
  • the conductive layer is electrically contacted to achieve electrical connection.
  • the drain electrode of the fabricated thin film transistor includes a source/drain metal layer and an anti-oxidation conductive layer, and the pixel electrode is in electrical contact with the anti-oxidation conductive layer to achieve electrical connection, thereby ensuring the drain electrode and the pixel electrode.
  • the electrical connection is good, which improves the display quality of the display.
  • the source/drain metal layer overlaps the anti-oxidation conductive layer to expose a portion of the anti-oxidation conductive layer, facilitating the pixel electrode located above the drain electrode and the anti-oxidation conductive layer
  • the surface is in direct contact and electrically connected.
  • the source/drain metal layer of the drain electrode and the anti-oxidation conductive layer can be formed by one patterning process to simplify the manufacturing process and reduce the production cost.
  • the data line, the source electrode and the drain electrode of the thin film transistor are generally formed by one patterning process, the data line and the source electrode also include a source/drain metal layer and an oxidation resistant conductive layer.
  • a patterning process of forming a data line, a source electrode and a drain electrode of the thin film transistor includes: first, forming an anti-oxidation conductive film layer and a source/drain electrode film layer on the substrate substrate; and then, at the source/drain electrode The photoresist layer is coated on the film layer, and the photoresist is exposed and developed by using a halftone or gray tone mask to form a photoresist completely reserved region, a photoresist semi-reserved region, and a photoresist non-reserved region.
  • the photoresist completely reserved region corresponds at least to a region where the source/drain metal layer, the data line and the source electrode of the drain electrode are located, and the photoresist semi-reserved region corresponds at least to a region where the portion of the anti-oxidation conductive layer exposed in the drain electrode is located , the photoresist does not retain the area corresponding to other areas;
  • the anti-oxidation conductive film layer and the source/drain electrode film layer of the photoresist non-retained region may be etched away by wet etching;
  • the remaining photoresist is stripped to form a data line, a source electrode and a drain electrode of the thin film transistor.
  • the source/drain metal layer of the drain electrode and the anti-oxidation conductive layer are simultaneously formed by one patterning process.
  • the source/drain metal layer of the drain electrode may be located above the anti-oxidation conductive layer or under the oxidation-resistant conductive layer.
  • the source-drain metal layer and the anti-oxidation conductive layer of the drain electrode are simultaneously formed by one patterning process, which is formed immediately after forming the source-drain electrode film layer.
  • the anti-oxidation conductive film layer can effectively prevent the surface of the source/drain metal layer of the drain electrode from being oxidized.
  • the anti-oxidation conductive layer of the drain electrode may correspond to the position of the source/drain metal layer and be located in the region where the source/drain metal layer is located (the boundary of the anti-oxidation conductive layer may correspond to the boundary position of the source/drain metal layer, It may also be located inside the boundary of the source/drain metal layer).
  • the thin film transistor array substrate of the ADS display device further includes a common electrode that cooperates with the pixel electrode to form a deflection of the driving liquid crystal molecules.
  • the pixel electrode when the pixel electrode is located in the drain of the thin film transistor When the electrode is above, the pixel electrode is usually electrically connected to the drain electrode by overlapping the drain electrode.
  • the pixel electrode of the present invention overlaps at least the anti-oxidation conductive layer of the drain electrode. Specifically, the pixel electrode may overlap only the anti-oxidation conductive layer of the drain electrode, or may overlap the drain electrode. Above the anti-oxidation conductive layer, it also overlaps the source and drain metal layers.
  • the method further includes:
  • the second transparent conductive film layer is patterned to form a common electrode, wherein the common electrode includes a plurality of slits and corresponds to a position of the pixel electrode.
  • the specific preparation process of the array substrate in this embodiment is as follows:
  • Step S1 forming a gate metal film layer on the base substrate 10 (such as a transparent glass substrate or a quartz substrate) as shown in FIGS. 1 and 3, and patterning the gate metal film layer to form a gate electrode 1 and a * line 10, and a germanium insulating layer 11 is formed on the gate electrode 1 and the gate line 10.
  • the base substrate 10 such as a transparent glass substrate or a quartz substrate
  • the gate metal may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the gate metal film layer may have a single layer structure or a multilayer structure,
  • the layer structure is, for example, Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, ⁇ 1 ⁇ , and the like.
  • the gate insulating layer 11 may be formed on the gate electrode 1 and the gate line 10 by a process such as coating, chemical deposition, sputtering, or the like.
  • the gate insulating layer 11 may be a composite layer of any two of the silicon dioxide layer, the silicon oxynitride layer and the silicon nitride layer, or a silicon dioxide layer, a silicon oxynitride layer and a silicon nitride layer. Composite layer. It is preferable that the silicon dioxide layer is disposed close to the active layer pattern 2 because the H content in the SiO 2 is relatively small and does not affect the semiconductor characteristics of the active layer pattern.
  • Step S2 As shown in Fig. 1 and Fig. 3, an active layer is formed on the base substrate 10 in which the step S1 is completed, and an active layer pattern 2 is formed by patterning the active layer.
  • the material of the active layer pattern 2 is a metal oxide semiconductor such as one or more of amorphous IGZO, germanium, IZO, ZnO, Ti02., SnO, and CdSnO.
  • Step S3 forming an etch stop layer on the base substrate i0 of step S2 as shown in FIG.
  • the material of the etch barrier layer 12 is silicon nitride, silicon dioxide or silicon oxynitride.
  • Step S4 performing a patterning process on the etch barrier layer 12 by using a common mask to form the first The hole 21 and the second via 22, wherein the first via 121 and the second via 122 are located above the active layer pattern 2, exposing the active layer pattern 2, as shown in FIG.
  • Step S5 As shown in Fig. 5, an anti-oxidation conductive film layer 13 and a source/drain electrode film layer 14 are sequentially formed on the base substrate 0 of the step S4.
  • an anti-oxidation conductive film layer 3 and a source/drain electrode film layer 14 may be sequentially formed on the base substrate 10 by a process such as chemical deposition or sputtering.
  • the material of the anti-oxidation conductive film layer 13 is a metal or a metal alloy which is low in electric power and is not easily oxidized, such as one or more of MoNb, MoW or MoTi, and the material of the source/drain electrode film layer 14 is low resistance. Metal copper that is oxidized but is easily oxidized.
  • Step S6 In combination with FIG. 1 and FIG. 6, the anti-oxidation conductive film layer 13 and the source/drain electrode film layer 4 are patterned to form the source electrode 3, the drain electrode 4, and the data line 20, wherein the source electrode 3 passes
  • the first via 121 is electrically connected to the active layer pattern 2
  • the drain electrode is electrically connected to the active layer pattern 2 through the second via 122, as shown in FIG.
  • the patterning process specifically includes;
  • a photoresist is coated on the source/drain electrode film layer 14, and the photoresist is exposed and developed to form a photoresist completely reserved region and a photoresist half.
  • a reserved area and a photoresist-unretained area wherein the photoresist completely reserved area corresponds at least to a region where the source/drain metal layer 41 of the data line 20, the source electrode 3, and the drain electrode 4 is located, and the photoresist semi-reserved area corresponds to at least leakage
  • the portion of the electrode 4 in which the portion of the anti-oxidation conductive layer 42 is exposed is located, and the region where the photoresist is not retained corresponds to other regions;
  • the anti-oxidation conductive film layer and the source/drain electrode film layer of the photoresist non-retained region may be etched away by wet etching;
  • the photoresist in the semi-reserved region of the photoresist is removed by an ashing process, and the source-drain electrode film layer of the semi-reserved region of the photoresist is etched away, and the source-drain electrode film layer is preferably etched away by an etching solution, wherein
  • the mixing ratio of the etching solution and the deionized water is 2:1 or i:1 -1 :5 , which is beneficial to slowing down the speed b of the source and drain metal etching;
  • the remaining photoresist is stripped to form the source electrode 3, the drain electrode 4 and the data line 20 of the thin film transistor, wherein the source electrode 3 and the data line 20 also include a source/drain metal layer and an oxidation-resistant conductive layer.
  • Step S7 As shown in FIG. 2, a first transparent conductive film layer, such as ITO or IZO, is formed on the base substrate 10 on which the step S6 is completed, and the first transparent conductive film layer is formed by using a common mask.
  • the patterning process forms the pixel electrode 5, wherein the pixel electrode 5 overlaps the source/drain metal layer of the drain electrode 4
  • Step S8 As shown in Fig. 2, a passivation layer 15 is formed on the base substrate 10 on which the step S7 is completed.
  • the material of the passivation layer 5 is silicon dioxide, silicon nitride or silicon oxynitride.
  • Step S9 In combination with FIG. 1, a second transparent conductive film layer, such as germanium or IZO, is formed on the base substrate 10 of step S8, and the second transparent conductive film layer is patterned by using a common mask.
  • the common electrode 6 is formed, wherein the common electrode 6 includes a plurality of slits and corresponds to the position of the pixel electrode 5.
  • the fabrication of the array substrate is completed by the steps S1 to S9.
  • the drain electrode of the thin film transistor when the drain electrode of the thin film transistor is a source-drain metal which is easily oxidized, the drain electrode provided through the thin film transistor includes a source/drain metal layer and an anti-oxidation conductive layer, the pixel electrode and the anti-oxidation The conductive layer is electrically contacted to realize electrical connection, which can ensure good electrical connection between the pixel electrode and the drain electrode, and improve display quality of the display device.

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Abstract

一种阵列基板及其制作方法、显示装置。所述阵列基板包括数据线（20）和栅线（10），以及由数据线（20）和栅线（10）限定的多个像素单元，每个像素单元包括薄膜晶体管和像素电极（5），漏电极（4）包括源漏金属层（41）和抗氧化的导电层（42），所述像素电极（5）与所述抗氧化的导电层（42）电性接触，实现电性连接。当薄膜晶体管的漏电极（4）为容易被氧化的源漏金属时，所述像素电极（5）与所述抗氧化的导电层（42）的电性接触，可以保证像素电极（5）和漏电极（4）的电性连接良好，提高显示器的显示品质。

Description

阵列基板及其制造方法、 显示装置
本申请主张在 2014 年 3 月 28 日在中国提交的中国专利申请号 No. 201410122807.2的优先权， 其全部内容通过引用包含于此。
Figure imgf000003_0001
薄膜晶体管液晶显示器 ( Thin Film Transistor-Liquid Crystal Display, 筒 称 TFTiCD) 具有体积小、 功耗低、 无辐射等特点， 近年来得到迅速发展， 在当前的平板显示器市场中占据主导地位。
TFT-LCD的主体结构为液晶面板， 液晶面板包括对盒设置的阵列基板和 彩膜基板以及填充在阵列基板和彩膜基板之间的液晶分子层。 阵列基板上形 成有数据线、 »线以及由数据线和 »线限定的多个像素单元， 每个像素单元 包括薄膜晶体管 （Thin Film Transistor, 简称 TFT) 和像素电极。 TFT的栅电 极与栅线电性连接， 源电极与数据线电性连接， 漏电极与像素电极电性连接。 其中， 栅电极与栅线由同一栅金属膜层形成， 源电极、 漏电极与数据线由同 一源漏电极膜层形成。 液晶面板还包括公共电极， 在其与像素电极之间产生 驱动液晶分子偏转的电场。 TFT-LCD的显示原理为： 通过栅线驱动电路依次 向每行栅线输入扫描信号， 逐行打开每一行的 TFT。 当某行的 TFT为打开状 态时， 通过数据线驱动电路向每列数据线输入像素电压， 并通过源电极将该 像素电压施加到像素电极上， 从而控制公共电极与像素电极之间产生驱动电 场， 驱动液晶分子偏转， 实现一定灰阶的显示。
现有技术中， 为了降低像素电压在传输过程中的损耗， 源漏电极的金属 通常采用铜 Cu， 以降低数据线的电阻。 但是 Cii很容易发生氧化， 如果在漏 电极制作完成之后， 再制作像素电极， 会在漏电极的表面形成氧化铜， 导致 漏电极与像素电极的电性连接不良， 造成像素单元显示不良， 严重影响显示 π ^·
本发明提供一种阵列基板及其制造方法， 用以解决在漏电极制作完成之 后， 在制作像素电极时， 漏电极的表面会形成氧化铜， 导致漏电极与像素电 极的电性连接不良， 造成像素单元显示不良， 严重影响显示品质的问题。
本发明还提供一种显示装置， 采用上述的阵列基板， 提高了产品的显示 品质。
为解决上述技术问题， 本发明的一个实施方式提供一种阵列基板， 包括 数据线、 栅线以及由数据线和栅线限定的多个像素单元， 每个像素单元包括 薄膜晶体管和像素电极， 所述像素电极与所述漏电极电性连接， 其中， 所述 漏电极包括源漏金属层和抗氧化的导电层， 所述像素电极与所述抗氧化的导 电层电性接触。
本发明的另一个实施方式还提供一种显示装置， 采) ¾如上所述的 列基 板。
本发明的另一个实施方式还提供一种阵列基板的制造方法， 包括： 在衬底基板上形成源漏电极膜层， 对所述源漏电极膜层进行构图工艺， 形成数据线、 薄膜晶体管的源电极和漏电极；
在所述衬底基板上形成第一透明导电膜层， 对所述第一透明导电膜层进 行构图工艺， 形成像素电极， 其中， 制作薄膜晶体管的漏电极的步骤还包括: 形成抗氧化的导电膜层， 对所述抗氧化的导电膜层进行构图工艺， 形成 抗氧化的导电层， 所述像素电极与所述抗氧化的导电层电性接触。
本发明的上述实施方式的有益效果如下：
上述实施方式中， 当薄膜晶体管的漏电极为容易被氧化的源漏金属时， 通过设置薄膜晶体管的漏电极包括源漏金属层和抗氧化的导电层， 所述像素 电极与所述抗氧化的导电层电性接触， 实现电性连接， 可以保证像素电极和 漏电极的电性连接良好， 提高显示器的显示品质。 为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅汉是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动性的前提下， 还可以根据这些 i†图获得其他的 i†图。
图 1表示本发明实施例中阵列基板的结构示意图；
图 2表示图 1沿 A A方向的剖视图；
图 3表示本发明实施例中阵列基板的制备过程示意图。
图 4表示本发明实施例中阵列基板的制备过程示意图。
图 5表示本发明实施例中阵列基板的制备过程示意图。
图 6表示本发明实施例中阵列基板的制备过程示意图。
现有技术中当薄膜晶体管阵列基板的数据线采用容易被氧化的源漏金属 (如： 铜）， 特别的， 当在通过一次构图工艺形成漏电极后， 再在漏电极上方 通过另一次构图工艺形成像素电极时， 会在与数据线采 同一源漏电极膜层 形成的漏电极的表面形成金属氧化物， 导致漏电极与像素电极的电性连接不 良。 本发明的一个实施方式中， 针对上述问题， 提供一种阵列基板及其制造 方法， 通过设置薄膜晶体管的漏电极包括源漏金属层和抗氧化的导电层， 所 述像素电极与所述抗氧化的导电层电性接触， 实现电性连接， 丛而可以保证 像素电极和漏电极的电性连接良好， 提高显示器的显示品质。
本发明的一个实施方式中的电性接触包括：
1 ) 两个导电膜层的图案的表面直接接触；
2 )两个导电膜层的图案通过电性连接结构（如导线、 或填充有导电介质 的过孔） 间接接触。
而两个导电膜层的图案的电性接触用于实现两者的电性连接。
需要说明的是， 本发明的实施方式和实施例中所涉及的阵列基板上的某 一膜层的图案位于另一膜层的图案的上方， 是指所述某一膜层先于所述另一 膜层形成在阵列基板的衬底基板上。 相应地， 阵列基板上的某一膜层的图案 位于另一膜层的图案的下方， 是指所述另一膜层先于所述某一膜层形成在阵 列基板的衬底基板上。
下面将结合 图和实施例，对本发明的具体实施方式作进一步详细描述。 以下实施例用于说明本发明， 但不用来限制本发明的范園。
实施例一
结合图 1和图 2所示，本实施例中提供一种 列基板，其包括数据线 20、 »线 10以及由数据线 20和栅线 10限定的多个像素单元，每个像素单元包括 薄膜晶体管和像素电极 5。 像素电极 5位于薄膜晶体管的漏电极 4的上方， 并与漏电极 4电性连接。 具体的， 在通过一次构图工艺形成漏电极 4后， 再 在漏电极 4的上方通过另一次构图工艺形成像素电极 5。
其中， 薄膜晶体管的漏电极 4包括源漏金属层 4】和抗氧化的导电层 42， 通过设置抗氧化的导电层 42， 使得像素电极 5通过与抗氧化的导电层 42电 性接触， 保证像素电极 5和漏电极 4的电性连接良好。 当然， 像素电极 5也 可以既与抗氧化的导电层 42电性接触， 又与源漏金属层 41电性接触。
在具体的应) ¾过程中，抗氧化的导电层 42的材料可以为低电阻率且不易 被氧化的金属或金属合金， 如： MoNb、 MoW或 MoTi中的一种或多种。
其中， 漏电极 4中， 源漏金属层 41可以搭接在抗氧化的导电层 42的上 方， 露出部分抗氧化的导电层 42， 方便位于漏电极 4上方的像素电极 5与抗 氧化的导电层 42的表面直接接触而电性连接。具体的， 可以通过一次构图工 艺同时形成源漏金属层 41 和抗氧化的导电层 42， 以简化制作工艺， 降低生 产成本。 也可以通过一次构图工艺先形成抗氧化的导电层 42， 再通过另一次 构图工艺形成源漏金属层 4i。
需要说明的是， 本发明中涉及的某一膜层的图案搭接在另一膜层的图案 的上方是指： 依次形成在衬底基板上的另一膜层和某一膜层， 且所述某一膜 层和另一膜层之间没有其他膜层， 所述某一膜层的图案的至少一部分和所述 另一膜层的图案的仅一部分接触设置， 从而露出部分所述另一膜层的图案。
当然， 源漏金属层 41也可以位于抗氧化的导电层 42下方， 并通过一次 构图工艺同时形成源漏金属层 41 和抗氧化的导电层 42， 由于在形成源漏电 极膜层后， 立即形成抗氧化的导电膜层， 可以有效防止源漏金属层 41的表面 被氧化。 此时， 抗氧化的导电层 42可以与源漏金属层 41的位置对应， 并位 于源漏金属层 41所在的区域内 （抗氧化的导电层 42的边界可以与源漏金属 层 41的边界位置对应， 也可以位于源漏金属层 41的边界的内侧）。
由于数据线、 薄膜晶体管的源电极和漏电极一般是通过一次构图工艺形 成的， 则本实施例中的源电极 3 ffi包括源漏金属层和抗氧化的导电层， 数据 线 20也包括源漏金属层和抗氧化的导电层。
下面以 ADS模式显示装置的 TFT阵列基板为例， 来具体说明本发明实 施例中 TFT阵列基板的具体结构：
其中， ADS (或称 AD- SDS， Advanced Super Dimension Switch, 高级超 维场转换技术） 主要是通过同一平面内狹缝像素电极 （即像素电极上具有多 个延伸方向不同的狭缝） 边缘所产生的电场以及狭缝像素电极层与板状公共 电极层间产生的电场形成多维电场， 使液晶盒内狭缝像素电极间、 像素电极 正上方所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大 了透光效率。 高级超维场转换技术可以提高显示装置的画面品质， 具有高分 辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波紋 (push Mura) 等优点。
结合图 1和图 2所示， 本实施例中的 TFT阵列基板具体包括：
衬底基板 10， 具体为透明的玻璃基板或石英基板；
形成在衬底基板 10上的 *电极 1和栅线 10;
形成在栅电极 1和栅线 10上方的栅绝缘层 11U
形成在栅绝缘层 11上方、 与栅电极 i的位置对应的有源层图案 2， 有源 层图案 2的村料可以为非晶硅或氧化物半导体；
形成在有源层图案 2上方的刻蚀阻挡层 12， 刻蚀阻挡层 12上形成有位 于有源层图案 2上方的过孔；
形成在刻蚀阻挡层 12上方的源电极 3、 漏电极 4和数据线 20， 源电极 3 和漏电极 4通过刻蚀阻挡层 12上的过孔与有源层图案 2接触设置，有源层图 案 2位于源电极 3和漏电极 4之间的部分形成薄膜晶体管的沟道。 其中， 漏 电极 4包括源漏金属层 41和抗氧化的导电层 42， 源漏金属层 41搭接在抗氧 化的导电层 42的上方， 露出部分抗氧化的导电层 42。 源电极 3也包括源漏 金属层和抗氧化的导电层， 数据线 20也包括源漏金属层和抗氧化的导电层； 形成在漏电极 4上方的像素电极 5， 像素电极 5搭接在源漏金属层 41和 抗氧化的导电层 42的上方；
形成在像素电极 5上方的钝化层 15;
形成在钝化层 15上方、 与像素电极 5位置对应的公共电极 6， 公共电极 6包括多个狭缝。
实施例二
本实施例中提供一种显示装置， 其采 ffi实施例一中的阵列基板， 由于薄 膜晶体管阵列基板的数据线采用了导电率较低但容易被氧化的源漏金属， 如 铜， 可以降低像素电压的传输电阻， 同时， 由于保证了漏电极和像素电极的 电性连接良好， 从而提高了显示装置的显示品质。
所述显示装置可以为： 液晶面板、 电子纸、 OLED 面板、 手机、 平板电 脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能 的产品或部件。
实施例三
基于同一发明构思， 本发明实施例还提供一种制造实施例一中的阵列基 板的方法， 所述制造方法包括：
在衬底基板上形成源漏电极膜层， 对所述源漏电极膜层进行构图工艺， 形成数据线、 薄膜晶体管的源电极和漏电极；
在所述衬底基板上形成第一透明导电膜层， 对所述第一透明导电膜层进 行构图工艺， 形成像素电极， 其中， 制作薄膜晶体管的漏电极的步骤还包括: 形成抗氧化的导电膜层， 对所述抗氧化的导电膜层进行构图工艺， 形成 抗氧化的导电层， 则所述漏电极包括源漏金属层和抗氧化的导电层， 所述像 素电极与所述抗氧化的导电层电性接触， 实现电性连接。
上述步骤中， 制作的薄膜晶体管的漏电极包括源漏金属层和抗氧化的导 电层， 像素电极与所述抗氧化的导电层电性接触， 实现电性连接， 从而保证 了漏电极和像素电极的电性连接良好， 提高了显示器的显示品质。
其中， 所述漏电极中， 源漏金属层搭接在抗氧化的导电层的上方， 露出 部分抗氧化的导电层， 方便位于漏电极上方的像素电极与抗氧化的导电层的 表面直接接触， 电性连接。 具体的， 可以通过一次构图工艺形成漏电极的源 漏金属层和抗氧化的导电层， 以简化制作工艺， 降低生产成本。
由于数据线、 薄膜晶体管的源电极和漏电极一般是通过一次构图工艺形 成， 则数据线和源电极也包括源漏金属层和抗氧化的导电层。
具体的， 形成数据线、 薄膜晶体管的源电极和漏电极的构图工艺包括： 首先， 在所述衬底基板上依次形成抗氧化的导电膜层和源漏电极膜层； 之后， 在源漏电极膜层上涂覆光刻胶， 采用半色调或灰色调掩膜板对所 述光刻胶进行曝光， 显影， 形成光刻胶完全保留区域、 光刻胶半保留区域和 光刻胶不保留区域， 其中， 光刻胶完全保留区域至少对应漏电极的源漏金属 层、 数据线和源电极所在的区域， 光刻胶半保留区域至少对应漏电极中露出 的部分抗氧化的导电层所在的区域， 光刻胶不保留区域对应其他区域；
之后， 可以釆用湿刻法刻蚀掉光刻胶不保留区域的抗氧化的导电膜层和 源漏电极膜层；
然后， 通过灰化工艺去除光刻胶半保留区域的光刻胶， 并刻蚀掉光刻胶 半保留区域的源漏电极膜层；
最后， 剥离剩余的光刻胶， 形成数据线、 薄膜晶体管的源电极和漏电极。 上述步骤中， 是通过一次构图工艺同时形成漏电极的源漏金属层和抗氧 化的导电层。 当然也可以通过一次构图工艺先在所述衬底基板上形成漏电极 的抗氧化的导电层， 再通过另一次构图工艺在形成有所述抗氧化的导电层的 衬底基板上形成漏电极的源漏金属层。
漏电极的源漏金属层可以位于抗氧化的导电层的上方， 也可以位于抗氧 化的导电层的下方。 当漏电极的源漏金属层位于抗氧化的导电层下方时， 需 要通过一次构图工艺同时形成漏电极的源漏金属层和抗氧化的导电层， 由于 在形成源漏电极膜层后， 立即形成抗氧化的导电膜层， 可以有效防止漏电极 的源漏金属层的表面被氧化。 此时， 漏电极的抗氧化的导电层可以与源漏金 属层的位置对应， 并位于源漏金属层所在的区域内 （抗氧化的导电层的边界 可以与源漏金属层的边界位置对应， 也可以位于源漏金属层的边界的内侧）。
对于 ADS显示装置的薄膜晶体管阵列基板，还包括与像素电极共同作用 形成驱动液晶分子偏转的公共电极。 其中， 当像素电极位于薄膜晶体管的漏 电极上方时， 像素电极通常通过搭接在漏电极上方的方式， 与漏电极电性连 接。 本发明中的像素电极至少搭接在漏电极的抗氧化的导电层的上方， 具体 的， 像素电极可以只搭接在漏电极的抗氧化的导电层的上方， 也可以既搭接 在漏电极的抗氧化的导电层的上方， 同时也搭接在源漏金属层的上方。
相应地， 在衬底基板上形成像素电极之后还包括：
在形成有像素电极的衬底基板上形成钝化层；
在形成有钝化层的衬底基板上形成第二透明导电膜层；
对所述第二透明导电膜层进行构图工艺， 形成公共电极， 其中， 所述公 共电极包括多个狭缝， 并与像素电极的位置对应。
结合图 1-图 6所示， 本实施例中阵列基板的具体制备过程为：
步骤 S1 : 结合图 1和 3所示， 在衬底基板 10 (如透明的玻璃基板或石英 基板） 上形成栅金属膜层， 对所述栅金属膜层进行构图工艺形成栅电极 1和 *线 10, 并在栅电极 1和栅线 10形成欐绝缘层 11。
其中， 栅金属可以是 Cu， Al， Ag， Mo, Cr, Nd, Ni, Mn, Ti, Ta, W 等金属以及这些金属的合金， 栅金属膜层可以为单层结构或者多层结构， 多 层结构比如 Cu\Mo, Ti\Cu\Ti, Μο\Α1\Μο等。
具体可以通过涂覆、化学沉积、溅射等工艺在栅电极 1和栅线 10上形成 栅绝缘层 11。其中， 栅绝缘层 11可以为二氧化硅层、氮氧化硅层和氮化硅层 中任意两个膜层的复合层或二氧化硅层、 氮氧化硅层和氮化硅层三个膜层的 复合层。优选二氧化硅层靠近有源层图案 2设置，因为 Si02中 H含量比较小， 不会对有源层图案的半导体特性产生影响。
步骤 S2: 结合图 1和图 3所示， 在完成步骤 S1的衬底基板 10形成有源 层， 并对有源层进行构图工艺形成有源层图案 2。
其中，有源层图案 2的材料为金属氧化物半导体，如：非晶 IGZO、 ΗΙΖΟ、 IZO、 ZnO、 Ti02.、 SnO, CdSnO中的一种或多种。
步骤 S3 : 如图 3所示， 在完成步骤 S2的衬底基板 i0上形成刻蚀阻挡层
12。
其中， 刻蚀阻挡层 12的材料为氮化硅、 二氧化硅或氮氧化硅。
步骤 S4: 采用普通掩膜板对刻蚀阻挡层 12进行构图工艺， 形成第一过 孔】21和第二过孔】22， 其中， 第一过孔 121和第二过孔 122位于有源层图 案 2的上方， 露出有源层图案 2， 如图 4所示。
步骤 S5: 如图 5所示， 在完成步骤 S4的衬底基板】 0上依次形成抗氧化 的导电膜层 13和源漏电极膜层 14。
具体可以采^化学沉积、溅射等工艺在衬底基板 10上依次形成抗氧化的 导电膜层】3和源漏电极膜层 14。 其中， 抗氧化的导电膜层 13的材料为低电 率且不易被氧化的金属或金属合金， 如 MoNb、 MoW或 MoTi中的一种或 多种， 源漏电极膜层 14的材料为低电阻率但易被氧化的金属铜。
步骤 S6: 结合图 1和图 6所示， 对抗氧化的导电膜层 13和源漏电极膜 层】 4进行构图工艺， 形成源电极 3、 漏电极 4和数据线 20， 其中， 源电极 3 通过第一过孔 121与有源层图案 2电性连接， 漏电极通过第二过孔 122与有 源层图案 2电性连接， 结合图 4所示。
所述构图工艺具体包括；
首先， 在源漏电极膜层 14上涂覆光刻胶， 采) ¾半色调或灰色调掩膜板对 所述光刻胶进行曝光， 显影， 形成光刻胶完全保留区域、 光刻胶半保留区域 和光刻胶不保留区域， 其中， 光刻胶完全保留区域至少对应数据线 20、 源电 极 3和漏电极 4的源漏金属层 41所在的区域，光刻胶半保留区域至少对应漏 电极 4中露出的部分抗氧化的导电层 42所在的区域，光刻胶不保留区域对应 其他区域；
之后， 可以采用湿刻法刻蚀掉光刻胶不保留区域的抗氧化的导电膜层和 源漏电极膜层；
然后， 通过灰化工艺去除光刻胶半保留区域的光刻胶， 并刻蚀掉光刻胶 半保留区域的源漏电极膜层， 优选通过刻蚀液刻蚀掉源漏电极膜层， 其中， 刻蚀液与去离子水混合比例为 2: 1 或 i : l -1 :5 ,有利于减缓源漏金属刻蚀的速 b ;
最后， 剥离剩余的光刻胶， 形成薄膜晶体管的源电极 3、 漏电极 4和数 据线 20， 其中， 源电极 3和数据线 20也包括源漏金属层和抗氧化的导电层。
歩骤 S7: 结合图 2所示， 在完成步骤 S6的衬底基板 10上形成第一透明 导电膜层， 如 ITO或 IZO， 采用普通的掩膜板对所述第一透明导电膜层进行 构图工艺形成像素电极 5， 其中， 像素电极 5搭接在漏电极 4的源漏金属层
41和抗氧化的导电层 42的上方。
步骤 S8:结合图 2所示，在完成步骤 S7的衬底基板 10上形成钝化层 15。 其中， 钝化层】5的材料为二氧化硅、 氮化硅或氮氧化硅。
步骤 S9: 结合图 1所示， 在完成步骤 S8的衬底基板 10上形成第二透明 导电膜层， 如 ΠΌ或 IZO， 采用普通的掩膜板对所述第二透明导电膜层进行 构图工艺形成公共电极 6， 其中， 公共电极 6包括多个狭缝， 并与像素电极 5 的位置对应。
通过步骤 S1 S9即完成阵列基板的制作。
本发明的技术方案中， 当薄膜晶体管的漏电极为容易被氧化的源漏金属 时， 通过设置薄膜晶体管的漏电极包括源漏金属层和抗氧化的导电层， 所述 像素电极与所述抗氧化的导电层电性接触， 实现电性连接， 可以保证像素电 极和漏电极的电性连接良好， 提高显示装置的显示品质。
以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普 通技术人员来说， 在不脱离本发明技术原理的前提下， 还可以做出若干改进 和替换， 这些改进和替换也应视为本发明的保护范围。

Claims

1 . 一种阵列基板， 包括数据线、 »线以及由数据线和栅线限定的多个像 素单元， 每个像素单元包括薄膜晶体管和像素电极， 所述像素电极与所述薄 膜晶体管的漏电极电性连接， 其中，
所述漏电极包括源漏金属层和抗氧化的导电层， 所述像素电极与所述抗 氧化的导电层电性接触。
2. 根据权利要求 1所述的阵列基板， 其中， 所述漏电极中， 所述源漏金 属层搭接在所述抗氧化导电层的上方， 露出部分所述抗氧化的导电层。
3. 根据权利要求 2所述的阵列基板， 其中， 所述像素电极搭接在所述漏 电极的源漏金属层和抗氧化的导电层的上方。
4. 根据权利要求 3所述的阵列基板， 其中， 所述 列基板还包括公共电 极， 所述公共电极包括多个狭缝， 位于所述像素电极上方， 所述公共电极和 像素电极之间形成有钝化层。
5. 根据权利要求 1所述的阵列基板， 其中， 所述源电极包括源漏金属层 和抗氧化的导电层；
所述数据线包括源漏金属层和抗氧化的导电层。
6. 根据权利要求 1 5任一项所述的阵列基板， 其中， 所述源漏金属层的 材料包括铜。
7. 根据权利要求 1 6任一项所述的阵列基板， 其中， 所述抗氧化的导电 层的材料包括 MoNb、 MoW或 MoTi中的一种或多种。
8. 一种显示装置， 采用权利要求 1-7任一项所述的阵列基板。
9. 一种阵列基板的制造方法， 包括：
在衬底基板上形成源漏电极膜层， 对所述源漏电极膜层进行构图工艺， 形成数据线、 薄膜晶体管的源电极和漏电极；
在形成有所述数据线、 源电极和漏电极的所述衬底基板上形成第一透明 导电膜层， 对所述第一透明导电膜层进行构图工艺， 形成像素电极，
其中， 制作所述薄膜晶体管的漏电极的步骤还包括：
形成抗氧化的导电膜层， 对所述抗氧化的导电膜层进行构图工艺， 形成 抗氧化的导电层， 所述像素电极与所述抗氧化的导电层电性接触。
10. 根据权利要求 9 所述的制造方法， 其中， 所述漏电极中， 所述源漏 金属层搭接在所述抗氧化导电层的上方， 露出部分所述抗氧化导电层。
11 . 根据权利要求 10所述的制造方法， 其中， 形成数据线、 薄膜晶体管 的源电极和漏电极的步骤包括：
在所述衬底基板上依次形成抗氧化的导电膜层和源漏电极膜层； 在所述源漏金属层上涂覆光刻胶；
采用灰色调或半色调掩膜板对所述光刻胶进行曝光， 显影， 形成光刻胶 完全保留区域、 光刻胶半保留区域和光刻胶不保留区域， 其中， 光刻胶完全 保留区域至少对应漏电极的源漏金属层、 数据线和源电极所在的区域， 光刻 胶半保留区域至少对应漏电极中露出的部分抗氧化的导电层所在的区域， 光 刻胶不保留区域对应其他区域；
刻蚀掉光刻胶不保留区域的抗氧化的导电膜层和源漏电极膜层； 通过灰化工艺去除光刻胶半保留区域的光刻胶， 并刻蚀掉光刻胶半保留 区域的源漏电极膜层；
剥离剩余的光刻胶， 形成数据线、 薄膜晶体管的源电极和漏电极。
12. 根据权利要求 9- 1 1任一项所述的制造方法， 其中， 所述形成所述像 素电极的步骤之后还包括：
在形成有所述像素电极的衬底基板上形成钝化层；
在形成有所述钝化层的衬底基板上形成第二透明导电膜层；
对所述第二透明导电膜层进行构图工艺， 形成公共电极， 其中， 所述公 共电极包括多个狭缝。
13. 根据权利要求 9- 12任一项所述的制造方法， 其中， 所述形成所述数 据线、 所述源电极和所述漏电极的步骤之前还包括：
在所述衬底基板上形成栅金属膜层， 对所述 »金属膜层进行构图工艺， 形成欐线和薄膜晶体管的栅电极；
在所述栅电极和栅线上形成極绝缘层；
在所述栅绝缘层上形成有源层膜层， 对所述有源层膜层进行构图工艺， 形成有源层； 在所述有源层上形成刻蚀阻挡层膜层， 对所述刻蚀 ffi挡层膜层进行构图 工艺， 在对应所述薄膜晶体管的源电极和漏电极对应的部分形成过孔， 所述 薄膜晶体管的源电极和漏电极通过所述过孔与所述有源层电连接。
14. 根据权利要求 9- 13任一项所述的制造方法， 其中， 所述源漏金属层 的材料包括铜。
15. 根据权利要求 9-14任一项所述的制造方法， 其中， 所述抗氧化的导 电层的材料包括 MoNb、 MoW或 MoTi中的一种或多种。
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