CN105552028A - 阵列基板及其制作方法、显示面板及显示装置 - Google Patents

阵列基板及其制作方法、显示面板及显示装置 Download PDF

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Publication number
CN105552028A
CN105552028A CN201610091331.XA CN201610091331A CN105552028A CN 105552028 A CN105552028 A CN 105552028A CN 201610091331 A CN201610091331 A CN 201610091331A CN 105552028 A CN105552028 A CN 105552028A
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China
Prior art keywords
film transistor
thin
photoresist
electrode
insulation layer
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CN201610091331.XA
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Inventor
王守坤
郭会斌
冯玉春
李梁梁
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to CN201610091331.XA priority Critical patent/CN105552028A/zh
Publication of CN105552028A publication Critical patent/CN105552028A/zh
Priority to PCT/CN2016/083241 priority patent/WO2017140058A1/zh
Priority to US15/525,979 priority patent/US10254609B2/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/1259—Multistep manufacturing methods
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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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Abstract

本发明涉及显示技术领域，公开了一种阵列基板及其制作方法、显示面板及显示装置。所述阵列基板包括薄膜晶体管和像素电极，所述薄膜晶体管的漏电极和像素电极之间形成绝缘层，所述漏电极和像素电极通过所述绝缘层中的过孔直接电性接触，连接良好，不易出现输接触不良的问题，提高了显示器件的良率。

Description

阵列基板及其制作方法、显示面板及显示装置
技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板及其制作方法、显示面板及显示装置。
背景技术
薄膜晶体管液晶显示器(ThinFilmTransistor-LiquidCrystalDisplay，简称TFT-LCD)具有体积小，功耗低，无辐射等特点，近年来得到迅速发展，在当前的平板显示器市场中占据主导地位。TFT-LCD的主体结构为液晶面板，液晶面板包括背光源、对盒的薄膜晶体管阵列基板和彩膜基板，液晶分子填充在阵列基板和彩膜基板之间。其中，阵列基板包括交叉分布的多条栅线和数据线，用于限定多个像素区域。参见图1所示，每一像素区域包括像素电极1和薄膜晶体管，薄膜晶体管的栅电极3与栅线连接，源电极4与数据线连接，漏电极5与像素电极1连接。薄膜晶体管作为开关器件，用于控制像素电极1与公共电极2形成驱动液晶偏转的电场，实现显示。
根据驱动液晶电场的方向，TFT-LCD分为垂直电场型和水平电场型。其中，垂直电场型TFT-LCD的公共电极形成在彩膜基板上，包括扭曲向列型(TN型)。水平电场型TFT-LCD的公共电极2形成在阵列基板上，包括高级超维场转换型(HADS型，如图1所示)。HADS技术可以提高显示装置的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(pushMura)等优点。
针对不同应用，HADS技术的改进技术有高透过率的I-HADS技术、高开口率的H-HADS技术和高分辨率的S-HADS技术等。参见图1所示，基于H-HADS技术的阵列基板包括板状像素电极1和狭缝公共电极2。现有技术中的H-HADS型阵列基板，薄膜晶体管的漏电极5和像素电极1不同层设置，具体通过以下方式来连接漏电极5和像素电极1：在完成薄膜晶体管的制作后，形成过孔，露出薄膜晶体管的漏电极5和像素电极1，然后在制作狭缝公共电极2的过程中，形成透明导电图形7。透明导电图形7分别与露出的漏电极5和像素电极1电性接触，实现漏电极5和像素电极1的连接。但是这种通过第三导电层连接漏电极5和像素电极1的方式，容易出现传输接触不良，使产品的良率急剧下降。
发明内容
本发明提供一种HADS阵列基板及其制作方法、显示面板及显示装置，用以解决现有技术中薄膜晶体管的漏电极和像素电极的电性连接方式容易出现传输接触不良，使产品的良率急剧下降的问题。
为解决上述技术问题，本发明实施例中提供一种阵列基板的制作方法，所述阵列基板包括多个像素区域，所述制作方法包括：
提供一基底；
在每一像素区域形成薄膜晶体管和像素电极；
在所述薄膜晶体管的漏电极和像素电极之间形成绝缘层，形成绝缘层的步骤包括：
在所述绝缘层中形成过孔，所述漏电极和像素电极通过所述过孔直接电性接触。
本发明实施例中还提供一种阵列基板，包括多个像素区域，每一像素区域包括设置在一基底上的薄膜晶体管和像素电极，所述阵列基板还包括位于所述薄膜晶体管的漏电极和像素电极之间形成绝缘层，所述绝缘层中具有过孔，所述漏电极和像素电极通过所述过孔直接电性接触。
本发明实施例中还提供一种显示面板，包括如上所述的阵列基板。
本发明实施例中还提供一种显示装置，包括如上所述的阵列基板。
本发明的上述技术方案的有益效果如下：
上述技术方案中，薄膜晶体管的漏电极和像素电极通过过孔直接电性接触，连接良好，不易出现输接触不良的问题，提高了产品的良率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示现有技术中HADS阵列基板的结构示意图；
图2表示本发明实施例中底栅型薄膜晶体管HADS阵列基板的结构示意图；
图3表示本发明实施例中顶栅型薄膜晶体管HADS阵列基板的结构示意图；
图4表示本发明实施例中顶栅共面型薄膜晶体管HADS阵列基板的结构示意图；
图5-图9表示图2中HADS阵列基板的制作过程示意图。
具体实施方式
下面将结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
实施例一
结合图2-图4所示，本发明实施例中提供一种阵列基板的制作方法，所述阵列基板包括多个像素区域，所述制作方法包括：
提供一基底100；
在每一像素区域形成薄膜晶体管和像素电极1；
在所述薄膜晶体管的漏电极5和像素电极1之间形成绝缘层101，形成绝缘层101的步骤包括：
在绝缘层101中形成过孔，漏电极5和像素电极1通过所述过孔直接电性接触。
通过上述制作方法制得的阵列基板，薄膜晶体管的漏电极5和像素电极1通过过孔直接电性接触，连接良好，不易出现传输接触不良的问题，提高了产品的良率。
其中，漏电极5和像素电极1通过绝缘层101中的过孔直接电性接触是指：当漏电极5位于绝缘层101远离基底100的一侧时，绝缘层101中的过孔露出像素电极1的一部分，漏电极5的一部分填充所述过孔，与像素电极1电性接触。当漏电极5位于绝缘层101靠近基底100的一侧时，绝缘层101中的过孔露出的漏电极5一部分，像素电极1的一部分填充所述过孔，与漏电极5电性接触。
优选地，薄膜晶体管的漏电极5和像素电极1之间仅具有一个绝缘层101，则在绝缘层101中形成的过孔为浅孔(贯穿一个绝缘层的过孔深度较小，为浅孔)，不会出现深孔(贯穿多个绝缘层的过孔深度较大，为深孔)刻蚀中存在的过刻(undercut)问题，进一步保证漏电极5和像素电极1的传输接触良好。
本实施例中，薄膜晶体管的漏电极5和像素电极1之间的绝缘层101为栅绝缘层。
本发明的技术方案适用于所有类型的薄膜晶体管阵列基板，如：底栅型薄膜晶体管阵列基板(参加图2所示)、顶栅型薄膜晶体管阵列基板(参加图3所示)、顶栅共面型薄膜晶体管阵列基板(参加图4所示)。
当然，本发明的技术方案也同时适用于水平电场型阵列基板和垂直电场型阵列基板。
下面以HADS阵列基板为例来具体介绍本发明的技术方案。
如图2所示，对于底栅型薄膜晶体管阵列基板，为了简化制作工艺，通过一次构图工艺形成栅绝缘层101和薄膜晶体管的有源层6，则，HADS阵列基板的制作方法具体包括：
提供一基底100，为透明基底，如：玻璃基底、石英树脂基底、有机树脂基底；
在基底100上形成栅电极3和板状像素电极1，如图5所示；
形成覆盖栅电极3和像素电极1的栅绝缘层101，结合图6所示；
在栅绝缘层101上形成半导体层103，如图6所示，对半导体层103和栅绝缘层101进行一次构图工艺，形成薄膜晶体管的有源层6，并在栅绝缘层101中形成过孔7，露出像素电极1的一部分，如图8所示；
形成直接搭接在有源层6两端的源电极4和漏电极5，漏电极5的一部分填充过孔，并与像素电极1直接电性接触，如图9所示；
形成覆盖薄膜晶体管的钝化层102，参见图2所示；
在钝化层102上形成狭缝公共电极2，如图2所示。
至此完成底栅型薄膜晶体管阵列基板的制作。
可选的，钝化层102为有机膜层，厚度较厚，能够为阵列基板提供平坦的表面。
其中，结合图7和图8所示，对半导体层103和栅绝缘层101进行一次构图工艺的步骤具体包括：
在半导体层101上涂覆光刻胶，采用灰色调或半色调掩膜板对所述光刻胶进行曝光，形成光刻胶完全保留区域200、光刻胶部分保留区域201和光刻胶不保留区域，其中，光刻胶完全保留区域200对应有源层6所在的区域，光刻胶不保留区域对应栅绝缘层101中的过孔7所在的区域，光刻胶部分保留区域201对应其他区域；
去除光刻胶不保留区域的半导体层103和栅绝缘层101，形成过孔7；
通过灰化工艺去除光刻胶部分保留区域201的光刻胶，如图7所示；
去除光刻胶部分保留区域201的半导体层103；
剥离剩余的光刻胶，形成薄膜晶体管的有源层6，如图8所示。
如图3所示，对于顶栅型薄膜晶体管阵列基板，为了简化制作工艺，通过一次构图工艺形成栅绝缘层101和薄膜晶体管的栅电极3，则HADS阵列基板的制作方法具体包括：
提供一基底100，为透明基底，如：玻璃基底、石英树脂基底、有机树脂基底；
在基底100上形成源电极4和漏电极5；
形成有源层6，有源层6的两端分别直接搭接在源电极4和漏电极5上；
形成覆盖有源层6、源电极4和漏电极5的栅绝缘层101；
在栅绝缘层101上形成栅金属层，对栅绝缘层101和所述栅金属层进行一次构图工艺，形成薄膜晶体管的栅电极3，并在栅绝缘层101中形成过孔，露出漏电极5的一部分；
形成板状像素电极1，像素电极1的一部分填充栅绝缘层101中的过孔，并与漏电极5直接电性接触；
形成覆盖栅电极3和像素电极1的钝化层102；
在钝化层102上形成狭缝公共电极2。
至此完成顶栅型薄膜晶体管阵列基板的制作。
可选的，钝化层102为有机膜层，厚度较厚，能够为阵列基板提供平坦的表面。
其中，对栅绝缘层101和所述栅金属层进行一次构图工艺的步骤具体包括：
在所述栅金属层上涂覆光刻胶，采用灰色调或半色调掩膜板对所述光刻胶进行曝光，形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中，所述光刻胶完全保留区域对应所述栅电极所在的区域，所述光刻胶不保留区域对应所述过孔所在的区域，所述光刻胶部分保留区域对应其他区域；
去除所述光刻胶不保留区域的栅金属层和栅绝缘层，形成所述过孔；
通过灰化工艺去除所述光刻胶部分保留区域的光刻胶；
去除所述光刻胶部分保留区域的栅金属层；
剥离剩余的光刻胶，形成薄膜晶体管的栅电极。
如图4所示，对于顶栅共面型薄膜晶体管，为了简化制作工艺，通过一次构图工艺形成栅电极3和栅绝缘层101，则HADS阵列基板的制作方法具体包括：
提供一基底100，为透明基底，如：玻璃基底、石英树脂基底、有机树脂基底；
在基底100上形成薄膜晶体管的有源层6；
形成薄膜晶体管的源电极4和漏电极5，源电极4和漏电极5直接搭接在有源层6的两端；
形成覆盖有源层6、源电极4和漏电极5的栅绝缘层101；
在栅绝缘层101上形成栅金属层，对所述栅金属层和栅绝缘层101进行一次构图工艺，形成薄膜晶体管的栅电极3，并在栅绝缘层101中形成过孔，露出漏电极5的一部分；
形成板状像素电极1，像素电极1的一部分填充栅绝缘层101中的过孔，并与漏电极5直接电性接触；
形成覆盖栅电极3和像素电极1的钝化层102；
在钝化层102上形成狭缝公共电极2。
至此完成顶栅共面型薄膜晶体管阵列基板的制作。
可选的，钝化层102为有机膜层，厚度较厚，能够为阵列基板提供平坦的表面。
其中，对所述栅金属层和栅绝缘层101进行一次构图工艺的具体步骤与顶栅型薄膜晶体管阵列基板的步骤相同，在此不赘述。
本实施例中，薄膜晶体管的有源层6的材料可以选择硅半导体(可以选择多晶硅或非晶硅)或金属氧化物半导体(可以选择非晶HIZO、ZnO、TiO2、CdSnO、MgZnO、IGO、IZO、ITO或IGZO中的一种或多种)。栅电极3、源电极4和漏电极5的材料为Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo等。像素电极1和公共电极2的材料可以选择透明金属氧化物，如：HIZO、ZnO、TiO2、CdSnO、MgZnO、IGO、IZO、ITO或IGZO。
栅绝缘层101的材料可以选用有机材料或氧化物、氮化物或者氮氧化物等无机材料，可以为单层、双层或多层结构。优选地，栅绝缘层101为有机膜层，因为有机膜层的厚度大，在其上形成的过孔尺寸较大，使得漏电极5和像素电极1通过栅绝缘层101中的过孔具有较大的接触面积，保证接触良好。
本实施例中仅以底栅型薄膜晶体管阵列基板(参加图2所示)、顶栅型薄膜晶体管阵列基板(参加图3所示)、顶栅共面型薄膜晶体管阵列基板(参加图4所示)为例来具体介绍本发明的技术方案。需要说明的是，本发明的技术方案也适用于其他类型的阵列基板，只需设置薄膜晶体管的漏电极和像素电极之间仅具有一个绝缘层，在绝缘层中形成的过孔为浅孔，漏电极和像素电极通过所述过孔直接电性接触即可。
实施例二
基于同一发明构思，本实施例中提供一种由实施例一中的制作方法制得的阵列基板。
所述阵列基板包括多个像素区域，结合图2-图4所示，每一像素区域包括设置在一基底100上的薄膜晶体管和像素电极1。所述阵列基板还包括位于所述薄膜晶体管的漏电极5和像素电极1之间形成绝缘层101，绝缘层101中具有过孔，漏电极5和像素电极1通过所述过孔直接电性接触，连接良好，不易出现传输接触不良的问题，提高了产品的良率。
具体的，当漏电极5位于绝缘层101远离基底100的一侧时，绝缘层101中的过孔露出像素电极1的一部分，漏电极5的一部分填充所述过孔，与像素电极1电性接触。当漏电极5位于绝缘层101靠近基底100的一侧时，绝缘层101中的过孔露出的一部分，像素电极1的一部分填充所述过孔，与漏电极5电性接触。
优选地，薄膜晶体管的漏电极5和像素电极1之间仅具有一个绝缘层101，则在绝缘层101中形成的过孔为浅孔，不会出现深孔刻蚀中存在的过刻(undercut)问题，进一步保证漏电极5和像素电极1的传输接触良好。
本实施例中，薄膜晶体管的漏电极5和像素电极1之间的绝缘层101为栅绝缘层。
为了简化制作工艺，降低生产成本，具体的，栅绝缘层101可以和薄膜晶体管的有源层6由同一构图工艺制得，也可以和薄膜晶体管的栅电极3由同一构图工艺制得。例如：对于顶栅型薄膜晶体管阵列基板(参加图3所示)和顶栅共面型薄膜晶体管阵列基板(参加图4所示)，栅绝缘层101和薄膜晶体管的栅电极3由同一构图工艺制得(具体为栅绝缘层101中过孔与栅电极3由同一构图工艺制得)；对于底栅型薄膜晶体管阵列基板(参加图2所示)，栅绝缘层101和薄膜晶体管的有源层6由同一构图工艺制得(具体为栅绝缘层101中过孔与有源层6由同一构图工艺制得)。
优选地，栅绝缘层101为有机膜层，因为有机膜层的厚度大，在其上形成的过孔尺寸较大，使得漏电极5和像素电极1通过栅绝缘层101中的过孔具有较大的接触面积，保证接触良好。
下面以HADS阵列基板为例来具体介绍本发明的技术方案。
如图2所示，以底栅型薄膜晶体管阵列基板为例，本实施例中的HADS阵列基板具体包括：
基底100，为透明基底，如：玻璃基底、石英树脂基底、有机树脂基底；
设置在基底100上的板状像素电极1和薄膜晶体管的栅电极3；
覆盖像素电极1和栅电极3的栅绝缘层101，栅绝缘层101中具有过孔，露出像素电极1的一部分；
设置在栅绝缘层101上的薄膜晶体管的有源层6，栅绝缘层101中的过孔与有源层6可以由同一构图工艺制得；
薄膜晶体管的源电极4和漏电极5，源电极4和漏电极5直接搭接在有源层6上，且漏电极5的一部分填充栅绝缘层101中的所述过孔，与像素电极1电性接触；
覆盖整个基底100的钝化层102；
设置在钝化层101上的狭缝公共电极2。
至于，顶栅型薄膜晶体管阵列基板的具体结构参加图3所示，顶栅共面型薄膜晶体管阵列基板的具体结构参加图4所示，在此不再详述。其中，栅绝缘层101中的过孔与栅电极3可以由同一构图工艺制得。
当本发明的技术方案应用于其他类型的薄膜晶体管阵列基板时，只需设置薄膜晶体管的漏电极和像素电极之间仅具有一个绝缘层，在绝缘层中形成的过孔为浅孔，漏电极和像素电极通过所述过孔直接电性接触即可，其他结构与现有技术中相同。本领域所属技术人员很容易想到，可以根据本发明的技术方案对其他结构作合理调整，都属于本发明的保护范围。
实施例三
本实施例中提供一种显示面板和显示装置，所述显示面板和显示装置包括实施例二中的阵列基板，保证了漏电极和像素电极的电性连接良好，提高了产品的良率。
所述显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本发明的保护范围。

Claims (14)

1.一种阵列基板的制作方法，所述阵列基板包括多个像素区域，所述制作方法包括：
提供一基底；
在每一像素区域形成薄膜晶体管和像素电极；
在所述薄膜晶体管的漏电极和像素电极之间形成绝缘层，其特征在于，形成绝缘层的步骤包括：
在所述绝缘层中形成过孔，所述漏电极和像素电极通过所述过孔直接电性接触。
2.根据权利要求1所述的制作方法，其特征在于，所述绝缘层为栅绝缘层。
3.根据权利要求2所述的制作方法，其特征在于，通过一次构图工艺形成所述栅绝缘层和薄膜晶体管的有源层。
4.根据权利要求3所述的制作方法，其特征在于，通过一次构图工艺形成所述栅绝缘层和薄膜晶体管的有源层的步骤包括：
依次形成栅绝缘层和半导体层；
在所述半导体层上涂覆光刻胶，采用灰色调或半色调掩膜板对所述光刻胶进行曝光，形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中，所述光刻胶完全保留区域对应所述有源层所在的区域，所述光刻胶不保留区域对应所述过孔所在的区域，所述光刻胶部分保留区域对应其他区域；
去除所述光刻胶不保留区域的半导体层和栅绝缘层，形成所述过孔；
通过灰化工艺去除所述光刻胶部分保留区域的光刻胶；
去除所述光刻胶部分保留区域的半导体层；
剥离剩余的光刻胶，形成薄膜晶体管的有源层。
5.根据权利要求3所述的制作方法，其特征在于，所述薄膜晶体管为底栅型薄膜晶体管，所述制作方法具体包括：
提供一基底；
在所述基底上形成板状像素电极和薄膜晶体管的栅电极；
形成覆盖所述像素电极和栅电极的栅绝缘层；
在所述绝缘层上形成半导体层，对所述半导体层和栅绝缘层进行一次构图工艺，形成薄膜晶体管的有源层，并在所述栅绝缘层中形成过孔，露出所述像素电极的一部分；
形成薄膜晶体管的源电极和漏电极，所述源电极和漏电极直接搭接在所述有源层上，且所述漏电极的一部分填充所述过孔，与像素电极电性接触；
形成覆盖整个所述基底的钝化层；
在所述钝化层上形成狭缝公共电极。
6.根据权利要求2所述的制作方法，其特征在于，通过一次构图工艺形成所述栅绝缘层和薄膜晶体管的栅电极。
7.根据权利要求6所述的制作方法，其特征在于，通过一次构图工艺形成所述栅绝缘层和薄膜晶体管的栅电极的步骤包括：
依次形成栅绝缘层和栅金属层；
在所述栅金属层上涂覆光刻胶，采用灰色调或半色调掩膜板对所述光刻胶进行曝光，形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中，所述光刻胶完全保留区域对应所述栅电极所在的区域，所述光刻胶不保留区域对应所述过孔所在的区域，所述光刻胶部分保留区域对应其他区域；
去除所述光刻胶不保留区域的栅金属层和栅绝缘层，形成所述过孔；
通过灰化工艺去除所述光刻胶部分保留区域的光刻胶；
去除所述光刻胶部分保留区域的栅金属层；
剥离剩余的光刻胶，形成薄膜晶体管的栅电极。
8.一种阵列基板，包括多个像素区域，每一像素区域包括设置在一基底上的薄膜晶体管和像素电极，所述阵列基板还包括位于所述薄膜晶体管的漏电极和像素电极之间形成绝缘层，其特征在于，所述绝缘层中具有过孔，所述漏电极和像素电极通过所述过孔直接电性接触。
9.根据权利要求8所述的阵列基板，其特征在于，所述绝缘层为栅绝缘层。
10.根据权利要求9所述的阵列基板，其特征在于，所述栅绝缘层和薄膜晶体管的有源层由同一构图工艺制得。
11.根据权利要求10所述的阵列基板，其特征在于，所述薄膜晶体管为底栅型薄膜晶体管，所述阵列基板具体包括：
基底；
设置在所述基底上的板状像素电极和薄膜晶体管的栅电极；
覆盖所述像素电极和栅电极的栅绝缘层，所述栅绝缘层中具有过孔，露出所述像素电极的一部分；
设置在所述栅绝缘层上的薄膜晶体管的有源层；
薄膜晶体管的源电极和漏电极，所述源电极和漏电极直接搭接在所述有源层上，且所述漏电极的一部分填充所述过孔，与像素电极电性接触；
覆盖整个所述基底的钝化层；
设置在所述钝化层上的狭缝公共电极。
12.根据权利要求9所述的阵列基板，其特征在于，所述栅绝缘层和薄膜晶体管的栅电极由同一构图工艺制得。
13.一种显示面板，其特征在于，包括权利要求8-12任一项所述的阵列基板。
14.一种显示装置，其特征在于，包括权利要求8-12任一项所述的阵列基板。
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