WO2017054250A1 - 一种tft阵列基板及其制作方法 - Google Patents

一种tft阵列基板及其制作方法 Download PDF

Info

Publication number
WO2017054250A1
WO2017054250A1 PCT/CN2015/091440 CN2015091440W WO2017054250A1 WO 2017054250 A1 WO2017054250 A1 WO 2017054250A1 CN 2015091440 W CN2015091440 W CN 2015091440W WO 2017054250 A1 WO2017054250 A1 WO 2017054250A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor pattern
substrate
electrode
mask
Prior art date
Application number
PCT/CN2015/091440
Other languages
English (en)
French (fr)
Inventor
葛世民
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/786,459 priority Critical patent/US20170162708A1/en
Publication of WO2017054250A1 publication Critical patent/WO2017054250A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13625—Patterning using multi-mask exposure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate and a method of fabricating the same.
  • the active matrix driven LCD display technology utilizes the bipolar polarization characteristics of the liquid crystal, and controls the alignment direction of the liquid crystal molecules by applying an electric field, thereby realizing the switching effect on the traveling direction of the backlight optical path.
  • the LCD display mode can be divided into TN.
  • VA and IPS series mode refers to applying a longitudinal electric field to liquid crystal molecules
  • the IPS series mode refers to applying a transverse electric field to liquid crystal molecules.
  • the IPS series mode for the application of the transverse electric field, it can be divided into the IPS mode and the FFS mode.
  • Each pixel unit of the FFS display mode includes two upper and lower electrodes, that is, a pixel electrode and a common electrode, and the common electrode of the lower layer is flattened on the entire surface of the open area.
  • the FFS display mode has a high transmittance, wide viewing angle and low color shift, and is a widely used LCD display technology.
  • a Single-gate TFT (single-gate thin film transistor) is often used, but a Dual gate TFT (Double Gate Transistor) and Single-gate Compared with TFT (single-gate thin film transistor), it has not only high mobility, large on-state current, smaller subthreshold swing, threshold voltage (Vth) stability and uniformity, but also Better gate bias stability.
  • the traditional FFS display mode Dual-Gate The TFT array substrate manufacturing method requires more mask times, which increases the complexity of the process and the production cost.
  • the present invention provides a TFT array substrate and a method of fabricating the same, which can reduce the number of masks, improve production efficiency, and reduce production costs.
  • the present invention provides a method for fabricating a TFT array substrate, including:
  • first transparent metal oxide conductor layer and a first metal layer on the substrate in sequence, and etching the first metal layer and the first transparent metal oxide conductor layer into a bottom gate electrode and a common electrode by using a first mask process, wherein
  • the bottom gate electrode is a laminated structure of the first metal layer and the first transparent metal oxide conductor layer
  • the common electrode is a single layer structure of the first transparent metal oxide conductor layer, wherein the first mask adopts a halftone mask, Any of a gray tone mask or a single slit mask;
  • the pixel electrode and the common electrode are at least partially overlapped and electrically connected to one of the source electrode and the drain electrode through the via hole.
  • the step of further forming a semiconductor layer and a second metal layer on the substrate, and etching the semiconductor layer and the second metal layer into a semiconductor pattern and a source electrode and a drain electrode at both ends of the semiconductor pattern by using a second mask process include:
  • the second mask adopts any one of a halftone mask, a gray tone mask or a single slit mask.
  • the invention also provides a method for fabricating a TFT array substrate, comprising: providing a substrate, sequentially forming a first transparent metal oxide conductor layer and a first metal layer on the substrate, and adopting a first mask process to form the first metal layer And the first transparent metal oxide conductor layer is etched into a bottom gate electrode and a common electrode, wherein the bottom gate electrode is a stacked structure of the first metal layer and the first transparent metal oxide conductor layer, and the common electrode is the first transparent metal oxide A single layer structure of the conductor layer.
  • the first mask adopts any one of a halftone mask, a gray tone mask or a single slit mask.
  • the method further includes: further forming a gate insulating layer on the substrate; further forming a semiconductor layer on the substrate, and etching the semiconductor layer into a semiconductor pattern by using a second mask process, wherein the semiconductor pattern is located above the bottom gate electrode; Further forming a second metal layer, and etching the second metal layer into a source electrode and a drain electrode at both ends of the semiconductor pattern by using a third mask process; further forming a first passivation layer on the substrate, and adopting a fourth mask
  • the first passivation layer is etched to form a via; a second transparent metal oxide conductor layer is further formed on the substrate, and the second transparent metal oxide conductor layer is etched into a top gate electrode and a fifth mask process a pixel electrode, wherein the top gate electrode is located above the semiconductor pattern, and the pixel electrode and the common electrode are at least partially overlapped and electrically connected to one of the source electrode and the drain electrode through the via hole.
  • a semiconductor layer is further formed on the substrate, and the semiconductor layer is etched into a semiconductor pattern by a second mask process and a second metal layer is further formed on the substrate, and the second metal layer is etched by a third mask process.
  • the method further comprises: forming an etch stop layer on the substrate, and etching the etch stop layer to form the semiconductor pattern by using a sixth mask process; and the step of forming the source electrode and the drain electrode at the two ends of the semiconductor pattern The etch stop layer at both ends is via.
  • the method further includes: further forming a gate insulating layer on the substrate; further forming a semiconductor layer and a second metal layer on the substrate, and etching the semiconductor layer and the second metal layer into a semiconductor pattern by using a second mask process a source electrode and a drain electrode at two ends of the semiconductor pattern, wherein the semiconductor pattern is located above the bottom gate electrode; a first passivation layer is further formed on the substrate, and the first passivation layer is etched by a third mask process to form a via hole; Forming a second transparent metal oxide conductor layer on the substrate, and etching the second transparent metal oxide conductor layer into a top gate electrode and a pixel electrode by using a fourth mask process, wherein the top gate electrode is located above the semiconductor pattern, The pixel electrode and the common electrode are at least partially overlapped and electrically connected to one of the source electrode and the drain electrode through the via hole.
  • the semiconductor layer and the second metal layer are further formed on the substrate, and the step of etching the semiconductor layer and the second metal layer into a semiconductor pattern and the source electrode and the drain electrode at both ends of the semiconductor pattern by using a second mask process include: Further forming an intrinsic semiconductor layer, a doped semiconductor layer and a second metal layer on the substrate, and etching the intrinsic semiconductor layer to a semiconductor pattern by using a second mask process, etching the doped semiconductor layer into an intrinsic semiconductor pattern A first doped semiconductor pattern and a second doped semiconductor pattern at both ends, and the second metal layer is etched into a drain electrode and a source electrode respectively above the first doped semiconductor pattern and the second doped semiconductor pattern.
  • the second mask adopts any one of a halftone mask, a gray tone mask or a single slit mask.
  • the present invention further provides an array substrate comprising: a substrate; a bottom gate electrode and a common electrode formed on the substrate, wherein the bottom gate electrode and the common electrode are formed by the same photomask process, and the bottom gate electrode is A laminated structure of a metal layer and a first transparent metal oxide conductor layer, the common electrode being a single layer structure of the first transparent metal oxide conductor layer.
  • the substrate further includes a semiconductor pattern over the bottom gate electrode and source and drain electrodes at both ends of the semiconductor pattern, wherein the semiconductor pattern and the source and drain electrodes are formed by another varnish process.
  • the semiconductor pattern includes: an intrinsic semiconductor pattern and a first doped semiconductor pattern and a second doped semiconductor pattern at both ends of the intrinsic semiconductor pattern, wherein the drain electrode and the source electrode are respectively located in the first doped semiconductor pattern and the second doping Above the semiconductor pattern.
  • the beneficial effects of the present invention are: different from the prior art, the bottom gate electrode of the TFT array substrate of the present invention is a laminated structure of a metal layer and a metal oxide conductor layer, and the common electrode is a metal oxide conductor layer.
  • the single-layer structure, and the bottom gate electrode and the common electrode are formed on the substrate by the same mask process. Therefore, the TFT array substrate of the present invention can reduce the number of times of the mask, improve the production efficiency, and reduce the production cost.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate of the present invention
  • 2A to 2F are process flow diagrams of fabricating a bottom gate electrode and a common electrode in the first embodiment of the TFT array substrate of FIG. 1;
  • FIG. 3 is a schematic diagram showing the principle of light transmission of the first photomask in the first embodiment of the TFT array substrate of FIG. 1;
  • FIG. 4 is a schematic view showing a process of forming a semiconductor pattern by a second mask process of the TFT array substrate of FIG. 1;
  • FIG. 5 is a schematic view showing a process of forming a source electrode and a drain electrode by a third mask process of the TFT array substrate of FIG. 1;
  • FIG. 6 is a schematic view showing a process of forming a via hole in a fourth photomask process of the TFT array substrate of FIG. 1;
  • FIG. 7 is a schematic structural view of a TFT array substrate obtained by the first embodiment of the method for fabricating the TFT array substrate of FIG. 1;
  • FIG. 8 is a schematic flow chart of a second embodiment of a method for fabricating a TFT array substrate of the present invention.
  • FIG. 9 is a schematic structural view of a TFT array substrate obtained by the second embodiment of the method for fabricating the TFT array substrate of FIG. 8;
  • FIG. 10 is a schematic flow chart of a third embodiment of a method for fabricating a TFT array substrate of the present invention.
  • FIG. 11A to FIG. 11D are schematic diagrams showing a process of fabricating a semiconductor pattern, a source electrode, and a drain electrode in a third embodiment of the method for fabricating the TFT array substrate of FIG. 10;
  • FIG. 12 is a schematic view showing the structure of a TFT array substrate obtained by the third embodiment of the method for fabricating the TFT array substrate of FIG.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate according to the present invention. As shown in FIG. 1 , a method for fabricating a TFT array substrate of the present embodiment includes:
  • S12 sequentially forming a first transparent metal oxide conductor layer and a first metal layer on the substrate, and etching the first metal layer and the first transparent metal oxide conductor layer into a bottom gate electrode and a common electrode by using a first mask process .
  • the substrate serves as a substrate, which may be a glass substrate, a plastic substrate or a substrate of another suitable material.
  • the substrate is preferably a glass substrate having a light transmitting property.
  • FIG. 2A to FIG. 2F are process flowcharts for fabricating a bottom gate electrode and a common electrode in the first embodiment of the TFT array substrate of FIG. 1.
  • a first transparent metal oxide conductor layer 110 and a first metal layer 120 are sequentially formed on the substrate 100 by physical vapor deposition (PVD), and the first metal layer 120 covers the first transparent metal oxide.
  • PVD physical vapor deposition
  • the material of the first metal oxide conductor layer 110 includes, but is not limited to, ITO (English: Indium) Tin Oxide, Chinese: indium tin oxide, ITO is a metal oxide with good electrical conductivity and transparency.
  • Materials of the first metal layer 120 include, but are not limited to, chromium, aluminum, titanium, or other metallic materials.
  • the substrate 100 having the first metal layer 120 and the first transparent metal oxide conductor layer 110 is exposed using the first photomask 10.
  • a photoresist layer (not shown) is covered on the first metal layer 120 in advance, and the first mask 10 is a halftone mask (Halt-tone).
  • Mask referred to as HTM
  • Gray-tone Mask GTM
  • Single Slit Mask Single slit
  • the first photomask 10 includes a light transmitting portion 101, a semi-transmissive portion 102, and an opaque portion 103.
  • the photoresist layer After exposing the substrate 100 having the first metal layer 120 and the first transparent metal oxide conductor layer 110 by using the first mask 10, the photoresist layer is completely exposed corresponding to the region of the light transmitting portion 101 of the first mask 10, corresponding to The area of the semi-transmissive portion 102 of the first mask 10 is half-exposed, and the area corresponding to the opaque portion 103 of the first mask 10 is not exposed. Therefore, after the process of exposing, half-exposure, non-exposure, and developing the photoresist layer by using the first mask 10, the first photoresist portion 1030 and the second photoresist portion 1020 are respectively obtained, wherein the first photoresist portion 1030 is obtained. The thickness is greater than the thickness of the second photoresist portion 1020.
  • the first photoresist portion 1030 corresponds to the opaque portion 103 of the first reticle 10
  • the second photoresist portion 1020 corresponds to the semi-transmissive portion 102 of the first reticle 10. .
  • the first metal layer 120 and the region of the first metal oxide conductor layer 110 not covered by the first photoresist portion 1030 and the second photoresist portion 1020 are further wet-etched for the first time, and there will be no The first metal layer 120 and the first metal oxide conductor layer 110 covered by the first photoresist portion 1030 and the second photoresist portion 1020 are removed.
  • the first photoresist portion 1030 and the second photoresist portion 1020 are ashed using oxygen so that the second photoresist portion 1020 having a thin thickness is removed and covered by the second photoresist portion 1020.
  • the first metal layer 120 is exposed.
  • the first photoresist portion 1030 retains a portion of the photoresist.
  • the exposed first metal layer 120 is further wet-etched so that only the first transparent metal oxide conductor layer 110 remains as the common electrode 11, and the common electrode 11 is the first transparent metal oxide conductor.
  • the layer 110 is formed in a single layer structure.
  • the remaining photoresist of the first photoresist portion 1030 is peeled off, so that the bottom gate electrode 12 is formed by the stacked structure of the remaining first metal layer 120 and the first transparent metal oxide conductor layer 110. Therefore, the bottom gate electrode 12 and the common electrode 11 can be simultaneously formed only by the same mask process.
  • FIG. 3 is a schematic diagram showing the principle of light transmission of the first photomask in the first embodiment of the TFT array substrate of FIG.
  • the first photomask 10, the light intensity curve 70, and the structure in which the bottom gate electrode 12 and the common electrode 11 are formed on the substrate 100 are collectively illustrated in FIG.
  • the first photomask 10 includes a light transmitting portion 101, a semi-transmissive portion 102, and an opaque portion 103.
  • the opaque portion 103 corresponds to a region of the bottom gate electrode 12, and the semi-transmissive portion 102 corresponds to In the region of the common electrode 11, the light transmitting portion 101 corresponds to other regions except the bottom gate electrode 12 and the common electrode 11.
  • the first upward convex portion 703 of the light intensity curve 70 corresponds to the opaque portion 103 of the first reticle 10, indicating that the light intensity is the weakest at this time.
  • the second upward convex portion 702 of the light intensity curve 70 corresponds to the semi-light transmitting portion 102 of the first reticle 10, wherein the first upward convex portion 703 corresponds to the illumination intensity corresponding to the second upward convex portion 702.
  • the intensity, and the corresponding light intensity of the first upward convex portion 703 and the light intensity corresponding to the second upward convex portion 702 are smaller than the light intensity of the other regions.
  • the thickness of the first photoresist portion 1030 corresponding to the bottom gate electrode 12 is made larger than the thickness of the second photoresist portion 1020 corresponding to the common electrode 11, thereby passing
  • the bottom gate electrode 12 and the common electrode 11 are obtained by a further wet etching method, a photoresist oxygen ashing method, etc., and therefore, the bottom gate electrode 12 and the common electrode 11 can be simultaneously formed by the same mask process.
  • the first transparent metal oxide conductor layer 110 and the first metal layer 120 are exposed, half exposed, and unexposed to form the bottom gate electrode 12 and the common electrode 11 by using the first mask 10.
  • the structure of the first reticle 10 is determined.
  • S14 further forming a semiconductor layer on the substrate, and etching the semiconductor layer into a semiconductor pattern by using a second photomask process.
  • a gate insulating layer 130 is formed on the substrate 100.
  • the gate insulating layer 130 covers the bottom gate electrode 12 and the common electrode 11 and extends onto the substrate 100.
  • the gate insulating layer 130 can be formed by chemical vapor deposition.
  • the material of the gate insulating layer 130 includes, but is not limited to, silicon nitride, silicon oxide or silicon oxynitride.
  • a semiconductor layer (not shown) is further formed over the gate insulating layer 130, and the semiconductor layer can be formed by a deposition method.
  • the material of the semiconductor layer is preferably IGZO (Indium Gallium) Zinc Oxide), an amorphous metal oxide containing indium, gallium and zinc, is a channel layer material used in next-generation thin film transistor technology.
  • the carrier mobility of IGZO is 20 to 30 times that of amorphous silicon. It can greatly improve the charging and discharging rate of the TFT to the pixel electrode, improve the response speed of the pixel, achieve a faster refresh rate, and at the same time, the faster response also greatly improves the line scanning rate of the pixel, so that the ultra-high resolution is in the TFT-LCD.
  • IGZO displays have higher energy efficiency levels and higher efficiency due to the reduction in the number of transistors and the improvement of the transmittance of each pixel.
  • IGZO can be produced using existing amorphous silicon production lines. With minor modifications, IGZO is more competitive than low-temperature polysilicon in terms of cost.
  • a photoresist layer (not shown) is further coated on the semiconductor layer, and the photoresist layer is exposed by a second mask (not shown), and the second mask includes a light transmitting portion and an opaque portion, thereby After the process of exposure development etching or the like is performed through the second mask process, the semiconductor layer corresponding to the light transmitting portion of the second mask is etched away, leaving a semiconductor layer corresponding to the impermeable portion of the second mask to form a semiconductor.
  • the pattern 14, that is, the semiconductor pattern 14 is formed of a semiconductor layer corresponding to the opaque portion of the second mask, because it is left unexposed by exposure etching.
  • the semiconductor pattern 14 is located above the bottom gate electrode 12.
  • the method of fabricating the semiconductor pattern 14 from the semiconductor layer employs a prior art method, and will not be described in detail herein.
  • S15 further forming a second metal layer on the substrate, and etching the second metal layer into a source electrode and a drain electrode at both ends of the semiconductor pattern by using a third mask process.
  • a second metal layer (not shown) is further formed on the substrate 100, and the second metal layer is exposed by a third mask (not shown) and subjected to development etching.
  • the source electrode 16 and the drain electrode 15 at both ends of the semiconductor pattern 14 are formed by using a third mask to form the source electrode 16 and the drain electrode 15.
  • the prior art process is used, and no further details are provided herein.
  • S16 further forming a first passivation layer on the substrate, and etching the first passivation layer by using a fourth mask process to form via holes.
  • a first passivation layer 160 is further formed on the substrate 100.
  • the first passivation layer 160 covers the source and drain electrodes 16, and 15 and the semiconductor pattern 14 and extends onto the gate insulating layer 130.
  • a fourth mask (not shown)
  • the region corresponding to the first passivation layer 160 above the source electrode 16 or the drain electrode 15 is formed.
  • Hole 17. Among them, the method of forming the via hole 17 adopts the prior art method, and will not be described in detail herein.
  • S17 further forming a second transparent metal oxide conductor layer on the substrate, and etching the second transparent metal oxide conductor layer into a top gate electrode and a pixel electrode by using a fifth mask process.
  • FIG. 7 is a schematic structural view of a TFT array substrate obtained by the first embodiment of the method for fabricating the TFT array substrate of FIG. 1, and the embodiment of steps S17 to S18 is described with reference to FIG.
  • a second transparent metal oxide conductor layer (not shown) is further formed on the first passivation layer 160 of the substrate 100.
  • the material of the second transparent metal oxide conductor layer is the same material as the common electrode 11, that is, The material of the second transparent metal oxide conductor layer is also an ITO oxide.
  • the second transparent metal oxide conductor layer is exposed by a fifth mask (not shown) and developed and etched to form a top gate electrode 19 and a plurality of pixel electrodes 18.
  • the top gate electrode 19 is located above the semiconductor pattern 14 and is disposed corresponding to the bottom gate electrode 12.
  • the pixel electrode 18 and the common electrode 11 are at least partially overlapped, and one of the pixel electrodes 18 is electrically connected to one of the source electrode 16 and the drain electrode 15 through the via hole 17. As shown in FIG. 7, one pixel electrode 18 is connected to the source electrode 16 through the via hole 17, and the remaining pixel electrodes 18 are spaced apart above the common electrode 11.
  • a second passivation layer 180 is further formed on the substrate 100, and the second passivation layer 180 covers the pixel electrode 18, the top gate electrode 19, and extends onto the first passivation layer 160.
  • the method for fabricating the pixel electrode 18 and the top gate electrode 19 from the second transparent metal oxide conductor layer and further covering the second passivation layer 180 is a prior art method, and will not be described in detail herein.
  • the TFT array substrate 1 obtained by the above embodiment includes the substrate 100, the bottom gate electrode 12 and the common electrode 11 formed on the substrate 100, the gate insulating layer 130, the semiconductor pattern 14, the drain electrode 15, and the source electrode 16, The first passivation layer 160, the pixel electrode 18, the top gate electrode 19, and the second passivation layer 180.
  • the bottom gate electrode 12 and the common electrode 11 are formed by the same photomask process, and the bottom gate electrode 12 is a stacked structure of the first metal layer 120 and the first transparent metal oxide conductor layer 110, and the common electrode 11 is first transparent.
  • the gate insulating layer 130 covers the bottom gate electrode 12 and the common electrode 11 and extends onto the substrate 100.
  • the semiconductor pattern 14 is located above the bottom gate electrode 12, and the drain electrode 15 and the source electrode 16 are respectively located at both ends of the semiconductor pattern 14.
  • the first passivation layer 160 covers the drain electrode 15 and the source electrode 16, the semiconductor pattern 14 and extends onto the gate insulating layer 130, and the region of the first passivation layer 160 corresponding to the source electrode 16 or the drain electrode 15 is also formed.
  • the via 17, the via 17 shown in FIG. 7 is located above the source electrode 16, which is used to electrically connect the source electrode 16 with the pixel electrode 18, and the pixel electrode 18 at least partially overlaps the common electrode 11, the top gate electrode 19 is disposed opposite to the bottom gate electrode 12.
  • the second passivation layer 180 covers the top gate electrode 19 and the pixel electrode 18 and extends onto the first passivation layer 160.
  • the TFT array substrate 1 is BCE (English: Back Channel Etch, Chinese: Array substrate of back channel etch structure) structure.
  • the TFT array substrate of the present embodiment may sequentially form a metal layer and a transparent metal oxide conductor layer on the substrate, and then form a bottom gate electrode and a common electrode on the substrate by the same mask process to make the metal layer and the transparent metal.
  • the stacked structure of the oxide conductor layer forms a bottom gate electrode, and the single layer structure of the transparent metal oxide conductor layer forms a common electrode, whereby the number of masks for fabricating the TFT array substrate can be reduced, the production efficiency is improved, and the production cost is lowered.
  • FIG. 8 is a schematic flow chart of a second embodiment of a method for fabricating a TFT array substrate according to the present invention. As shown in FIG. 8, the manufacturing method of the TFT array substrate of this embodiment includes:
  • S22 sequentially forming a first transparent metal oxide conductor layer and a first metal layer on the substrate, and etching the first metal layer and the first transparent metal oxide conductor layer into a bottom gate electrode and a common electrode by using a first mask process .
  • S24 further forming a semiconductor layer on the substrate, and etching the semiconductor layer into a semiconductor pattern by using a second mask process.
  • S25 further forming an etch barrier layer on the substrate, and etching the etch barrier layer by a sixth mask process to form etch barrier via holes at both ends of the semiconductor pattern.
  • S26 further forming a second metal layer on the substrate, and etching the second metal layer into a source electrode and a drain electrode at both ends of the semiconductor pattern by using a third photomask process.
  • S27 further forming a first passivation layer on the substrate, and etching the first passivation layer by using a fourth mask process to form via holes.
  • S28 further forming a second transparent metal oxide conductor layer on the substrate, and etching the second transparent metal oxide conductor layer into a top gate electrode and a pixel electrode by using a fifth mask process.
  • FIG. 9 is a schematic structural view of a TFL array substrate prepared by the second embodiment of the method for fabricating the TFT array substrate of FIG.
  • the etch stop layer 210 covers the semiconductor pattern 14 and extends onto the gate insulating layer 130.
  • the etch barrier layer 210 is exposed and developed by an etching process using a sixth mask (not shown), and the etch barrier layer 210 is exposed and etched in a region at both ends of the semiconductor pattern 14 to form an etch stop via hole 20, engraved.
  • the etch barrier via 20 is for electrically connecting the source electrode 16 and the drain electrode 15 to the semiconductor pattern 14.
  • the function of the etch barrier layer 210 is to protect the semiconductor pattern 14 from corrosion during the process of forming the source electrode 16 and the drain electrode 15. Steps S26 to S29 are similar to steps S15 to S18 of the foregoing embodiment, and details are not described herein again.
  • the TFL array substrate 2 of the present embodiment is an ESL (English: Etch stopper
  • ESL Electronic Standard Etch stopper
  • the structure of the array substrate of the present embodiment is different from that of the array substrate 1 of the BCE structure shown in FIG. 7 in that the TFL array substrate 2 is different from the array substrate 1 of the BCE structure shown in FIG.
  • an etch stop layer 210 over the semiconductor 14 the etch stop layer 210 is formed with etch stop vias 20 corresponding to regions at both ends of the semiconductor pattern 14 such that the source and drain electrodes 15 and the drain electrodes 15 are located at opposite ends of the semiconductor pattern 14.
  • the semiconductor pattern 14 is electrically connected by etching the barrier via 20 .
  • the array substrate process of the present embodiment is similar to the process of the above embodiment, which can reduce the number of masks, improve production efficiency, and reduce production cost, and can also avoid forming a drain electrode by etching by providing an etch barrier layer.
  • the semiconductor pattern is erroneously etched with the source electrode.
  • FIG. 10 is a schematic flow chart of a third embodiment of a method for fabricating a TFT array substrate according to the present invention. As shown in FIG. 10, the method for fabricating the TFT array substrate of the present embodiment includes:
  • S32 sequentially forming a first transparent metal oxide conductor layer and a first metal layer on the substrate, and etching the first metal layer and the first transparent metal oxide conductor layer into a bottom gate electrode and a common electrode by using a first mask process .
  • the steps S31 to S33 are similar to the steps S11 to S13 of the first embodiment, and are not described herein again.
  • S34 further forming a semiconductor layer and a second metal layer on the substrate, and etching the semiconductor layer and the second metal layer into a semiconductor pattern and a source electrode and a drain electrode at both ends of the semiconductor pattern by using a second mask process.
  • FIG. 11A to FIG. 11D are schematic diagrams showing a process of fabricating a semiconductor pattern, a source electrode and a drain electrode in a third embodiment of the method for fabricating the TFT array substrate of FIG. 10 .
  • the semiconductor layer 140 is used for etching to form the semiconductor pattern 14
  • the second metal layer 150 is used for etching to form the source electrode 16 and the drain electrode 15 located at both ends of the semiconductor pattern 14, and the semiconductor pattern 14 is located at the bottom gate electrode 12.
  • the semiconductor layer 140 is used for etching to form the semiconductor pattern 14
  • the second metal layer 150 is used for etching to form the source electrode 16 and the drain electrode 15 located at both ends of the semiconductor pattern 14
  • the semiconductor pattern 14 is located at the bottom gate electrode 12.
  • the semiconductor pattern 14 is located at the bottom gate electrode 12.
  • the semiconductor layer 140 includes an intrinsic semiconductor layer 190 and a doped semiconductor layer 200.
  • the intrinsic semiconductor layer 190 and the doped semiconductor layer 200 are successively deposited on the substrate 10 by chemical vapor deposition (CVD).
  • the intrinsic semiconductor layer 190 is an a-Si (amorphous silicon) layer
  • the doped semiconductor layer 200 is an n+a-Si layer
  • the n+a-Si layer is a high concentration doped N-type amorphous silicon conductive layer.
  • a second metal layer 150 is further deposited on the substrate 100 using a PVD method.
  • the second metal layer 150 is the same as the material of the first embodiment, and may be a metal material such as aluminum, chromium, molybdenum or titanium.
  • a photoresist layer (not shown) on the second metal layer 150, exposing and developing the photoresist layer by using a second mask, the second mask being similar in structure to the first mask, and also using halftone Any of a mask, a gray tone mask, or a single slit mask.
  • a photoresist pattern 21 is obtained, as shown in FIG. 11C.
  • the region of the second metal layer 150 not covered by the photoresist pattern 21 is wet-etched, and then the intrinsic semiconductor layer 190 not covered by the photoresist pattern 21 and the region corresponding to the doped semiconductor layer 200 are removed by dry etching.
  • the photoresist pattern 21 is subjected to ashing treatment by using oxygen, and the photoresist at a thin position at the channel of the photoresist pattern 21 is removed, and the photoresist pattern 21 retains a certain thickness of photoresist at a thick position, which is referred to as post-production.
  • the corresponding positions above the source electrode 16 and the drain electrode 15 retain a certain thickness of photoresist.
  • the second metal layer 150 not covered by the photoresist is further removed by wet etching, and the doped semiconductor layer 200 not covered by the photoresist is removed by dry etching and a small portion of the intrinsic semiconductor layer 190 is removed, and the remaining portions are removed.
  • the photoresist is such that the structure shown in FIG.
  • the semiconductor pattern 14 is composed of an intrinsic semiconductor pattern 22 and first and second doped semiconductor patterns 23 and 24 respectively located at both ends of the intrinsic semiconductor pattern 22.
  • S35 further forming a first passivation layer on the substrate, and etching the first passivation layer by using a third mask process to form via holes.
  • S36 further forming a second transparent metal oxide conductor layer on the substrate, and etching the second transparent metal oxide conductor layer into a top gate electrode and a pixel electrode by using a fourth mask process.
  • FIG. 12 is a schematic structural view of a TFT array substrate obtained by the third embodiment of the method for fabricating the TFT array substrate of FIG.
  • the steps S35 to S37 are similar to the steps S16 to S18 of the above embodiment, and are not described herein again.
  • the structure of the TFT array substrate 3 of the present embodiment is different from the structure of the TFT array substrate 1 of the first embodiment in that the present embodiment is composed of the intrinsic semiconductor pattern 22, and the first incorporation of the intrinsic semiconductor pattern 22 is also provided.
  • the semiconductor pattern 23 and the second doped semiconductor pattern 24 are substituted for the semiconductor pattern 14 shown in FIG. 7 of the first embodiment, and the drain electrode 15 in the embodiment shown in FIG. 12 is located above the first doped semiconductor pattern 23.
  • the source electrode 16 is located above the second doped semiconductor pattern 24.
  • the TFT array substrate of the present embodiment can form a bottom gate electrode and a common electrode on the substrate through the same mask process, and form a semiconductor pattern and source and drain electrodes at both ends of the semiconductor pattern through the same mask process, wherein the semiconductor The pattern is composed of a semi-signal semiconductor pattern and a first doped semiconductor pattern and a second doped semiconductor pattern at both ends of the semi-symmetric semiconductor pattern, and the drain electrode and the source electrode are respectively located above the first doped semiconductor pattern and the second doped semiconductor pattern Therefore, the TFT array substrate of the present embodiment requires only four mask processes, reducing the number of masks, improving production efficiency, and reducing production costs.
  • the TFT array substrate of the present invention can form a bottom gate electrode formed of a metal layer and a transparent metal oxide conductor layer on the substrate by a photomask process and a transparent metal oxide.
  • the common electrode formed by the conductor layer so that the process of the array substrate can reduce the number of masks, improve production efficiency, and reduce production cost.

Abstract

一种TFT阵列基板及其制作方法，TFT阵列基板通过同一道光罩工艺在基板（100）上形成底栅电极（12）及公共电极（11），其中底栅电极（12）为金属层（120）与金属氧化物导体层（110）的叠层结构，公共电极（11）为金属氧化物导体层（110）的单层结构，从而能够减少光罩次数，提高生产效率和降低生产成本。

Description

一种TFT阵列基板及其制作方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种TFT阵列基板及其制作方法。
【背景技术】
有源矩阵驱动的LCD显示技术利用了液晶的双极性偏振特点，通过施加电场控制液晶分子的排列方向，实现对背光源光路行进方向的开关作用。根据对液晶分子施加电场方向的不同，可以将LCD显示模式分为TN, VA及IPS系列模式。VA系列模式指对液晶分子施加纵向电场，而IPS系列模式指对液晶分子施加横向电场。而在IPS系列模式中，对于施加横向电场的不同，又可分为IPS模式和FFS模式等。其中FFS显示模式的每一个像素单元含有上下两层电极，即像素电极和公共电极，且下层的公共电极采用开口区整面平铺的方式。FFS显示模式具有高透过率，广视角以及较低的色偏等优点，是一种广泛应用的LCD显示技术。
在有源阵列显示装置中，常采用的是Single-gate TFT（单栅极薄膜晶体管），但是Dual gate TFT（双栅极晶体管）与Single-gate TFT（单栅极薄膜晶体管）相比，不仅具有较高的迁移率，较大的开态电流，更小的亚阈值摆幅，阈值电压（Vth）稳定性和均匀性好等优点，还具有更好的栅极偏压稳定性。然而，传统的FFS显示模式的Dual-Gate TFT阵列基板制造方法需要更多的光罩次数，增加了工艺的复杂性以及生产成本。
【发明内容】
有鉴于此，本发明提供一种TFT阵列基板及其制作方法，能够减少光罩次数，提高生产效率和降低生产成本。
为解决上述问题，本发明提供一种TFT阵列基板的制作方法，包括：
提供一基板；
在基板上依次形成第一透明金属氧化物导体层和第一金属层，并采用第一光罩工艺将第一金属层和第一透明金属氧化物导体层蚀刻成底栅电极及公共电极，其中底栅电极为第一金属层和第一透明金属氧化物导体层的叠层结构，公共电极为第一透明金属氧化物导体层的单层结构，其中，第一光罩采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种；
在基板上进一步形成栅绝缘层；
在基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将半导体层和第二金属层蚀刻成半导体图案以及位于半导体图案两端的源电极和漏电极，其中半导体图案位于底栅电极上方；
在基板上进一步形成第一钝化层，并采用第三光罩工艺对第一钝化层进行蚀刻以形成过孔；
在基板上进一步形成第二透明金属氧化物导体层，并采用第四光罩工艺将第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，顶栅电极位于半导体图案的上方，像素电极与公共电极至少部分重叠设置且通过过孔与源电极及漏电极中的一者电连接。
其中，在基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将半导体层和第二金属层蚀刻成半导体图案以及位于半导体图案两端的源电极和漏电极的步骤包括：
在基板上进一步形成本征半导体层、掺杂半导体层以及第二金属层，并通过采用第二光罩工艺将本征半导体层蚀刻成本征半导体图案，将掺杂半导体层蚀刻成位于本征半导体图案两端的第一掺杂半导体图案和第二掺杂半导体图案，并将第二金属层蚀刻成分别位于第一掺杂半导体图案和第二掺杂半导体图案上方的漏电极和源电极。
其中，第二光罩采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种。
本发明还提供一种TFT阵列基板的制作方法，包括：提供一基板，在基板上依次形成第一透明金属氧化物导体层和第一金属层，并采用第一光罩工艺将第一金属层和第一透明金属氧化物导体层蚀刻成底栅电极及公共电极，其中底栅电极为第一金属层和第一透明金属氧化物导体层的叠层结构，公共电极为第一透明金属氧化物导体层的单层结构。
其中，第一光罩采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种。
其中，制作方法还包括：在基板上进一步形成栅绝缘层；在基板上进一步形成半导体层，并采用第二光罩工艺将半导体层蚀刻成半导体图案，其中半导体图案位于底栅电极上方；在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成位于半导体图案两端的源电极及漏电极；在基板上进一步形成第一钝化层，并采用第四光罩工艺对第一钝化层进行蚀刻以形成过孔；在基板上进一步形成第二透明金属氧化物导体层，并采用第五光罩工艺将第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，顶栅电极位于半导体图案的上方，像素电极与公共电极至少部分重叠设置且通过过孔与源电极及漏电极中的一者电连接。
其中，在基板上进一步形成半导体层，并采用第二光罩工艺将半导体层蚀刻成半导体图案的步骤与在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成位于半导体图案两端的源电极及漏电极的步骤之间，制作方法还包括：在基板上进一步形成刻蚀阻挡层，并采用第六光罩工艺对刻蚀阻挡层进行蚀刻以形成位于半导体图案两端的刻蚀阻挡层过孔。
其中，制作方法还包括：在基板上进一步形成栅绝缘层；在基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将半导体层和第二金属层蚀刻成半导体图案以及位于半导体图案两端的源电极和漏电极，其中半导体图案位于底栅电极上方；在基板上进一步形成第一钝化层，并采用第三光罩工艺对第一钝化层进行蚀刻以形成过孔；在基板上进一步形成第二透明金属氧化物导体层，并采用第四光罩工艺将第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，顶栅电极位于半导体图案的上方，像素电极与公共电极至少部分重叠设置且通过过孔与源电极及漏电极中的一者电连接。
其中，在基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将半导体层和第二金属层蚀刻成半导体图案以及位于半导体图案两端的源电极和漏电极的步骤包括：在基板上进一步形成本征半导体层、掺杂半导体层以及第二金属层，并通过采用第二光罩工艺将本征半导体层蚀刻成本征半导体图案，将掺杂半导体层蚀刻成位于本征半导体图案两端的第一掺杂半导体图案和第二掺杂半导体图案，并将第二金属层蚀刻成分别位于第一掺杂半导体图案和第二掺杂半导体图案上方的漏电极和源电极。
其中，第二光罩采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种。
为解决上述问题，本发明还提供一种阵列基板，包括：基板；形成在基板上的底栅电极和公共电极，其中底栅电极和公共电极由同道光罩工艺形成，且底栅电极为第一金属层和第一透明金属氧化物导体层的叠层结构，公共电极为第一透明金属氧化物导体层的单层结构。
其中，基板进一步包括位于底栅电极上方的半导体图案以及位于半导体图案两端的源电极和漏电极，其中半导体图案与源电极和漏电极由另一同道光罩工艺形成。
其中，半导体图案包括：本征半导体图案以及位于本征半导体图案两端的第一掺杂半导体图案和第二掺杂半导体图案，漏电极和源电极分别位于第一掺杂半导体图案和第二掺杂半导体图案上方。
通过上述方案，本发明的有益效果是：区别于现有技术，本发明的TFT阵列基板的底栅电极为金属层与金属氧化物导体层的叠层结构，公共电极为金属氧化物导体层的单层结构，并且底栅电极及公共电极是通过同一道光罩工艺在基板上形成，因此，本发明的TFT阵列基板的制造可减少光罩的次数，提高生产效率和降低生产成本。
【附图说明】
图1是本发明TFT阵列基板的制作方法的第一实施方式的流程示意图；
图2A至图2F是图1中TFT阵列基板的第一实施方式中制作底栅电极和公共电极的工艺流程图；
图3是图1中TFT阵列基板的第一实施方式中第一光罩的透光原理示意图；
图4是图1中TFT阵列基板的第二光罩工艺形成半导体图案的工艺示意图；
图5是图1中TFT阵列基板的第三光罩工艺形成源电极及漏电极的工艺示意图；
图6是图1中TFT阵列基板的第四光罩工艺形成过孔的工艺示意图；
图7是由图1中TFT阵列基板的制作方法的第一实施方式制得的TFT阵列基板的结构示意图；
图8是本发明TFT阵列基板的制作方法的第二实施方式的流程示意图；
图9是由图8中TFT阵列基板的制作方法的第二实施方式制得的TFT阵列基板的结构示意图；
图10是本发明TFT阵列基板的制作方法的第三实施方式的流程示意图；
图11A至图11D是图10中TFT阵列基板的制作方法的第三实施方式中制作半导体图案、源电极和漏电极的工艺示意图；
图12是由图10中TFT阵列基板的制作方法的第三实施方式制得的TFT阵列基板的结构示意图。
【具体实施方式】
为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚、明白，以下结合附图和实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参看图1，图1是本发明TFT阵列基板的制作方法的第一实施方式的流程示意图，如图1所示，本实施方式的TFT阵列基板的制作方法包括：
S11：提供一基板。
S12：在基板上依次形成第一透明金属氧化物导体层和第一金属层，并采用第一光罩工艺将第一金属层和第一透明金属氧化物导体层蚀刻成底栅电极及公共电极。
其中，基板作为衬底基板，其可以为玻璃基板、塑料基板或其他合适材质的基板。在本实施方式中，基板优选为具有透光的特性的玻璃基板。
请一并参看图2A至图2F，图2A至图2F是图1中TFT阵列基板的第一实施方式中制作底栅电极和公共电极的工艺流程图。如图2A所示，采用物理气相沉积法（简称PVD）在基板100上先后形成第一透明金属氧化物导体层110及第一金属层120，第一金属层120覆盖在第一透明金属氧化物导体层110上方。其中，第一金属氧化物导体层110的材料包括但不限于为ITO（英文为：Indium tin oxide，中文为：氧化铟锡），ITO是一种具有良好的导电性和透明性的金属氧化物。第一金属层120的材料包括但不限于为铬、铝、钛或其他金属材料。
如图2B所示，采用第一光罩10对具有第一金属层120和第一透明金属氧化物导体层110的基板100进行曝光。其中，预先在第一金属层120上方覆盖一层光阻层（图未示），第一光罩10为半色调掩膜（Halt-tone Mask；简称HTM）、灰色调掩膜(Gray-tone Mask；简称GTM)或单狭缝掩膜（Single slit Mask；简称SSM）中的任一种。第一光罩10包括透光部101、半透光部102及不透光部103。采用第一光罩10对具有第一金属层120和第一透明金属氧化物导体层110的基板100进行曝光后，光阻层对应第一光罩10的透光部101的区域完全曝光，对应第一光罩10的半透光部102的区域半曝光，对应第一光罩10的不透光部103的区域不曝光。因此，在采用第一光罩10对光阻层进行曝光、半曝光、不曝光及显影的制程后相应获得第一光阻部1030和第二光阻部1020，其中第一光阻部1030的厚度大于第二光阻部1020的厚度，第一光阻部1030对应于第一光罩10的不透光部103，第二光阻部1020对应于第一光罩10的半透光部102。
如图2C所示，进一步对第一金属层120和第一金属氧化物导体层110没有被第一光阻部1030和第二光阻部1020覆盖的的区域进行第一次湿刻，将没有被第一光阻部1030和第二光阻部1020覆盖区域的第一金属层120和第一金属氧化物导体层110去掉。
如图2D所示，使用氧气对第一光阻部1030和第二光阻部1020进行灰化，以使得厚度较薄的第二光阻部1020被去掉，被第二光阻部1020覆盖的第一金属层120裸露出来。第一光阻部1030保留部分光阻。
如图2E所示，进一步对裸露出来的第一金属层120进行湿刻，从而在仅保留下第一透明金属氧化物导体层110作为公共电极11，公共电极11为第一透明金属氧化物导体层110形成的单层结构。
如图2F所示，将第一光阻部1030余下的光阻剥离去除，从而使得由余下的第一金属层120和第一透明金属氧化物导体层110的叠层结构形成底栅电极12。因此，仅通过同一道光罩工艺可以同时形成底栅电极12和公共电极11。
请参看图3，图3是图1中TFT阵列基板的第一实施方式中第一光罩的透光原理示意图。为了方便说明，图3中将第一光罩10、光强曲线70及基板100上形成底栅电极12和公共电极11的结构放在一起进行说明。如图3所示，第一光罩10包括透光部101、半透光部102及不透光部103，其中，不透光部103对应底栅电极12的区域，半透光部102对应于公共电极11的区域，透光部101对应于除了底栅电极12和公共电极11的其他区域。光强曲线70的第一向上凸起部703对应于第一光罩10的不透光部103，表示此时光照强度最弱。光强曲线70的第二向上凸起部702对应于第一光罩10的半透光部102，其中，第一向上凸起部703对应的光照强度小于第二向上凸起部702对应的光照强度，并且，第一向上凸起部703对应的光照强度和第二向上凸起部702对应的光照强度均小于其他区域的光照强度。因此，在使用第一光罩10进行曝光显影后，使得对应于底栅电极12上的第一光阻部1030的厚度大于对应于公共电极11上的第二光阻部1020的厚度，从而通过进一步的湿刻法、光阻氧气灰化法等获得底栅电极12和公共电极11，因此，通过同一道光罩工艺可以同时形成底栅电极12和公共电极11。
在本实施方式中，利用第一光罩10对第一透明金属氧化物导体层110和第一金属层120进行曝光、半曝光及未曝光，以形成底栅电极12和公共电极11，是由第一光罩10的结构决定的。
S13：在基板上进一步形成栅绝缘层。
S14：在基板上进一步形成半导体层，并采用第二光罩工艺将半导体层蚀刻成半导体图案。
如图4所示，在基板100上形成一层栅绝缘层130，栅绝缘层130覆盖底栅电极12和公共电极11并延伸到基板100上，该栅绝缘层130可以采用化学气相沉积法形成，栅绝缘层130的材质包括但不限于为氮化硅、氧化硅或氮氧化硅。
并在栅绝缘层130上方进一步形成半导体层（图未示），半导体层可以通过沉积法形成。半导体层的材料优选为IGZO（Indium Gallium Zinc Oxide），IGZO是一种含有铟、镓和锌的非晶金属氧化物，是用于新一代薄膜晶体管技术中的沟道层材料，IGZO的载流子迁移率是非晶硅的20~30倍，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在TFT-LCD中成为可能，另外，由于晶体管数量减少和提高了每个像素的透光率，IGZO显示器具有更高的能效水平，而且效率更高，并且IGZO可以利用现有的非晶硅生产线生产，只需稍加改动，因此在成本方面IGZO比低温多晶硅更具有竞争力。
进一步在半导体层上面再覆盖一层光阻层（图未示），采用第二光罩（图未示）对光阻层进行曝光，第二光罩包括透光部和不透光部，从而使得经过第二光罩工艺进行曝光显影蚀刻等制程后，对应于第二光罩的透光部的半导体层被蚀刻去掉，留下对应于第二光罩的不透部的半导体层形成一半导体图案14，即半导体图案14由对应于第二光罩的不透光部的半导体层形成，因为未被曝光蚀刻而保留。半导体图案14位于底栅电极12上方。这里由半导体层制作半导体图案14的方法采用的是现有技术的方法，在此不作过多的赘述。
S15：在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成位于半导体图案两端的源电极及漏电极。
如图5所示，在基板100上进一步形成第二金属层（图未示），采用第三光罩（图未示）对第二金属层进行曝光，并进行显影蚀刻的制程后，形成位于半导体图案14两端的源电极16及漏电极15，其中，采用第三光罩制作源电极16及漏电极15的工艺采用的是现有技术的工艺，在此不再过多的赘述。
S16：在基板上进一步形成第一钝化层，并采用第四光罩工艺对第一钝化层进行蚀刻以形成过孔。
如图6所示，进一步在基板100上形成第一钝化层160，第一钝化层160覆盖源电极16及漏电极15、半导体图案14并延伸到栅绝缘层130上。采用第四光罩（图未示）对第一钝化层160进行曝光、显影及蚀刻等制程后，以使对应于源电极16或漏电极15上方的第一钝化层160的区域形成过孔17。其中，形成过孔17的方法采用的是现有技术的方法，在此不再过多的赘述。
S17：在基板上进一步形成第二透明金属氧化物导体层，并采用第五光罩工艺将第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极。
S18：在基板上进一步形成第二钝化层。
请参看图7，图7是由图1中TFT阵列基板的制作方法的第一实施方式制得的TFT阵列基板的结构示意图，结合图7说明步骤S17至S18的实施方式。在基板100的第一钝化层160上进一步形成第二透明金属氧化物导体层（图未示），该第二透明金属氧化物导体层的材料采用的是与公共电极11同样的材料，即第二透明金属氧化物导体层的材料也为ITO氧化物。采用第五光罩（图未示）对第二透明金属氧化物导体层进行曝光，并进行显影蚀刻后，形成顶栅电极19和多个像素电极18。其中，顶栅电极19位于半导体图案14的上方，并与底栅电极12对应设置。像素电极18与公共电极11至少部分重叠设置，且其中一个像素电极18通过过孔17与源电极16及漏电极15中的一者电连接。图7中所示的是一个像素电极18通过过孔17与源电极16连接，其余的像素电极18间隔排列在公共电极11的上方。并在基板100上进一步形成第二钝化层180，第二钝化层180覆盖像素电极18、顶栅电极19并延伸到第一钝化层160上。
其中，由第二透明金属氧化物导体层制作像素电极18和顶栅电极19并进一步覆盖第二钝化层180采用的是现有的技术方法，在此不再过多的赘述。
因此，由上述实施方式制得的TFT阵列基板1包括：基板100、形成在基板100上的底栅电极12和公共电极11、栅绝缘层130、半导体图案14、漏电极15及源电极16、第一钝化层160、像素电极18、顶栅电极19及第二钝化层180。其中，底栅电极12和公共电极11由同道光罩工艺形成，并且底栅电极12为第一金属层120和第一透明金属氧化物导体层110的叠层结构，公共电极11为第一透明金属氧化物导体层110的单层结构。栅绝缘层130覆盖底栅电极12和公共电极11并延伸到基板100上，半导体图案14位于底栅电极12上方，漏电极15及源电极16分别位于半导体图案14的两端。第一钝化层160覆盖漏电极15及源电极16、半导体图案14并延伸到栅绝缘层130上，并且，第一钝化层160对应于源电极16或漏电极15的区域还形成有过孔17，图7中所示的过孔17位于源电极16上方，该过孔17用于将源电极16与像素电极18电连接，并且像素电极18与公共电极11至少部分重叠，顶栅电极19与底栅电极12相对设置。第二钝化层180覆盖顶栅电极19和像素电极18并延伸到第一钝化层160上。该TFT阵列基板1为BCE（英文为：Back Channel Etch，中文为：背沟道刻蚀结构）结构的阵列基板。
综上，本实施方式的TFT阵列基板可以在基板上依次形成金属层和透明金属氧化物导体层，然后通过同一道光罩工艺在基板上一次形成底栅电极和公共电极，使金属层和透明金属氧化物导体层的叠层结构形成底栅电极，透明金属氧化物导体层的单层结构形成公共电极，由此可以减少制作TFT阵列基板的光罩次数，提高生产效率和降低生产成本。
请参看图8，图8是本发明TFT阵列基板的制作方法的第二实施方式的流程示意图。如图8所示，本实施方式的TFT阵列基板的制作方法包括：
S21：提供一基板。
S22：在基板上依次形成第一透明金属氧化物导体层和第一金属层，并采用第一光罩工艺将第一金属层和第一透明金属氧化物导体层蚀刻成底栅电极及公共电极。
S23：在基板上进一步形成栅绝缘层。
S24：在基板上进一步形成半导体层，并采用第二光罩工艺将半导体层蚀刻成半导体图案。
S25：在基板上进一步形成刻蚀阻挡层，并采用第六光罩工艺对刻蚀阻挡层进行蚀刻以形成位于半导体图案两端的刻蚀阻挡层过孔。
S26：在基板上进一步形成第二金属层，并采用第三光罩工艺将第二金属层蚀刻成位于半导体图案两端的源电极及漏电极。
S27：在基板上进一步形成第一钝化层，并采用第四光罩工艺对第一钝化层进行蚀刻以形成过孔。
S28：在基板上进一步形成第二透明金属氧化物导体层，并采用第五光罩工艺将第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极。
S29：在基板上进一步形成第二钝化层。
其中，请结合图1至图6及图9一并参考，本实施方式与上述实施方式的区别在于，如图4所示的在采用第二光罩将半导体层蚀刻出半导体图案14后，本实施方式还在基板100上进一步形成刻蚀阻挡层210，如图9所示，图9是由图8的TFT阵列基板的制作方法的第二实施方式制得的TFL阵列基板的结构示意图。其中，刻蚀阻挡层210覆盖半导体图案14并延伸到栅绝缘层130上。采用第六光罩（图未示）对刻蚀阻挡层210进行曝光显影并进行蚀刻工艺，将刻蚀阻挡层210位于半导体图案14两端的区域进行曝光蚀刻形成刻蚀阻挡层过孔20，刻蚀阻挡层过孔20用于使源电极16和漏电极15与半导体图案14电连接。其中，刻蚀阻挡层210的作用是使得在形成源电极16和漏电极15的工艺制程中保护半导体图案14不被腐蚀。步骤S26至步骤S29至上述实施方式的步骤S15至步骤S18类似，在此不再赘述。
本实施方式的TFL阵列基板2为ESL（英文为：Etch stopper layer；中文为：刻蚀阻挡层）结构的阵列基板，本实施方式的图9所示的阵列基板2的结构图与图7所示的BCE结构的阵列基板1的区别在于，TFL阵列基板2还包括位于半导体14上方的刻蚀阻挡层210，刻蚀阻挡层210对应于半导体图案14两端的区域形成有刻蚀阻挡层过孔20，使得位于半导体图案14两端的源电极16和漏电极15通过刻蚀阻挡层过孔20与半导体图案14电连接。
综上，本实施方式的阵列基板制程工艺与上述实施方式的工艺类似，其可以减少光罩的次数，提高生产效率和降低生产成本，并且通过设置刻蚀阻挡层还可以避免在蚀刻形成漏电极和源电极时误腐蚀半导体图案。
请参看图10，图10是本发明TFT阵列基板的制作方法的第三实施方式的流程示意图。如图10所示，本实施方式的TFT阵列基板的制作方法包括：
S31：提供一基板。
S32：在基板上依次形成第一透明金属氧化物导体层和第一金属层，并采用第一光罩工艺将第一金属层和第一透明金属氧化物导体层蚀刻成底栅电极及公共电极。
S33：在基板上进一步形成栅绝缘层。
其中，步骤S31至步骤S33与第一实施方式的步骤S11至S13类似，在此不再赘述。
S34：在基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将半导体层和第二金属层蚀刻成半导体图案以及位于半导体图案两端的源电极和漏电极。
请一并参考图1至图5、图11A至图11D，其中图11A至图11D是图10中TFT阵列基板的制作方法的第三实施方式中制作半导体图案、源电极和漏电极的工艺示意图。与第一实施方式类似，半导体层140用于蚀刻形成半导体图案14，第二金属层150用于蚀刻形成位于半导体图案14两端的源电极16和漏电极15，并且半导体图案14位于底栅电极12上方。
本实施方式与第一实施方式的区别之处在于，如图11A所示，半导体层140包括本征半导体层190以及掺杂半导体层200。采用化学气相沉积法（简称CVD）在基板10上先后沉积本征半导体层190以及掺杂半导体层200。其中本征半导体层190为a-Si（非晶硅）层，掺杂半导体层200为n+a-Si层，n+a-Si层为高浓度掺杂的N型非晶硅导电层。
如图11B所示，进一步采用PVD法在基板100上沉积第二金属层150。第二金属层150与第一实施方式的材料相同，可以为铝、铬、钼、钛等金属材料。
进一步在第二金属层150上形成光阻层（图未示），采用第二光罩对光阻层进行曝光并显影，第二光罩与第一光罩的结构类似，同样是采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种。采用第二光罩对光阻层进行曝光显影后，得到一光阻图案21，如图11C所示。进一步将第二金属层150没有被光阻图案21覆盖的区域进行湿刻去除，然后采用干刻法去掉没有被光阻图案21覆盖的本征半导体层190以及掺杂半导体层200对应的区域。进一步使用氧气对光阻图案21进行灰化处理，将光阻图案21中沟道处较薄位置的光阻去掉，光阻图案21较厚位置保留一定厚度的光阻，这里指后期制作形成的源电极16和漏电极15上方对应的位置保留一定厚度的光阻。进一步使用湿刻法将没有被光阻覆盖的第二金属层150去掉，并使用干刻法将没有被光阻覆盖的掺杂半导体层200去掉以及去掉少部分本征半导体层190，并去除余下的光阻，从而得到图11D所示的结构，其中，本征半导体层190被蚀刻成本征半导体图案22，掺杂半导体层200被蚀刻成分别位于本征半导体图案22两端的第一掺杂半导体图案23和第二掺杂半导体图案24，第二金属层150被蚀刻成分别位于第一掺杂半导体图案23上方的漏电极15和位于第二掺杂半导体图案24上方的源电极16。因此，本实施方式仅通过同一道光罩工艺可以同时形成半导体图案14和源电极16及漏电极15。半导体图案14由本征半导体图案22和分别位于本征半导体图案22两端的第一掺杂半导体图案23和第二掺杂半导体图案24组成。
S35：在基板上进一步形成第一钝化层，并采用第三光罩工艺对第一钝化层进行蚀刻以形成过孔。
S36：在基板上进一步形成第二透明金属氧化物导体层，并采用第四光罩工艺将第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极。
S37：在基板上进一步形成第二钝化层。
请一起参看图6、图7及图12，图12是由图10中TFT阵列基板的制作方法的第三实施方式制得的TFT阵列基板的结构示意图。其中，步骤S35至步骤S37与上述实施方式的步骤S16至步骤S18类似，在这不再赘述。
本实施方式的TFT阵列基板3的结构与第一实施方式的TFT阵列基板1的结构的区别在于，本实施方式为由本征半导体图案22，并且本征半导体图案22两端还设置有第一掺杂半导体图案23和第二掺杂半导体图案24以替代第一实施方式图7中所示的半导体图案14，并且图12所示的实施方式中的漏电极15位于第一掺杂半导体图案23上方，源电极16位于第二掺杂半导体图案24上方。因此，本实施方式的TFT阵列基板可以通过同一道光罩工艺在基板上形成底栅电极和公共电极，并通过同一道光罩工艺形成半导体图案及位于半导体图案两端的源电极和漏电极，其中，半导体图案由半征半导体图案和位于半征半导体图案两端的第一掺杂半导体图案和第二掺杂半导体图案组成，漏电极和源电极分别位于第一掺杂半导体图案和第二掺杂半导体图案上方，使得本实施方式的TFT阵列基板仅需要四道光罩工艺，减少光罩次数，提高生产效率，降低生产成本。
综上所述，区域别于现有技术，本发明的TFT阵列基板可以通过一道光罩工艺在基板上形成由金属层和透明金属氧化物导体层叠层形成的底栅电极和由透明金属氧化物导体层形成的公共电极，从而使得阵列基板的制程可以减少光罩次数，提高生产效率，降低生产成本。
以上参照附图说明了本发明的优选实施例，并非因此局限本发明的权利范围。本领域技术人员不脱离本发明的范围和实质内所作的任何修改、等同替换和改进，均应在本发明的权利范围之内。

Claims (13)

  1. 一种TFT阵列基板的制作方法，其中，所述制作方法包括：
    提供一基板；
    在所述基板上依次形成第一透明金属氧化物导体层和第一金属层，并采用第一光罩工艺将所述第一金属层和所述第一透明金属氧化物导体层蚀刻成底栅电极及公共电极，其中所述底栅电极为所述第一金属层和第一透明金属氧化物导体层的叠层结构，所述公共电极为所述第一透明金属氧化物导体层的单层结构，其中，所述第一光罩采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种；
    在所述基板上进一步形成栅绝缘层；
    在所述基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将所述半导体层和第二金属层蚀刻成半导体图案以及位于所述半导体图案两端的源电极和漏电极，其中所述半导体图案位于所述底栅电极上方；
    在所述基板上进一步形成第一钝化层，并采用第三光罩工艺对所述第一钝化层进行蚀刻以形成过孔；
    在所述基板上进一步形成第二透明金属氧化物导体层，并采用第四光罩工艺将所述第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，所述顶栅电极位于所述半导体图案的上方，所述像素电极与所述公共电极至少部分重叠设置且通过所述过孔与所述源电极及漏电极中的一者电连接。
  2. 根据权利要求1所述的制作方法，其中，在所述基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将所述半导体层和第二金属层蚀刻成半导体图案以及位于所述半导体图案两端的源电极和漏电极的步骤包括：
    在所述基板上进一步形成本征半导体层、掺杂半导体层以及第二金属层，并通过采用所述第二光罩工艺将所述本征半导体层蚀刻成本征半导体图案，将所述掺杂半导体层蚀刻成位于所述本征半导体图案两端的第一掺杂半导体图案和第二掺杂半导体图案，并将所述第二金属层蚀刻成分别位于所述第一掺杂半导体图案和第二掺杂半导体图案上方的所述漏电极和源电极。
  3. 根据权利要求2所述的制作方法，其中，所述第二光罩采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种。
  4. 一种TFT阵列基板的制作方法，其中，所述制作方法包括：
    提供一基板；
    在所述基板上依次形成第一透明金属氧化物导体层和第一金属层，并采用第一光罩工艺将所述第一金属层和所述第一透明金属氧化物导体层蚀刻成底栅电极及公共电极，其中所述底栅电极为所述第一金属层和第一透明金属氧化物导体层的叠层结构，所述公共电极为所述第一透明金属氧化物导体层的单层结构。
  5. 根据权利要求4所述的制作方法，其中，所述第一光罩采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种。
  6. 根据权利要求4所述的制作方法，其中，所述制作方法还包括：
    在所述基板上进一步形成栅绝缘层；
    在所述基板上进一步形成半导体层，并采用第二光罩工艺将所述半导体层蚀刻成半导体图案，其中所述半导体图案位于所述底栅电极上方；
    在所述基板上进一步形成第二金属层，并采用第三光罩工艺将所述第二金属层蚀刻成位于所述半导体图案两端的源电极及漏电极；
    在所述基板上进一步形成第一钝化层，并采用第四光罩工艺对所述第一钝化层进行蚀刻以形成过孔；
    在所述基板上进一步形成第二透明金属氧化物导体层，并采用第五光罩工艺将所述第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，所述顶栅电极位于所述半导体图案的上方，所述像素电极与所述公共电极至少部分重叠设置且通过所述过孔与所述源电极及漏电极中的一者电连接。
  7. 根据权利要求6所述的制作方法，其中，在所述基板上进一步形成半导体层，并采用第二光罩工艺将所述半导体层蚀刻成半导体图案的步骤与在所述基板上进一步形成第二金属层，并采用第三光罩工艺将所述第二金属层蚀刻成位于所述半导体图案两端的源电极及漏电极的步骤之间，所述制作方法还包括：
    在所述基板上进一步形成刻蚀阻挡层，并采用第六光罩工艺对所述刻蚀阻挡层进行蚀刻以形成位于所述半导体图案两端的刻蚀阻挡层过孔。
  8. 根据权利要求4所述的制作方法，其中，所述制作方法还包括：
    在所述基板上进一步形成栅绝缘层；
    在所述基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将所述半导体层和第二金属层蚀刻成半导体图案以及位于所述半导体图案两端的源电极和漏电极，其中所述半导体图案位于所述底栅电极上方；
    在所述基板上进一步形成第一钝化层，并采用第三光罩工艺对所述第一钝化层进行蚀刻以形成过孔；
    在所述基板上进一步形成第二透明金属氧化物导体层，并采用第四光罩工艺将所述第二透明金属氧化物导体层蚀刻成顶栅电极和像素电极，其中，所述顶栅电极位于所述半导体图案的上方，所述像素电极与所述公共电极至少部分重叠设置且通过所述过孔与所述源电极及漏电极中的一者电连接。
  9. 根据权利要求8所述的制作方法，其中，在所述基板上进一步形成半导体层以及第二金属层，并采用第二光罩工艺将所述半导体层和第二金属层蚀刻成半导体图案以及位于所述半导体图案两端的源电极和漏电极的步骤包括：
    在所述基板上进一步形成本征半导体层、掺杂半导体层以及第二金属层，并通过采用所述第二光罩工艺将所述本征半导体层蚀刻成本征半导体图案，将所述掺杂半导体层蚀刻成位于所述本征半导体图案两端的第一掺杂半导体图案和第二掺杂半导体图案，并将所述第二金属层蚀刻成分别位于所述第一掺杂半导体图案和第二掺杂半导体图案上方的所述漏电极和源电极。
  10. 根据权利要求9所述的制作方法，其中，所述第二光罩采用半色调掩膜、灰色调掩膜或单狭缝掩膜中的任一种。
  11. 一种TFT阵列基板，其中，所述阵列基板包括：
    基板；
    形成在所述基板上的底栅电极和公共电极，其中所述底栅电极和公共电极由同道光罩工艺形成，且所述底栅电极为第一金属层和第一透明金属氧化物导体层的叠层结构，所述公共电极为所述第一透明金属氧化物导体层的单层结构。
  12. 根据权利要求11所述的阵列基板，其中，所述基板进一步包括位于所述底栅电极上方的半导体图案以及位于所述半导体图案两端的源电极和漏电极，其中所述半导体图案与所述源电极和漏电极由另一同道光罩工艺形成。
  13. 根据权利要求12所述的阵列基板，其中，所述半导体图案包括：本征半导体图案以及位于所述本征半导体图案两端的第一掺杂半导体图案和第二掺杂半导体图案，所述漏电极和源电极分别位于所述第一掺杂半导体图案和第二掺杂半导体图案上方。
PCT/CN2015/091440 2015-09-28 2015-10-08 一种tft阵列基板及其制作方法 WO2017054250A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/786,459 US20170162708A1 (en) 2015-09-28 2015-10-08 Tft substrates and the manufacturing methods thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510629393.7A CN105304643A (zh) 2015-09-28 2015-09-28 一种tft阵列基板及其制作方法
CN201510629393.7 2015-09-28

Publications (1)

Publication Number Publication Date
WO2017054250A1 true WO2017054250A1 (zh) 2017-04-06

Family

ID=55201681

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/091440 WO2017054250A1 (zh) 2015-09-28 2015-10-08 一种tft阵列基板及其制作方法

Country Status (3)

Country Link
US (1) US20170162708A1 (zh)
CN (1) CN105304643A (zh)
WO (1) WO2017054250A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170162708A1 (en) * 2015-09-28 2017-06-08 Shenzhen China Star Optoelectronics Technology Co. Ltd. Tft substrates and the manufacturing methods thereof

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104779203B (zh) * 2015-04-23 2017-11-28 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN105720012A (zh) * 2016-02-18 2016-06-29 深圳市华星光电技术有限公司 双栅极tft阵列基板及制作方法
CN106684037B (zh) 2017-03-22 2019-09-24 深圳市华星光电半导体显示技术有限公司 优化4m制程的tft阵列制备方法
US10290665B2 (en) 2017-04-10 2019-05-14 Shenzhen China Star Optoelectronics Technology Co., Ltd Array substrates, display devices, and the manufacturing methods thereof
CN106910748A (zh) * 2017-04-10 2017-06-30 深圳市华星光电技术有限公司 一种阵列基板、显示装置及其制作方法
CN108010924A (zh) * 2017-12-06 2018-05-08 京东方科技集团股份有限公司 一种阵列基板及制作方法、显示面板
CN113192980B (zh) * 2018-03-21 2023-06-16 福建华佳彩有限公司 一种阵列基板结构、显示装置及阵列基板结构的制备方法
CN109509757B (zh) * 2018-11-29 2024-04-12 福建华佳彩有限公司 液晶显示器Demux结构、制作方法及液晶显示器
CN111740717B (zh) * 2020-02-10 2024-01-05 绍兴中芯集成电路制造股份有限公司 半导体器件及其形成方法
CN112083607B (zh) * 2020-09-23 2022-04-22 惠科股份有限公司 阵列基板及其制造方法、显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060146255A1 (en) * 2004-12-31 2006-07-06 Ahn Byung C Liquid crystal display device and fabricating method thereof
CN101527282A (zh) * 2007-12-03 2009-09-09 株式会社半导体能源研究所 半导体装置的制造方法
CN102543864A (zh) * 2012-02-07 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102540604A (zh) * 2010-12-28 2012-07-04 乐金显示有限公司 用于ffs模式液晶显示器件的阵列基板及其制造方法
CN102769040A (zh) * 2012-07-25 2012-11-07 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制作方法、显示装置
US20140339542A1 (en) * 2013-05-16 2014-11-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN104867870A (zh) * 2015-04-14 2015-08-26 深圳市华星光电技术有限公司 双栅极氧化物半导体tft基板的制作方法及其结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6439830B2 (en) * 1999-12-08 2002-08-27 Total Mailroom Support, Inc. Opening guard mechanism for printed product stacking device
WO2003044595A1 (en) * 2001-11-22 2003-05-30 Samsung Electronics Co., Ltd. Liquid crystal display and thin film transistor array panel
US7157394B2 (en) * 2004-07-17 2007-01-02 Adams Sr James Hugo Stoichiometrically balanced silicon nitride ceramic for high performance cutting tools
KR101085136B1 (ko) * 2004-12-04 2011-11-18 엘지디스플레이 주식회사 수평 전계 박막 트랜지스터 기판 및 그 제조 방법
JP4117001B2 (ja) * 2005-02-17 2008-07-09 株式会社神戸製鋼所 薄膜トランジスタ基板、表示デバイス、および表示デバイス用のスパッタリングターゲット
KR101293573B1 (ko) * 2006-10-02 2013-08-06 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
EP2502891A1 (en) * 2011-03-23 2012-09-26 Sika Technology AG Activator composition for latent hydraulic and/or pozzolanic binder materials
EP2827418B1 (en) * 2012-03-14 2015-09-23 Nissan Motor Co., Ltd. Electrode assembly for solid polymer fuel cell
CN105304643A (zh) * 2015-09-28 2016-02-03 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060146255A1 (en) * 2004-12-31 2006-07-06 Ahn Byung C Liquid crystal display device and fabricating method thereof
CN101527282A (zh) * 2007-12-03 2009-09-09 株式会社半导体能源研究所 半导体装置的制造方法
CN102540604A (zh) * 2010-12-28 2012-07-04 乐金显示有限公司 用于ffs模式液晶显示器件的阵列基板及其制造方法
CN102543864A (zh) * 2012-02-07 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102769040A (zh) * 2012-07-25 2012-11-07 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制作方法、显示装置
US20140339542A1 (en) * 2013-05-16 2014-11-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN104867870A (zh) * 2015-04-14 2015-08-26 深圳市华星光电技术有限公司 双栅极氧化物半导体tft基板的制作方法及其结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170162708A1 (en) * 2015-09-28 2017-06-08 Shenzhen China Star Optoelectronics Technology Co. Ltd. Tft substrates and the manufacturing methods thereof

Also Published As

Publication number Publication date
CN105304643A (zh) 2016-02-03
US20170162708A1 (en) 2017-06-08

Similar Documents

Publication Publication Date Title
WO2017054250A1 (zh) 一种tft阵列基板及其制作方法
WO2017054191A1 (zh) 一种tft阵列基板及其制作方法
US9368637B2 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
WO2016201729A1 (zh) 一种阵列基板及其制作方法、液晶显示器
WO2016119280A1 (zh) 氧化物薄膜晶体管及其制作方法
WO2014085971A1 (zh) 一种金属氧化物tft器件及制造方法
WO2014146291A1 (zh) 薄膜晶体管及其像素单元的制造方法
WO2016090689A1 (zh) 一种阵列基板的掺杂方法及制造设备
WO2017035851A1 (zh) Tft、阵列基板及tft的制备方法
WO2017024573A1 (zh) 一种阵列基板及其制作方法
WO2017067062A1 (zh) 一种双栅极薄膜晶体管及其制作方法、以及阵列基板
WO2021027059A1 (zh) 一种阵列基板及其制备方法、触控显示面板
WO2017054259A1 (zh) 液晶显示面板、阵列基板及其制造方法
WO2019095482A1 (zh) Tft基板及其制作方法
WO2017140015A1 (zh) 双栅极tft阵列基板及制作方法
WO2019232820A1 (zh) 阵列基板的制作方法以及液晶显示装置
WO2017054258A1 (zh) Tft阵列基板的制备方法、tft阵列基板及显示装置
WO2016078112A1 (zh) 薄膜晶体管基板的制作方法及制造设备
WO2021120378A1 (zh) 一种阵列基板及其制作方法
WO2015096374A1 (zh) 阵列基板及其制作方法、显示装置和薄膜晶体管
WO2017071054A1 (zh) 一种显示面板及其制造方法
WO2016026177A1 (zh) Tft基板的制作方法及其结构
WO2019029007A1 (zh) 一种tft基板的制备方法、tft基板以及oled显示面板
WO2018218712A1 (zh) 低温多晶硅tft基板及其制作方法
WO2016090690A1 (zh) 一种ltps像素单元及其制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14786459

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15905162

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15905162

Country of ref document: EP

Kind code of ref document: A1