WO2016090689A1 - 一种阵列基板的掺杂方法及制造设备 - Google Patents

一种阵列基板的掺杂方法及制造设备 Download PDF

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Publication number
WO2016090689A1
WO2016090689A1 PCT/CN2014/095383 CN2014095383W WO2016090689A1 WO 2016090689 A1 WO2016090689 A1 WO 2016090689A1 CN 2014095383 W CN2014095383 W CN 2014095383W WO 2016090689 A1 WO2016090689 A1 WO 2016090689A1
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Prior art keywords
pattern layer
photoresist
polysilicon pattern
polysilicon
doped region
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PCT/CN2014/095383
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English (en)
French (fr)
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薛景峰
张鑫
陈归
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深圳市华星光电技术有限公司
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Priority to US14/426,224 priority Critical patent/US9640569B2/en
Publication of WO2016090689A1 publication Critical patent/WO2016090689A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a doping method and a manufacturing apparatus for an array substrate.
  • TFT LCD liquid crystal display can be divided into polysilicon (Poly-Si TFT) and amorphous silicon (a-Si TFT) two, and due to low temperature polysilicon (Low Temperature Poly-silicon (LTPS) liquid crystal display has higher resolution, higher color saturation and lower cost than traditional TFT-LCD amorphous silicon display.
  • LTPS-TFT LCD liquid crystal displays have become the mainstream of new generation liquid crystal displays.
  • the LTPS process is more complicated, one of which is that the off current (I off) of the TFT is large, in order to reduce I. Off, usually using dual gate or lightly doped drain area (Lightly doped Drain (referred to as LDD) structure.
  • LDD lightly doped Drain
  • it is generally required to dope twice (N-type heavily doped and N-type lightly doped), for example, first adopting a photomask to perform an N-type re-doping after exposure. Miscellaneous, and then removing the photoresist, performing a second N-type light doping, the prior art two doping not only increases the manufacturing process, but also increases the cost.
  • the present invention provides a doping method and a manufacturing apparatus for an array substrate, which realize a heavily doped region and a lightly doped region in which polysilicon is formed by primary doping.
  • the present invention provides a method for doping an array substrate, comprising: forming a polysilicon pattern layer on a substrate, forming a gate insulating layer on the substrate having the polysilicon pattern layer, forming on the gate insulating layer a gate pattern layer, wherein a photoresist pattern layer is formed on the gate insulating layer of the substrate by using a halftone mask, wherein the gate insulating layer covers the polysilicon pattern layer, and the photoresist pattern layer is formed corresponding to the heavily doped region of the polysilicon pattern layer a first photoresist portion corresponding to the lightly doped region corresponding to the polysilicon pattern layer, and a second photoresist portion corresponding to the undoped region of the polysilicon pattern layer, the first photoresist portion being thinner than the second photoresist portion;
  • the halftone mask includes an all-transmission portion corresponding to the hollow portion, a semi-transmissive portion corresponding to the first photoresist portion, and an opaque portion
  • the doping the polysilicon pattern layer once comprises doping the low temperature polysilicon by a diffusion method or an ion implantation method to form a polysilicon pattern layer, and the polysilicon pattern layer includes a heavily doped region and a lightly doped region.
  • the halftone mask is a halftone mask or a gray scale mask
  • the semi-transmissive portion of the halftone mask corresponding to the first photoresist portion is a semi-transmissive film
  • the transmittance of the semi-transmissive film is 0 to 100.
  • the gray-scale reticle corresponding to the semi-transmissive portion of the first photoresist portion has at least one slit to block a part of the light source to achieve a semi-transparent effect, and the slit adjustment control transmittance is between 0 and 100%.
  • the present invention further provides a method for doping an array substrate, comprising: forming a photoresist pattern layer on a gate insulating layer of a substrate by using a halftone mask, wherein the substrate is provided with a polysilicon pattern layer, and the gate is provided with a polysilicon pattern layer
  • the pole insulating layer covers the polysilicon pattern layer, and the photoresist pattern layer forms a hollow portion corresponding to the to-be-doped region of the polysilicon pattern layer, and the first photoresist portion is formed corresponding to the to-be-lightly doped region of the polysilicon pattern layer, corresponding to the polysilicon pattern layer
  • the doped region forms a second photoresist portion, and the first photoresist portion is thinner than the second photoresist portion; the polysilicon pattern layer is doped once to form a heavily doped region and a lightly doped region of the polysilicon pattern layer at a time.
  • the step of forming a photoresist pattern layer on the gate insulating layer on the substrate by using the halftone mask includes: forming a polysilicon pattern layer on the substrate; forming a gate insulating layer on the substrate having the polysilicon pattern layer; A gate pattern layer is formed on the insulating layer; a photoresist pattern layer is formed on the gate insulating layer having the gate pattern layer by using a halftone mask.
  • the halftone mask includes a full light transmitting portion corresponding to the hollow portion, a semi-transmissive portion corresponding to the first photoresist portion, and an opaque portion corresponding to the second photoresist portion; and a halftone mask is used on the substrate
  • Forming the photoresist pattern layer on the gate insulating layer comprises: exposing the photoresist pattern layer by using a halftone mask, forming three exposure levels of the exposure portion, the half exposure portion and the unexposed portion on the photoresist pattern layer, The exposure levels are respectively etched to form a hollow portion corresponding to the exposed portion, a first photoresist portion corresponding to the half exposure portion, and a second photoresist portion corresponding to the unexposed portion.
  • the doping the polysilicon pattern layer once comprises: doping the low temperature polysilicon by a diffusion method or an ion implantation method to form a polysilicon pattern layer, the polysilicon pattern layer including a heavily doped region and a lightly doped region.
  • the halftone mask is a halftone mask or a gray scale mask
  • the halftone mask corresponds to the semi-transmissive portion of the first photoresist portion is a semi-transmissive film, and the transmittance of the semi-transmissive film is Between 0 and 100%
  • the gray-scale mask corresponding to the semi-transmissive portion of the first photoresist portion has at least one slit to block a part of the light source to achieve a semi-transparent effect, and the slit adjustment control transmittance is 0-100 %between.
  • an apparatus for manufacturing an array substrate includes: an exposure device, a halftone mask, and a doping device; the exposure device is configured to form light on a gate insulating layer of a substrate by using a halftone mask a resist pattern layer, wherein a polysilicon pattern layer is disposed on the substrate, the gate insulating layer covers the polysilicon pattern layer, and the photoresist pattern layer forms a hollow portion corresponding to the heavily doped region of the polysilicon pattern layer, and the light-doped layer corresponding to the polysilicon pattern layer is to be lightly doped Forming a first photoresist portion, forming a second photoresist portion corresponding to the undoped region of the polysilicon pattern layer, the first photoresist portion being thinner than the second photoresist portion; and the doping device for doping the polysilicon pattern layer once The heavily doped region and the lightly doped region of the polysilicon pattern layer are formed at one time.
  • the polysilicon pattern layer is formed on the substrate, the gate insulating layer is formed on the substrate having the polysilicon pattern layer, the gate pattern layer is formed on the gate insulating layer, and the photoresist pattern layer is gate insulated on the gate pattern layer
  • the layer is formed by exposure of a halftone mask using an exposure device.
  • the halftone mask comprises a full light transmissive portion corresponding to the hollow portion, a semi-transmissive portion corresponding to the first photoresist portion, and an opaque portion corresponding to the second photoresist portion, through the halftone mask by the exposure device Exposing the photoresist pattern layer to form three exposure levels of the exposed portion, the half exposed portion and the unexposed portion on the photoresist pattern layer, etching the three exposure levels, respectively forming a hollow portion corresponding to the exposed portion, corresponding to a first photoresist portion of the half exposure portion and a second photoresist portion corresponding to the unexposed portion.
  • the polysilicon pattern layer is formed by doping low temperature polysilicon by using a diffusion method or an ion implantation method, and the polysilicon pattern layer includes a heavily doped region and a lightly doped region.
  • the halftone mask is a halftone mask or a gray scale mask; wherein the semi-transmissive portion of the halftone mask corresponding to the first photoresist portion is a semi-transmissive film, and the transmittance of the semi-transmissive film is 0 ⁇ Between 100%; the gray-scale reticle corresponding to the semi-transmissive portion of the first photoresist portion has at least one slit to block a part of the light source to achieve a semi-transparent effect, and the slit adjustment control transmittance is between 0 and 100% .
  • the beneficial effects of the present invention are: in the prior art, the present invention forms a photoresist pattern layer on the gate insulating layer of the substrate through a halftone mask, wherein the substrate is provided with a polysilicon pattern layer, and the gate is provided with a polysilicon pattern layer.
  • the pole insulating layer covers the polysilicon pattern layer, so that the photoresist pattern layer forms a hollow portion corresponding to the to-be-doped region of the polysilicon pattern layer, and the first light-resisting portion is formed corresponding to the light-doped region of the polysilicon pattern layer, corresponding to the polysilicon pattern layer
  • the undoped region forms a second photoresist portion, and the first photoresist portion is thinner than the second photoresist portion, and the polysilicon pattern layer is doped once, thereby realizing a heavily doped region of the polysilicon pattern layer at a time and
  • the lightly doped area reduces the manufacturing process of LTPS and reduces costs.
  • 1 is a schematic view showing a process of twice doping an array substrate in the prior art
  • FIG. 2 is a schematic view showing the principle of light transmission of a cover film of the prior art
  • FIG. 3 is a schematic view showing a process of performing exposure and doping in the first embodiment of the doping method of the array substrate of the present invention, and showing a schematic structure of the first embodiment of the manufacturing apparatus of the array substrate of the present invention;
  • FIG. 4 is a schematic view showing the principle of light transmission of the halftone mask of FIG. 3;
  • FIG. 5 is a schematic view showing a process of performing exposure and doping in the second embodiment of the doping method of the array substrate of the present invention, and further showing a schematic structure of the second embodiment of the manufacturing apparatus of the array substrate of the present invention;
  • FIG. 6 is a schematic view showing the principle of light transmission of the halftone mask of FIG. 5;
  • FIG. 7 is a schematic flow chart of a first embodiment of a doping method of an array substrate of the present invention.
  • FIG. 1 is a schematic diagram of a prior art process of doping the array substrate twice. It should be noted that the placement state of the manufacturing equipment shown in FIG. 1 and the structure and state of each component of the array substrate are not in the same process stage in the actual production at the same time. FIG. 1 only shows different process stages for convenience of explanation ( The state in which the manufacturing equipment is placed under exposure and doping, the structure and state of the array substrate.
  • the manufacturing apparatus of the prior art array substrate includes an exposure device 10, a cover film 11, and a doping device 12.
  • the array substrate 13 includes the substrate 14, the polysilicon pattern layer 15, the gate insulating layer 16, and the gate pattern layer 17.
  • the cover film 11 includes an opaque portion 110 and a full light transmitting portion 111, wherein the light transmission principle of the cover film 11 is as shown in FIG. 2, wherein the downward convex portion 200 of the light intensity curve 20 indicates opaque, upward convex Portion 201 indicates light transmission.
  • FIG. 1 and FIG. 2 the doping process flow of the prior art array substrate is further illustrated.
  • a polysilicon layer 15 is formed on the substrate 14 of the array substrate 13, wherein a buffer layer 19 is further disposed between the polysilicon layer 15 and the substrate 14.
  • the polysilicon layer 15 is disposed on the buffer layer 19;
  • the insulating layer 16 is formed on the substrate 14 having the polysilicon layer 15, and the gate pattern layer 17 is formed on the gate insulating layer 16; finally formed on the gate insulating layer 16 having the gate pattern layer 17 by the exposure device 10.
  • the rear exposed portion is removed, that is, the exposed portion of the photoresist pattern layer 18 forms the hollow portion 181 during the presentation, and the unexposed portion forms a photoresist of a thickness after being highlighted.
  • the photoresist formed in the unexposed portion of the photoresist pattern layer 18 is etched to form the photoresist portion 180 in the unexposed portion of the photoresist pattern layer 18.
  • the hollow portion 181 of the photoresist pattern layer 18 corresponds to the region 110 to be heavily doped of the polysilicon layer 15.
  • the polysilicon layer 15 is heavily doped by the doping device 12 such that the heavily doped region 151 of the polysilicon layer 15 forms a heavily doped region.
  • the photoresist corresponding to the region to be doped is removed, and the polysilicon layer 15 is lightly doped a second time, so that the lightly doped region 152 of the polysilicon layer 15 forms a lightly doped region. So far, the polysilicon layer 15 is formed into a heavily doped region and a lightly doped region by two doping processes.
  • FIG. 3 is a schematic diagram of a process of performing exposure and doping in the first embodiment of the doping method of the array substrate according to the present invention.
  • the schematic structure of the first embodiment of the manufacturing apparatus of the array substrate in the present invention is also shown.
  • the array substrate includes an N-type transistor and a P-type transistor, wherein the N-type transistor is provided with a channel region, a lightly doped region, and a heavily doped region, and the P-type transistor has only a channel region and a heavily doped region.
  • the method is described for an N-type transistor of an array substrate.
  • the placement state of the manufacturing device shown in FIG. 3 and the structure and state of each component of the array substrate do not appear in the same process stage at the same time in practice, that is, FIG. 3 shows different process stages simultaneously for convenience of viewing.
  • the state in which the device is placed exposure and doping
  • the structure and state of each element of the array substrate Similarly, Figure 5 is the same.
  • the manufacturing apparatus of the array substrate 24 includes an exposure device 21, a halftone mask 22, and a doping device 23; the array substrate 24 includes a substrate 25, a polysilicon pattern layer 26, a gate insulating layer 27, and a gate pattern layer. 28 and buffer layer 30.
  • the exposure device 21 is configured to form a photoresist pattern layer 29 on the gate insulating layer 27 of the substrate 25 by using the halftone mask 22; the polysilicon pattern layer 26 is disposed on the substrate 25, and the polysilicon pattern layer 26 is covered by the gate insulating layer 27.
  • the photoresist pattern layer 29 is formed with the recessed portion 262 corresponding to the heavily doped region 262 of the polysilicon pattern layer 26, and the first photoresist portion 291 is formed corresponding to the lightly doped region 261 of the polysilicon pattern layer 26, corresponding to the polysilicon pattern layer.
  • the doped region 260 forms the second photoresist portion 290, and the first photoresist portion 291 is thinner than the second photoresist portion 290; the doping device 23 is used to dope the polysilicon pattern layer 26 once to form the polysilicon pattern layer at a time. A heavily doped region and a lightly doped region of 26.
  • the substrate 25 is a glass substrate; the polysilicon pattern layer 26 is formed on the substrate 25, the polysilicon pattern layer 26 is also referred to as an active layer, and a buffer layer is further disposed between the substrate 25 and the polysilicon pattern layer 26.
  • a polysilicon pattern layer 26 is formed on the buffer layer 30 of the substrate 25; a gate insulating layer 27 is formed on the substrate 25 having the polysilicon pattern layer 26, and a gate pattern layer 28 is formed on the gate insulating layer 27, wherein the gate is formed
  • the pole insulating layer 27 is an inorganic insulating material such as silicon oxide SiO2 or silicon nitride SiNX deposited on the gate pattern layer 28 to form a gate insulating layer 27 on the entire surface of the substrate 25; the photoresist pattern layer 29 has The gate insulating layer 27 of the gate pattern layer 28 is formed by the halftone mask 22 by the exposure device 21.
  • the halftone mask 22 includes an all-transmission portion 222 corresponding to the hollow portion 292 of the photoresist pattern layer 29, a semi-transmissive portion 221 corresponding to the first photoresist portion 291 of the photoresist pattern layer 29, and a corresponding portion.
  • the opaque portion 220 of the second photoresist portion 290 of the photoresist pattern layer 29, the light transmission principle of the halftone mask 22 is as shown in FIG. 4, wherein the first downward convex portion 310 of the light intensity curve 31 indicates no Light transmission, the second downward convex portion 311 represents semi-light transmission, and 312 represents light transmission.
  • the manufacturing process of the present embodiment is as follows. First, the photoresist pattern layer 29 is exposed through the halftone mask 22 by the exposure device 21, since the halftone mask 22 has the all-transmission portion 222, the semi-transmissive portion 221, and the opaque portion. The different transmittances of the portion 220, so that after exposure, a total of three exposure levels of the exposed portion, the half exposed portion, and the unexposed portion will be formed on the photoresist pattern layer 29.
  • the principle is that the photoresist pattern layer 29 is exposed through the all-transmission portion 222 of the halftone mask 22 by using the exposure device 21 to form an exposure portion, and at the same time, the semi-transmissive portion 221 of the halftone mask 22 is opposite to the photoresist pattern.
  • the layer 29 is subjected to half exposure to form a half exposure portion, and the opaque portion 220 of the halftone mask 22 is not exposed to the photoresist pattern layer 29 to form an unexposed portion.
  • the photoresist pattern layer 29 is subjected to a saliency process, and during the saliency process, the exposed portion is removed to form the vacant portion 292, so that two thicknesses of photoresist are formed on the cured photoresist pattern layer 29,
  • the photoresist is etched so that the half exposure portion forms the first photoresist portion 291, the unexposed portion forms the second photoresist portion 290, and the first photoresist portion 291 is thinner than the second photoresist portion 290.
  • the hollow portion 292 of the photoresist pattern layer 29 corresponds to the region 262 to be heavily doped of the polysilicon pattern layer 26
  • the first photoresist portion 291 corresponds to the region 261 to be lightly doped of the polysilicon pattern layer 26
  • the two photoresist portions 290 correspond to the undoped regions 260 of the polysilicon pattern layer 26.
  • the finally formed polysilicon pattern layer 26 includes a heavily doped region and a lightly doped region formed by one doping, that is, the heavily doped region 262 is doped to form a heavily doped region, and at the same time, the lightly doped region 261 is to be lightly doped. After doping, a lightly doped region is formed. Therefore, the final doping process is: doping the polysilicon pattern layer 26 by using the doping device 23, doping the low temperature polysilicon by using a diffusion method or an ion implantation method, and doping the polysilicon pattern layer 26 after doping. A heavily doped region and a lightly doped region are included.
  • a polysilicon film is formed by a low-pressure chemical vapor deposition method, that is, an active layer (not shown) is formed, and an active layer is doped with a phosphorus atom or a germanium atom to form a polysilicon pattern layer 26 by ion implantation. Since the step-like photoresist pattern layer 29 is formed on the gate insulating layer 27 covering the polysilicon pattern layer 26, the polysilicon pattern layer 26 is doped with a phosphorus atom or a germanium atom, and only one doping is required to form a heavily doped layer.
  • the principle is that the doping device 23 is doped to the heavily doped region 262 of the polysilicon pattern layer 26 by the hollow portion 292 of the photoresist pattern layer 29 to form a heavily doped region, and at the same time, A photoresist portion 291 is doped to the lightly doped region 261 to form a lightly doped region, and the heavily doped region and the lightly doped region of the polysilicon pattern layer 26 are both formed in one doping.
  • the undoped region 260 of the polysilicon pattern layer 26 will form a channel region, wherein the lightly doped region and the channel region constitute a conductive region of the polysilicon pattern layer 26.
  • the conductive region may also be covered with Light blocking layer (not shown) to reduce leakage current and improve display quality. So far, the doping process of the array substrate 24 is completed, and only one doping is required to form a heavily doped region and a lightly doped region on the polysilicon pattern layer 26.
  • the photoresist pattern layer 29 is exposed, half exposed, and unexposed by the halftone mask 22 by the exposure device 21 to form the hollow portion 292 of the photoresist pattern layer 29, the first photoresist portion 291, and
  • the second photoresist portion 290 is determined by the structure of the halftone mask 22.
  • the halftone mask 22 is a halftone mask (Halt-tone) Mask (abbreviated as HTM), wherein the semi-transmissive portion 221 of the halftone mask 22 is a semi-transmissive film, and the transmittance of the semi-transmissive film is between 0 and 100%.
  • HTM halftone mask
  • the photoresist pattern layer 29 is formed on the gate insulating layer 27 of the substrate 25 by the exposure device 21 by the exposure device 21, and the polysilicon pattern layer 26 is provided on the substrate 25, and the gate is provided.
  • the insulating layer 27 covers the polysilicon pattern layer 26, and the halftone mask 22 includes a fully transparent portion 222, a semi-transmissive portion 221, and an opaque portion 220.
  • the semi-transmissive portion 221 is a semi-transmissive film, and the semi-transparent film is controlled by The transmittance of the film 22 achieves a half-exposure effect, thereby forming a first photoresist portion 291 corresponding to the light-doped region 261 of the polysilicon pattern layer 26 on the photoresist pattern layer 29, corresponding to the polysilicon pattern layer 26 to be heavily doped
  • the impurity region 262 forms a hollow portion 292, and the second photoresist portion 290 is formed corresponding to the undoped region 260 of the polysilicon pattern layer 26, so that the photoresist pattern layer 29 is formed to include the hollow portion 292, the first photoresist portion 291, and the second light.
  • the stepped structure of the resist portion 290 utilizes the resist pattern layer 29 of the stepped structure to realize the primary doping of the polysilicon pattern layer 26 by the doping means 23 to form a heavily doped region and a lightly doped region.
  • FIG. 5 is a schematic diagram of a process for performing exposure and doping in the second embodiment of the doping method of the array substrate of the present invention, and further showing a second embodiment of the manufacturing apparatus of the array substrate of the present invention.
  • FIG. 6 is a schematic diagram of the light transmission principle of the halftone mask of FIG. 5 is similar to FIG. 3, and also shows the state of the manufacturing equipment under different process stages (exposure and doping), the structure and state of each component of the array substrate for convenience of viewing, and does not appear in the same process stage at the same time. .
  • the manufacturing apparatus includes an exposure device 21, a halftone mask 32, and a doping device 23, wherein the exposure device 21 and the doping device 23 are identical to those of FIG. 3, and details are not described herein again.
  • the array substrate 24 includes a substrate 25, a polysilicon pattern layer 26, a gate insulating layer 27, a gate pattern layer 28, and a buffer layer 30.
  • the structure and function of the array substrate 24 are the same as those of the array substrate in FIG. Narration.
  • the embodiment of FIG. 5 differs from the embodiment of FIG. 3 only in that the halftone mask 32 of FIG. 5 is a gray-scale mask (Gray-tone).
  • the half-tone mask 32 semi-transmissive portion 321 has at least one slit to block a part of the light source to achieve a semi-transparent effect, and the slit adjustment control transmittance is between 0 and 100%.
  • the halftone mask 32 can also be a single slit mask (Single Slit Mask; referred to as SSM).
  • FIG. 7 is a schematic flow chart of the first embodiment of the doping method of the array substrate of the present invention. As shown in FIG. 7, the doping process of the array substrate includes the following steps:
  • a polysilicon pattern layer 26 is formed on the substrate 25.
  • the polysilicon pattern layer 26 is formed on the substrate 25 by a low pressure chemical vapor deposition method or a direct method. In other embodiments, the polysilicon pattern layer 26 can also be formed by excimer laser crystallization.
  • a buffer layer 30 is further disposed between the substrate 25 and the polysilicon pattern layer 26, and the polysilicon pattern layer 26 is disposed on the buffer layer 30.
  • the substrate 25 is a glass substrate; the polysilicon pattern layer 26 is also referred to as an active layer, and includes a region 262 to be heavily doped, a region 261 to be lightly doped, and an undoped region 260, wherein the lightly doped region 261 is doped.
  • the light-doped region formed by the impurity and the channel region formed by the undoped region 260 constitute a conductive region of the polysilicon pattern layer 26.
  • the conductive region may also be covered with a light blocking layer (not shown). To reduce leakage current and improve display quality.
  • a gate insulating layer 27 is formed on the substrate 25 having the polysilicon pattern layer 26.
  • a gate pattern layer 28 is formed on the gate insulating layer 27.
  • the gate insulating layer 27 is an inorganic insulating material such as silicon oxide SiO 2 or silicon nitride SiNX deposited on the gate pattern layer 28 to form a gate insulating layer 27 on the entire surface of the substrate 25.
  • a photoresist pattern layer 29 is formed on the gate insulating layer 27 having the gate pattern layer 28 using the halftone mask 22.
  • a photoresist pattern layer 29 is formed on the gate insulating layer 27 of the substrate 25 by using the halftone mask 22. Since the polysilicon pattern layer 26 is provided on the substrate 25, the gate insulating layer 27 covers the polysilicon pattern layer 26 to form a photoresist pattern layer.
  • the recessed portion 262 corresponding to the polysilicon pattern layer 26 is formed with a hollow portion 292, and the first light resist portion 291 is formed corresponding to the lightly doped region 261 of the polysilicon pattern layer 26, and the undoped region 260 corresponding to the polysilicon pattern layer 26 is formed.
  • the polysilicon pattern layer 26 is doped once to form a heavily doped region and a lightly doped region of the polysilicon pattern layer 26 at a time.
  • the halftone mask 22 includes a fully transparent portion 222 , a semi-transmissive portion 221 , and an opaque portion 220 .
  • the photoresist pattern layer 29 is exposed by the exposure device 21 using the halftone mask 22, since the halftone mask 22 has the all-transmission portion 222, the semi-transmissive portion 221, and the opaque portion 220. Since the transmittance is different, a total of three exposure levels of the exposed portion, the half exposed portion, and the unexposed portion are formed on the photoresist pattern layer 29 after one exposure.
  • the principle is that the exposure device 21 exposes the photoresist pattern layer 29 through the all-transmission portion 222 of the halftone mask 22, and the portion of the photoresist pattern layer 29 corresponding to the all-transmission portion 222 forms an exposure portion. Similarly, half The semi-transmissive portion 221 of the mask 22 is half-exposed to the photoresist pattern layer 29 to form a half-exposure portion, and the opaque portion 220 of the halftone mask 22 is not exposed to the photoresist pattern layer 29 to form an unexposed portion. After the exposure, the photoresist pattern layer 29 is subjected to a saliency process.
  • the exposed portion is removed, and the exposed portion of the photoresist pattern layer 29 is formed corresponding to the hollow portion 292, thereby forming two thicknesses on the photoresist pattern layer 29.
  • the photoresist is etched such that the half exposure portion forms the first photoresist portion 291, the unexposed portion forms the second photoresist portion 290, and the first photoresist portion 291 is larger than the second photoresist portion 290. Thin, the photoresist pattern layer 29 is formed into a stepped structure including the hollow portion 292, the first photoresist portion 291, and the second photoresist portion 290.
  • the photoresist pattern layer 29 is exposed through the halftone mask 22 by the exposure device 21, and the photoresist pattern layer 29 is formed to form an exposure portion and a half exposure portion according to the light transmission characteristics of the halftone mask 22.
  • the three exposure levels of the unexposed portion form a corresponding hollow portion 292, the first photoresist portion 291 and the second photoresist portion 290 on the photoresist pattern layer 29, which are determined by the light transmission structure of the halftone mask 22.
  • the halftone mask 22 is a halftone mask (Halt-tone) Mask; referred to as HTM), the semi-transmissive portion 221 is a semi-transmissive film, and the transmittance of the semi-transmissive film is between 0 and 100%.
  • HTM halftone mask
  • HTM halftone mask
  • the light transmissive structure of the halftone mask 22 can also be as shown in FIG. 5, and the halftone mask 32 is a gray scale mask (Gray-tone).
  • Mask abbreviated as GTM
  • the semi-transmissive portion 321 has at least one slit to block a part of the light source to achieve a semi-transparent effect, and the slit adjustment control transmittance is between 0 and 100%.
  • the halftone mask 32 can also be a single slit mask (Single Slit Mask; referred to as SSM).
  • the array substrate generally includes an N-type transistor and a P-type transistor, wherein the N-type transistor is provided with a channel region, a lightly doped region, and a heavily doped region, and the P-type transistor has only a channel region and a heavily doped region
  • the polysilicon pattern layer 26 is N-type doped by the doping device 23, wherein the N-type doping refers to diffusion or ion implantation.
  • the normal polysilicon pattern layer 26 is doped with a phosphorus atom or a germanium atom.
  • the polysilicon pattern layer 26 Since the stepped photoresist pattern layer 29 is disposed on the polysilicon pattern layer 26, the polysilicon pattern layer 26 only needs to be doped once, and the region 262 to be heavily doped in the hollow portion 292 of the corresponding photoresist pattern layer 29 is formed.
  • the conductive region may also be covered with a light blocking layer (not shown) to reduce leakage current and improve display quality.
  • the semi-tone mask of the present invention has an all-transmission portion, a semi-transmissive portion, and an opaque portion, and a polysilicon pattern layer is disposed on the substrate, and the gate insulating layer is covered.
  • a polysilicon pattern layer wherein a photoresist pattern layer is formed on the gate insulating layer of the substrate by using a halftone mask, so that the photoresist pattern layer forms a hollow portion having a corresponding polysilicon pattern layer to be heavily doped, corresponding to the polysilicon pattern layer a first photoresist portion of the lightly doped region, a second photoresist portion corresponding to the undoped region of the polysilicon pattern layer, and the first photoresist portion is thinner than the second photoresist portion; thereby being on the polysilicon pattern layer Forming a stepped photoresist pattern layer, so that the polysilicon pattern layer is doped once, and a heavily doped region, a lightly doped region, and an undoped channel region can be formed

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Abstract

提供了一种阵列基板（24）的掺杂方法及制造设备，其方法包括：采用半调掩膜（22）在基板（25）的栅极绝缘层（27）上形成光阻图案层（29），其中，基板（25）上设有多晶硅图案层（26），栅极绝缘层（27）覆盖多晶硅图案层（26），光阻图案层（29）对应多晶硅图案层（26）的待重掺杂区域（262）形成镂空部（292），对应待轻掺杂区域（261）形成第一光阻部（291），对应不掺杂区域（260）形成第二光阻部（290），并且，第一光阻部（291）比第二光阻部（290）薄；对多晶硅图案层（26）进行一次掺杂，以一次形成该多晶硅图案层（26）的重掺杂区域（262）和轻掺杂区域（261）。通过上述方式，能够通过一次掺杂形成多晶硅图案层（26）的重掺杂区域（262）和轻掺杂区域（261），减少了LTPS阵列基板（24）的生产工艺。

Description

一种阵列基板的掺杂方法及制造设备
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板的掺杂方法及制造设备。
【背景技术】
TFT LCD液晶显示器可分为多晶硅(Poly-Si TFT)与非晶硅(a-Si TFT)两种，而由于低温多晶硅(Low Temperature Poly-silicon；简称LTPS)液晶显示器比传统的TFT-LCD非晶硅显示器具有高分辨率、高色彩饱和度、成本低廉的优势，LTPS-TFT LCD液晶显示器成为新一代液晶显示器的主流。
而LTPS工艺较为复杂，其中一点，就是TFT的关态电流（I off）较大，为了降低I off，通常采用双栅结构（dual gate）或者轻掺杂漏区域（Lightly doped drain；简称LDD）结构，现有技术中，为了实现LDD，一般需要两次掺杂（N型重掺杂和N型轻掺杂），例如先采用光罩进行曝光后进行一次N型重掺杂，再除去光阻，进行第二次N型轻掺杂，现有技术的两次掺杂不仅增加了制造工序，也增加了成本。
【发明内容】
有鉴于此，本发明提供一种阵列基板的掺杂方法及制造设备，实现一次掺杂形成多晶硅的重掺杂区域和轻掺杂区域。
为解决上述问题，本发明提供一种一种阵列基板的掺杂方法，包括：在基板上形成多晶硅图案层，在具有多晶硅图案层的基板上形成栅极绝缘层，在栅极绝缘层上形成栅极图案层，采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，栅极绝缘层覆盖多晶硅图案层，光阻图案层对应多晶硅图案层的待重掺杂区域形成镂空部，对应多晶硅图案层的待轻掺杂区域形成第一光阻部，对应多晶硅图案层的不掺杂区域形成第二光阻部，第一光阻部比第二光阻部薄；所述半调掩膜包括对应镂空部的全透光部，对应第一光阻部的半透光部，及对应第二光阻部的不透光部，利用半调掩膜对光阻图案层进行曝光，在光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对三种曝光层次分别进行刻蚀，以形成对应曝光部的镂空部、对应半曝光部的第一光阻部及对应未曝光部的第二光阻部；对多晶硅图案层进行一次掺杂，以一次形成多晶硅图案层的重掺杂区域和轻掺杂区域。
其中，对多晶硅图案层进行一次掺杂包括：采用扩散法或离子注入法对低温多晶硅进行掺杂，以形成多晶硅图案层，多晶硅图案层包括重掺杂区域和轻掺杂区域。
其中，半调掩膜为半色调光罩或灰阶光罩；半色调光罩对应第一光阻部的半透光部为半透光膜，半透光膜的透过率在0~100%之间；灰阶光罩对应第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0~100%之间。
为解决上述问题，本发明还提供的一种阵列基板的掺杂方法包括：采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，基板上设有多晶硅图案层，栅极绝缘层覆盖多晶硅图案层，该光阻图案层对应多晶硅图案层的待重掺杂区域形成镂空部，对应多晶硅图案层的待轻掺杂区域形成第一光阻部，对应多晶硅图案层的不掺杂区域形成第二光阻部，第一光阻部比第二光阻部薄；对多晶硅图案层进行一次掺杂，以一次形成该多晶硅图案层的重掺杂区域和轻掺杂区域。
其中，采用半调掩膜在基板上的栅极绝缘层上形成光阻图案层的步骤包括：在基板上形成多晶硅图案层；在具有多晶硅图案层的基板上形成栅极绝缘层；在栅极绝缘层上形成栅极图案层；采用半调掩膜在具有栅极图案层的栅极绝缘层上形成光阻图案层。
其中，该半调掩膜包括对应镂空部的全透光部，对应第一光阻部的半透光部，及对应第二光阻部的不透光部；采用半调掩膜在基板上的栅极绝缘层上形成光阻图案层包括：利用半调掩膜对光阻图案层进行曝光，在光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对三种曝光层次分别进行刻蚀，以形成对应曝光部的镂空部、对应半曝光部的第一光阻部及对应未曝光部的第二光阻部。
其中，对多晶硅图案层进行一次掺杂包括：采用扩散法或离子注入法对低温多晶硅进行掺杂，以形成多晶硅图案层，该多晶硅图案层包括重掺杂区域和轻掺杂区域。
其中，半调掩膜为半色调光罩或灰阶光罩；该半色调光罩对应所述第一光阻部的半透光部为半透光膜，半透光膜的透过率在0~100%之间；该灰阶光罩对应第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0~100%之间。
为解决上述问题，本发明提供的一种阵列基板的制造设备包括：曝光装置、半调掩膜以及掺杂装置；该曝光装置用于采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，基板上设有多晶硅图案层，栅极绝缘层覆盖多晶硅图案层，光阻图案层对应多晶硅图案层的待重掺杂区域形成镂空部，对应多晶硅图案层的待轻掺杂区域形成第一光阻部，对应多晶硅图案层的不掺杂区域形成第二光阻部，第一光阻部比第二光阻部薄；掺杂装置用于对多晶硅图案层进行一次掺杂，以一次形成多晶硅图案层的重掺杂区域和轻掺杂区域。
其中，多晶硅图案层在基板上形成，栅极绝缘层在具有多晶硅图案层的基板上形成，栅极图案层在栅极绝缘层上形成，光阻图案层在具有栅极图案层的栅极绝缘层利用曝光装置通过半调掩膜曝光形成。
其中，半调掩膜包括对应镂空部的全透光部，对应第一光阻部的半透光部，及对应于第二光阻部的不透光部，利用曝光装置通过半调掩膜对光阻图案层进行曝光，以在光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对三种曝光层次进行刻蚀，分别形成对应曝光部的镂空部、对应半曝光部的第一光阻部及对应未曝光部的第二光阻部。
其中，多晶硅图案层通过采用扩散法或离子注入法对低温多晶硅进行掺杂形成，多晶硅图案层包括重掺杂区域和轻掺杂区域。
其中，半调掩膜为半色调光罩或灰阶光罩；其中半色调光罩对应第一光阻部的半透光部为半透光膜，半透光膜的透过率在0~100%之间；灰阶光罩对应第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0~100%之间。
通过上述方案，本发明的有益效果是：区域别于现有技术，本发明通过半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，基板上设有多晶硅图案层，栅极绝缘层覆盖该多晶硅图案层，使光阻图案层对应多晶硅图案层的待重掺杂区域形成镂空部，对应多晶硅图案层的待轻掺杂区域形成第一光阻部，对应多晶硅图案层的不掺杂区域形成第二光阻部，并且第一光阻部比所述第二光阻部薄，对该多晶硅图案层进行一次掺杂，从而实现一次形成多晶硅图案层的重掺杂区域和轻掺杂区域，减少了LTPS的制造工艺，降低成本。
【附图说明】
图1是现有技术对阵列基板两次掺杂的工艺示意图；
图2是现有技术的罩膜的透光原理示意图；
图3是本发明中阵列基板的掺杂方法第一实施方式中进行曝光和掺杂的工艺示意图，图中还显示出本发明中阵列基板的制造设备第一实施方式的示意结构；
图4是图3中半调掩膜的透光原理示意图；
图5是本发明阵列基板的掺杂方法第二实施方式中进行曝光和掺杂的工艺示意图，图中还显示出本发明中阵列基板的制造设备第二实施方式的示意结构；
图6是图5中半调掩膜的透光原理示意图；
图7是本发明阵列基板的掺杂方法第一实施方式的流程示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
请参看图1，图1是现有技术的对阵列基板两次掺杂的工艺示意图。需要说明的是，图1中所显示的制造设备放置状态、阵列基板各元件的结构及状态并非实际生产中同一时间内的同一工艺阶段出现，图1只是为了方便说明而同时显示不同工艺阶段（曝光和掺杂）下的制造设备放置的状态、阵列基板的结构及状态。如图1所示，现有技术的阵列基板的制造设备包括曝光装置10、罩膜11及掺杂装置12。这里仅是对利用该制造设备对阵列基板13进行两次掺杂工艺作说明，阵列基板13包括基板14、多晶硅图案层15、栅极绝缘层16及栅极图案层17。
罩膜11包括不透光部110及全透光部111，其中罩膜11的透光原理如图2所示，其中光强曲线20的向下凸起部200表示不透光，向上凸起部201表示透光。结合图1和图2，进一步说明现有技术的阵列基板的掺杂工艺流程。首先是在阵列基板13的基板14上形成多晶硅图层15，其中，多晶硅图层15与基板14之间还设有缓冲层19，优选的，多晶硅图层15设置在缓冲层19上；栅极绝缘层16形成在具有多晶硅图层15的基板14上，再在栅极绝缘层16上形成栅极图案层17；最后利用曝光装置10在具有栅极图案层17的栅极绝缘层16上形成光阻图案层18，其中，利用曝光装置10通过罩膜11对光阻图案层18进行曝光，使罩膜11的全透光部111在光阻图案层18上形成曝光部，不透光部110在光阻图案层18上形成未曝光部，使得光阻图案层18形成曝光部及未曝光部两种曝光层次，进而对曝光后的光阻图案层18进行显彰处理，故而在显彰后曝光部被去除，即光阻图案层18的曝光部在显彰过程中形成镂空部181，而未曝光部在显彰后形成一种厚度的光刻胶。对光阻图案层18的未曝光部形成的光刻胶进行蚀刻，使光阻图案层18的未曝光部形成光阻部180。并且，光阻图案层18的镂空部181对应多晶硅图层15的待重掺杂区域151。通过掺杂装置12对多晶硅图层15进行第一次重掺杂，使多晶硅图层15的待重掺杂区域151形成重掺杂区域。去除待掺杂区域对应的光阻，对多晶硅图层15进行第二次轻掺杂，使多晶硅图层15的待轻掺杂区域152形成轻掺杂区域。至此，通过两次掺杂工艺，使多晶硅图层15形成重掺杂区域及轻掺杂区域。
然而，现有技术通过对多晶硅图层15进行两次掺杂，以形成重掺杂区域及轻掺杂区域，工艺较为复杂，并且成本较高。本发明提出了一种只需一次掺杂形成阵列基板的制造设备，请参看图3，图3是本发明中阵列基板的掺杂方法第一实施方式中进行曝光和掺杂的工艺示意图，图中还显示出本发明中阵列基板的制造设备第一实施方式的示意结构。通常阵列基板包括N型晶体管及P型晶体管，其中N型晶体管上设有沟道区域、轻掺杂区域及重掺杂区域，而P型晶体管上只有沟道区域及重掺杂区域，本实施方式是针对阵列基板的N型晶体管进行说明。
需要说明的是，图3所显示的制造设备放置状态、阵列基板各元件的结构、状态在实际中并非在同一时间内的同一工艺阶段出现，即图3是为了方便观看而同时显示不同工艺阶段（曝光和掺杂）下制造设备放置状态、阵列基板各元件的结构、状态。类似地，图5同理。如图3所示，阵列基板24的制造设备包括曝光装置21、半调掩膜22及掺杂装置23；阵列基板24包括基板25、多晶硅图案层26、栅极绝缘层27、栅极图案层28及缓冲层30。
其中，曝光装置21用于采用半调掩膜22在基板25的栅极绝缘层27上形成光阻图案层29；基板25上设有多晶硅图案层26，栅极绝缘层27覆盖多晶硅图案层26，使光阻图案层29对应多晶硅图案层26的待重掺杂区域262形成镂空部292，对应多晶硅图案层26的待轻掺杂区域261形成第一光阻部291，对应多晶硅图案层的不掺杂区域260形成第二光阻部290，并且第一光阻291部比第二光阻部290薄；掺杂装置23用于对多晶硅图案层26进行一次掺杂，以一次形成多晶硅图案层26的重掺杂区域和轻掺杂区域。
在本实施方式中，基板25为玻璃基板；多晶硅图案层26在基板25上形成，多晶硅图案层26又称为有源层，并且，在基板25与多晶硅图案层26之间还设有缓冲层30，多晶硅图案层26在基板25的缓冲层30上形成；栅极绝缘层27在具有多晶硅图案层26的基板25上形成，栅极图案层28在栅极绝缘层27上形成，其中，栅极绝缘层27是无机绝缘材料，如氧化硅SiO2或氮化硅SiNX沉积在栅极图案层28上形成，从而在基板25的整个表面上形成栅极绝缘层27；光阻图案层29在具有栅极图案层28的栅极绝缘层27上利用曝光装置21通过半调掩膜22形成。
在本实施方式中，半调掩膜22包括对应光阻图案层29的镂空部292的全透光部222、对应光阻图案层29的第一光阻部291的半透光部221及对应光阻图案层29的第二光阻部290的不透光部220，半调掩膜22的透光原理如图4所示，其中光强曲线31的第一向下凸起部310表示不透光，第二向下凸起部311表示半透光，312表示透光。
本实施方式的制造工艺如下，先是利用曝光装置21通过半调掩膜22对光阻图案层29进行曝光，由于半调掩膜22具有全透光部222、半透光部221及不透光部220的不同透光度，因而在一次曝光后在光阻图案层29上将会形成曝光部、半曝光部及未曝光部共三种曝光层次。其原理为：运用曝光装置21通过半调掩膜22的全透光部222对光阻图案层29进行曝光，形成曝光部，同时，半调掩膜22的半透光部221对光阻图案层29进行半曝光，形成半曝光部，半调掩膜22的不透光部220对光阻图案层29未曝光，形成未曝光部。
其次是对光阻图案层29进行显彰处理，在显彰处理期间，曝光部被去除而形成镂空部292，因而在显彰处理光阻图案层29上形成两种厚度的光刻胶，对光刻胶进行蚀刻，从而使半曝光部形成第一光阻部291，未曝光部形成第二光阻部290，并且，第一光阻部291比第二光阻部290薄。并且，在本实施方式中，光阻图案层29的镂空部292对应多晶硅图案层26的待重掺杂区域262，第一光阻部291对应多晶硅图案层26的待轻掺杂区域261，第二光阻部290对应多晶硅图案层26的不掺杂区域260。
由于最终形成的多晶硅图案层26包括通过一次掺杂形成的重掺杂区域和轻掺杂区域，即待重掺杂区域262经掺杂后形成重掺杂区域，同时，待轻掺杂区域261掺杂后形成轻掺区域。因此，最后的掺杂工艺为：利用掺杂装置23对多晶硅图案层26进行掺杂，其掺杂是通过采用扩散法或离子注入法对低温多晶硅进行掺杂，掺杂后使多晶硅图案层26包括重掺杂区域和轻掺杂区域。在本实施方式中，采用低压化学气相沉积方法形成多晶硅薄膜，即形成有源层（图未示），采用离子注入法向有源层掺杂磷原子或锑原子从而形成多晶硅图案层26，而由于覆盖多晶硅图案层26的栅极绝缘层27上形成有阶梯状的光阻图案层29，因而对多晶硅图案层26掺杂磷原子或锑原子，只是需要一次掺杂，便能形成重掺杂区域和轻掺杂区域，其原理为：掺杂装置23通过光阻图案层29的镂空部292向多晶硅图案层26的待重掺杂区域262一次掺杂形成重掺杂区域，同时，通过第一光阻部291向待轻掺杂区域261掺杂形成轻掺杂区域，该多晶硅图案层26的重掺杂区域和轻掺杂区域都是在一次掺杂中形成的。此外，多晶硅图案层26的不掺杂区域260将形成沟道区域，其中，轻掺杂区域和沟道区域组成多晶硅图案层26的导电区域，在其他实施方式中，导电区域上还可以覆盖有挡光层（图未示），以降低漏电流，改善显示质量。至此，对阵列基板24的掺杂工艺完成，只需要一次掺杂，便在多晶硅图案层26上形成重掺杂区域及轻掺杂区域。
在本实施方式中，通过曝光装置21利用半调掩膜22对光阻图案层29进行曝光、半曝光及未曝光，以形成光阻图案层29的镂空部292、第一光阻部291及第二光阻部290，是由半调掩膜22的结构决定的。
在本实施方式中，半调掩膜22为半色调光罩（Halt-tone Mask；简称HTM），其中，半调掩膜22的半透光部221为一个半透光膜，半透光膜的透过率在0~100%之间。
区域别于现有技术，本发明的通过曝光装置21利用半调掩膜22在基板25的栅极绝缘层27上形成光阻图案层29，由于基板25上设有多晶硅图案层26，栅极绝缘层27覆盖多晶硅图案层26，而半调掩膜22包括全透光部222、半透光部221及不透光部220，半透光部221为一半透光膜，通过控制半透光膜22的透过率实现半曝光的效果，从而在光阻图案层29上形成对应多晶硅图案层26的待轻掺杂区域261的第一光阻部291，对应多晶硅图案层26的待重掺杂区域262形成镂空部292，对应多晶硅图案层26的不掺杂区域260形成第二光阻部290，从而使光阻图案层29形成包括镂空部292、第一光阻部291及第二光阻部290的阶梯状结构，利用该阶梯状结构的光阻图案层29，从而实现通过掺杂装置23对多晶硅图案层26的一次掺杂形成重掺杂区域和轻掺杂区域。
请参看图5和图6，图5是本发明阵列基板的掺杂方法第二实施方式中进行曝光和掺杂的工艺示意图，图中还显示出本发明中阵列基板的制造设备第二实施方式的示意结构；图6是图5中半调掩膜的透光原理示意图。其中，图5与图3类似，也是为了方便观看而同时显示不同工艺阶段（曝光和掺杂）下制造设备放置状态、阵列基板各元件的结构、状态，并非在同一时间内的同一工艺阶段出现。图5中，制造设备包括曝光装置21、半调掩膜32及掺杂装置23，其中，曝光装置21和掺杂装置23与图3的一致，在此不再赘述。图5中，阵列基板24包括基板25、多晶硅图案层26、栅极绝缘层27、栅极图案层28及缓冲层30，它们的结构和功能与图3中的阵列基板一致，在此不再赘述。而图5的实施方式中与图3的实施方式的区别仅在于，图5的半调掩膜32为灰阶光罩(Gray-tone Mask；简称GTM)，半调掩膜32半透光部321具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0~100%之间。在其他实施方式中，半调掩膜32还可以为单夹缝掩膜（Single slit Mask；简称SSM）。
请一起参看图3和图7，图7是本发明阵列基板的掺杂方法第一实施方式的流程示意图，如图7所示，阵列基板的掺杂流程包括以下步骤：
S11：在基板25上形成多晶硅图案层26。
其中，采用低压化学气相沉积法或直接法在基板25上形成多晶硅图案层26。在其他实施方式中，多晶硅图案层26也可以采用准分子激光晶化法制成。优选的，基板25与多晶硅图案层26之间还设有缓冲层30，多晶硅图案层26设置在缓冲层30上。
其中，基板25为玻璃基板；多晶硅图案层26又称为有源层，它包括待重掺杂区域262、待轻掺杂区域261及不掺杂区域260，其中，待轻掺杂区域261掺杂后形成的轻掺杂区及不掺杂区域260形成的沟道区域组成多晶硅图案层26的导电区域，在其他实施方式中，导电区域上还可以覆盖有挡光层（图未示），以降低漏电流，改善显示质量。
S12：在具有多晶硅图案层26的基板25上形成栅极绝缘层27。
S13:在栅极绝缘层27上形成栅极图案层28。
其中，栅极绝缘层27是无机绝缘材料，如氧化硅SiO2或氮化硅SiNX沉积在栅极图案层28上形成，从而在基板25的整个表面上形成栅极绝缘层27。
S14：采用半调掩膜22在具有栅极图案层28的栅极绝缘层27上形成光阻图案层29。
采用半调掩膜22在基板25的栅极绝缘层27上形成光阻图案层29，由于基板25上设有多晶硅图案层26，栅极绝缘层27覆盖多晶硅图案层26，使光阻图案层29对应多晶硅图案层26的待重掺杂区域262形成镂空部292，对应多晶硅图案层26的待轻掺杂区域261形成第一光阻部291，对应多晶硅图案层26的不掺杂区域260形成第二光阻部290，且第一光阻部291比第二光阻部290薄；对多晶硅图案层26进行一次掺杂，以一次形成多晶硅图案层26的重掺杂区域和轻掺杂区域。
其中，半调掩膜22包括全透光部222、半透光部221及不透光部220。在本实施方式中，通过曝光装置21利用半调掩膜22对光阻图案层29进行曝光，由于半调掩膜22具有全透光部222、半透光部221及不透光部220的不同透光度，因而在一次曝光后在光阻图案层29上将会形成曝光部、半曝光部及未曝光部共3种曝光层次。其原理是，曝光装置21通过半调掩膜22的全透光部222对光阻图案层29进行曝光，全透光部222对应的光阻图案层29的部分形成曝光部，同理，半调掩膜22的半透光部221对光阻图案层29半曝光，形成半曝光部，半调掩膜22的不透光部220对光阻图案层29未曝光，形成未曝光部。曝光后对光阻图案层29进行显彰处理，在处理期间，曝光部被去除，使光阻图案层29的曝光部对应形成镂空部292，因而在光阻图案层29上形成两种厚度的光刻胶，对光刻胶进行蚀刻，从而使半曝光部形成第一光阻部291，未曝光部形成第二光阻部290，并且，第一光阻部291比第二光阻部290薄，使光阻图案层29形成包括镂空部292、第一光阻部291及第二光阻部290的阶梯状结构。
在本实施方式中，利用曝光装置21通过半调掩膜22对光阻图案层29进行曝光，使光阻图案层29形成根据半调掩膜22的透光特性形成曝光部、半曝光部及未曝光部三种曝光层次，从而在光阻图案层29上形成相应的镂空部292、第一光阻部291及第二光阻部290，是由半调掩膜22的透光结构决定的，在本实施方式中，半调掩膜22为半色调光罩（Halt-tone Mask；简称HTM），其半透光部221为一个半透光膜，半透光膜的透过率在0~100%之间。
此外，半调掩膜22的透光结构还可以如图5所示，半调掩膜32为灰阶光罩(Gray-tone Mask；简称GTM)，其半透光部321具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝调节控制透过率在0~100%之间。在其他实施方式中，半调掩膜32还可以为单夹缝掩膜（Single slit Mask；简称SSM）。
S15：去除半调掩膜22，对多晶硅图案层26一次掺杂，在多晶硅图案层26上形成重掺杂区域和轻掺杂区域。
由于阵列基板通常包括N型晶体管及P型晶体管，其中N型晶体管上设有沟道区域、轻掺杂区域及重掺杂区域，而P型晶体管上只有沟道区域及重掺杂区域，本实施方式是针对阵列基板的N型晶体管进行说明，因此在本实施方式中，通过掺杂装置23对多晶硅图案层26进行N型掺杂，其中，N型掺杂是指采用扩散法或离子注入法向多晶硅图案层26掺入磷原子或锑原子。由于多晶硅图案层26上设置有阶梯状的光阻图案层29，因而只需对多晶硅图案层26进行一次掺杂，便会在对应光阻图案层29的镂空部292的待重掺杂区域262掺杂成重掺杂区域，同时对应第一光阻部291的待轻掺杂区域261掺杂成轻掺杂区，此外，对应第二光阻部291的多晶硅图案层26的不掺杂区域260形成沟道区域，其中，轻掺杂区域和沟道区域组成多晶硅图案层26的导电区域，该多晶硅图案层26的重掺杂区域和轻掺杂区域都是在一次掺杂中形成的。在其他实施方式中，导电区域上还可以覆盖有挡光层（图未示），以降低漏电流，改善显示质量。
综上所述，区域别于现有技术，本发明的半调掩膜具有全透光部、半透光部及不透光部，并且，基板上设有多晶硅图案层，栅极绝缘层覆盖多晶硅图案层，通过利用半调掩膜在基板的栅极绝缘层上形成光阻图案层，从而使光阻图案层形成具有对应多晶硅图案层的待重掺杂区域的镂空部，对应多晶硅图案层的待轻掺杂区域的第一光阻部，对应多晶硅图案层的不掺杂区域的第二光阻部，并且，第一光阻部比第二光阻部薄；从而在多晶硅图案层上形成有阶梯状的光阻图案层，因而对多晶硅图案层进行一次掺杂，便能在多晶硅图案层上一次形成重掺杂区域、轻掺杂区域及不掺杂的沟道区域，实现一次掺杂形成多晶硅图案层的重掺杂区域和轻掺杂区域，减少LTPS阵列基板的生产工艺，降低成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板的掺杂方法，其中，所述掺杂方法包括：
    在基板上形成多晶硅图案层，在具有所述多晶硅图案层的基板上形成栅极绝缘层，在所述栅极绝缘层上形成栅极图案层，采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，所述栅极绝缘层覆盖所述多晶硅图案层，所述光阻图案层对应所述多晶硅图案层的待重掺杂区域形成镂空部，对应所述多晶硅图案层的待轻掺杂区域形成第一光阻部，对应所述多晶硅图案层的不掺杂区域形成第二光阻部，所述第一光阻部比所述第二光阻部薄；所述半调掩膜包括对应所述镂空部的全透光部，对应所述第一光阻部的半透光部，及对应所述第二光阻部的不透光部，利用所述半调掩膜对所述光阻图案层进行曝光，在所述光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对所述三种曝光层次分别进行刻蚀，以形成对应所述曝光部的所述镂空部、对应所述半曝光部的所述第一光阻部及对应所述未曝光部的所述第二光阻部；
    对所述多晶硅图案层进行一次掺杂，以一次形成所述多晶硅图案层的重掺杂区域和轻掺杂区域。
  2. 根据权利要求1所述的掺杂方法，其中，所述对所述多晶硅图案层进行一次掺杂包括：
    采用扩散法或离子注入法对低温多晶硅进行掺杂，以形成所述多晶硅图案层，所述多晶硅图案层包括所述重掺杂区域和所述轻掺杂区域。
  3. 根据权利要求1所述的掺杂方法，其中，所述半调掩膜为半色调光罩或灰阶光罩；其中，所述半色调光罩对应所述第一光阻部的半透光部为半透光膜，所述半透光膜的透过率在0~100%之间；所述灰阶光罩对应所述第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝调节控制透过率在0~100%之间。
  4. 一种阵列基板的掺杂方法，其中，所述掺杂方法包括：
    采用半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，所述基板上设有多晶硅图案层，所述栅极绝缘层覆盖所述多晶硅图案层，所述光阻图案层对应所述多晶硅图案层的待重掺杂区域形成镂空部，对应所述多晶硅图案层的待轻掺杂区域形成第一光阻部，对应所述多晶硅图案层的不掺杂区域形成第二光阻部，所述第一光阻部比所述第二光阻部薄；
    对所述多晶硅图案层进行一次掺杂，以一次形成所述多晶硅图案层的重掺杂区域和轻掺杂区域。
  5. 根据权利要求4所述的掺杂方法，其中，所述采用半调掩膜在基板上的栅极绝缘层上形成光阻图案层的步骤包括：
    在所述基板上形成所述多晶硅图案层；
    在具有所述多晶硅图案层的基板上形成所述栅极绝缘层；
    在所述栅极绝缘层上形成栅极图案层；
    采用所述半调掩膜在具有所述栅极图案层的栅极绝缘层上形成所述光阻图案层。
  6. 根据权利要求4所述的掺杂方法，其中，所述半调掩膜包括对应所述镂空部的全透光部，对应所述第一光阻部的半透光部，及对应所述第二光阻部的不透光部；
    所述采用半调掩膜在基板上的栅极绝缘层上形成光阻图案层包括：
    利用所述半调掩膜对所述光阻图案层进行曝光，在所述光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对所述三种曝光层次分别进行刻蚀，以形成对应所述曝光部的所述镂空部、对应所述半曝光部的所述第一光阻部及对应所述未曝光部的所述第二光阻部。
  7. 根据权利要求4所述的掺杂方法，其中，所述对所述多晶硅图案层进行一次掺杂包括：
    采用扩散法或离子注入法对低温多晶硅进行掺杂，以形成所述多晶硅图案层，所述多晶硅图案层包括所述重掺杂区域和所述轻掺杂区域。
  8. 根据权利要求4所述的掺杂方法，其中，所述半调掩膜为半色调光罩或灰阶光罩；其中，所述半色调光罩对应所述第一光阻部的半透光部为半透光膜，所述半透光膜的透过率在0~100%之间；所述灰阶光罩对应所述第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝调节控制透过率在0~100%之间。
  9. 一种阵列基板的制造设备，其中，所述制造设备包括：
    曝光装置、半调掩膜以及掺杂装置；
    所述曝光装置用于采用所述半调掩膜在基板的栅极绝缘层上形成光阻图案层，其中，所述基板上设有多晶硅图案层，所述栅极绝缘层覆盖所述多晶硅图案层，所述光阻图案层对应所述多晶硅图案层的待重掺杂区域形成镂空部，对应所述多晶硅图案层的待轻掺杂区域形成第一光阻部，对应所述多晶硅图案层的不掺杂区域形成第二光阻部，所述第一光阻部比所述第二光阻部薄；
    所述掺杂装置用于对所述多晶硅图案层进行一次掺杂，以一次形成所述多晶硅图案层的重掺杂区域和轻掺杂区域。
  10. 根据权利要求9所述的制造设备，其中，所述多晶硅图案层在所述基板上形成，所述栅极绝缘层在具有所述多晶硅图案层的基板上形成，所述栅极图案层在所述栅极绝缘层上形成；所述光阻图案层在具有所述栅极图案层的栅极绝缘层利用所述曝光装置通过所述半调掩膜曝光形成。
  11. 根据权利要求9所述的制造设备，其中，所述半调掩膜包括对应所述镂空部的全透光部，对应所述第一光阻部的半透光部，及对应所述第二光阻部的不透光部，利用所述曝光装置通过所述半调掩膜对所述光阻图案层进行曝光，以在所述光阻图案层上形成曝光部、半曝光部及未曝光部三种曝光层次，对所述三种曝光层次进行蚀刻，分别形成对应所述曝光部的所述镂空部、对应所述半曝光部的所述第一光阻部及对应所述未曝光部的所述第二光阻部。
  12. 根据权利要求9所述的制造设备，其中，所述多晶硅图案层通过采用扩散法或离子注入法对低温多晶硅进行掺杂形成，所述多晶硅图案层包括所述重掺杂区域和所述轻掺杂区域。
  13. 根据权利要求9所述的制造设备，其中，所述半调掩膜为半色调光罩或灰阶光罩；其中所述半色调光罩对应所述第一光阻部的半透光部为半透光膜，所述半透光膜的透过率在0~100%之间；所述灰阶光罩对应所述第一光阻部的半透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝调节控制透过率在0~100%之间。
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