WO2013166668A1 - 一种薄膜晶体管阵列基板及其制作方法 - Google Patents

一种薄膜晶体管阵列基板及其制作方法 Download PDF

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WO2013166668A1
WO2013166668A1 PCT/CN2012/075241 CN2012075241W WO2013166668A1 WO 2013166668 A1 WO2013166668 A1 WO 2013166668A1 CN 2012075241 W CN2012075241 W CN 2012075241W WO 2013166668 A1 WO2013166668 A1 WO 2013166668A1
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layer
metal layer
thin film
film transistor
transistor array
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PCT/CN2012/075241
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English (en)
French (fr)
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黄华
贾沛
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深圳市华星光电技术有限公司
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Priority to US13/574,564 priority Critical patent/US20130299838A1/en
Publication of WO2013166668A1 publication Critical patent/WO2013166668A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G02F1/133555—Transflectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present invention relates to the field of liquid crystal production technology, and in particular, to a method for fabricating a thin film transistor array substrate.
  • the transflective liquid crystal display is more and more used in the field of liquid crystal display because it can provide a clear image display effect in an outdoor environment exposed to direct sunlight.
  • TFT Thin Film Transistor
  • An object of the present invention is to provide a method for fabricating a thin film transistor array substrate, which solves the prior art process for forming a thin film transistor array substrate of a transflective liquid crystal display by adding a mask process to form a reflective layer.
  • the process is relatively complicated, the production difficulty and the production cost are high, and the technical problem of the production difficulty of the liquid crystal display is increased.
  • Another object of the present invention is to provide a thin film transistor array substrate to solve the prior art process of forming a reflective layer by adding a mask process, so that the process of the thin film transistor array substrate of the transflective liquid crystal display is relatively advanced.
  • the complexity, the difficulty of production and the high production cost increase the technical problems of the production difficulty of the liquid crystal display.
  • the invention provides a method for fabricating a thin film transistor array substrate, wherein the method comprises the following steps:
  • a transparent conductive layer and a second metal layer sequentially on the substrate, the second metal layer being sequentially formed by a combination of a second molybdenum metal layer, a second aluminum metal layer, and a third molybdenum metal layer; using a multi-stage adjustment mask Forming the transparent conductive layer and the second metal layer, forming a source and a drain including the transparent conductive layer and the second metal layer on the semiconductor layer, and forming a common on the gate insulating layer by the transparent conductive layer An electrode on which the reflective layer is formed by the second metal layer;
  • a planarization layer is deposited on the common electrode, the reflective layer, and the source, drain, and semiconductor layers constituting the thin film transistor, and the planarization layer is formed of a transparent insulating material.
  • the reflective layer is connected to the drain.
  • the reflective layer and the drain are spaced apart.
  • the multi-stage adjustment mask is a gray-scale tone mask, a stack layer mask or a halftone mask.
  • the first metal layer is sequentially formed by a combination of a first aluminum metal layer and a first molybdenum metal layer.
  • a semiconductor layer located above the gate is retained, and a reactive ion etching method is used.
  • the second metal layer is wet etched using a mixed solution of nitric acid, phosphoric acid, and acetic acid, and the transparent conductive layer is dry etched using a reactive ion etching method;
  • the transparent conductive layer is dry etched using a reactive ion etching method in a process of forming a common electrode from the transparent conductive layer on the gate insulating layer by using a multi-stage adjustment mask.
  • Another object of the present invention is to provide a method for fabricating a thin film transistor array substrate, which solves the problem of forming a thin film transistor array substrate of a transflective liquid crystal display by adding a mask process to form a reflective layer in the prior art.
  • the process process is relatively complicated, the production difficulty and the production cost are high, and the technical problem of the production difficulty of the liquid crystal display is increased.
  • the present invention provides a method of fabricating a thin film transistor array substrate, the method comprising the following steps:
  • a transparent conductive layer and a second metal layer sequentially on the substrate, patterning the transparent conductive layer and the second metal layer by using a multi-stage adjustment mask, forming the transparent conductive layer and the second layer on the semiconductor layer A source and a drain of the metal layer, a common electrode is formed on the gate insulating layer by the transparent conductive layer, and a reflective layer is formed on the common electrode by the second metal layer.
  • the reflective layer is connected to the drain.
  • the reflective layer and the drain are spaced apart.
  • the method further includes the following steps:
  • a planarization layer is deposited on the common electrode, the reflective layer, and the source, drain, and semiconductor layers constituting the thin film transistor, and the planarization layer is formed of a transparent insulating material.
  • the multi-stage adjustment mask is a gray-scale tone mask, a stack layer mask or a halftone mask.
  • the first metal layer is sequentially formed by a combination of a first aluminum metal layer and a first molybdenum metal layer
  • the second metal layer is sequentially composed of a second molybdenum metal layer, A two-aluminum metal layer and a third molybdenum metal layer are combined.
  • the first metal is mixed with a mixture of nitric acid, phosphoric acid, and acetic acid.
  • the layer is subjected to wet etching.
  • the semiconductor layer is patterned by a first photomask, and the semiconductor layer above the gate is left, and a reactive ion etching method is used.
  • a multi-stage adjustment mask is used to form a reflective layer on the semiconductor layer, and a source and a drain including the transparent conductive layer and the second metal layer are used.
  • the second metal layer is wet etched by a mixture of nitric acid, phosphoric acid and acetic acid, and the transparent conductive layer is dry etched by a reactive ion etching method;
  • the transparent conductive layer is dry etched using a reactive ion etching method in a process of forming a common electrode from the transparent conductive layer on the gate insulating layer by using a multi-stage adjustment mask.
  • Another object of the present invention is to provide a thin film transistor array substrate to solve the prior art process of forming a reflective layer by adding a mask process, so that the process of the thin film transistor array substrate of the transflective liquid crystal display is relatively advanced.
  • the complexity, the difficulty of production and the high production cost increase the technical problems of the production difficulty of the liquid crystal display.
  • the present invention provides a thin film transistor array substrate, the thin film transistor array substrate comprising:
  • each of the thin film transistors includes a gate, a gate insulating layer, a semiconductor layer, a source and a drain, the gate, the gate insulating layer, and the semiconductor
  • the layer and the source and the drain are sequentially formed on the substrate, and the source and the drain comprise a transparent conductive layer and a metal layer;
  • a reflective layer is formed by the second metal layer on the common electrode.
  • the reflective layer is connected to the drain.
  • the reflective layer and the drain are spaced apart.
  • a first mask process is performed to form a gate
  • a second mask process is performed. Forming a transparent conductive layer and a second metal layer on the substrate, and then performing a multi-stage adjustment mask to form a source, a drain, a common electrode, and a reflective layer, thereby forming a thin film transistor array substrate of the transflective liquid crystal display.
  • the invention simplifies the process procedure, reduces the manufacturing difficulty and the manufacturing cost, and improves the output of the liquid crystal display.
  • FIG. 1 is a cross-sectional view of a display panel and a backlight module according to a preferred embodiment of the present invention
  • 2A-2C are schematic cross-sectional views showing a process of a thin film transistor array substrate of a display panel according to a preferred embodiment of the present invention
  • 2D is a schematic cross-sectional view showing a process of a thin film transistor array substrate of a display panel according to another preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a display panel and a backlight module according to a preferred embodiment of the present invention.
  • the method for fabricating the thin film transistor (TFT) array substrate of the present embodiment can be applied to a manufacturing process of the display panel 100 (such as a liquid crystal display panel) to fabricate a protective layer of the transistor.
  • the liquid crystal display panel 100 can be disposed on the backlight module 200, thereby forming a liquid crystal display device.
  • the display panel 100 can include a first substrate 110 , a second substrate 120 , a liquid crystal layer 130 , a first polarizer 140 , and a second polarizer 150 .
  • the substrate material of the first substrate 110 and the second substrate 120 may be a glass substrate or a flexible plastic substrate.
  • the first substrate 110 may be, for example, a thin film transistor array substrate
  • the second substrate 120 may be, for example, colored. Filter (Color Filter, CF) substrate. It should be noted that in some embodiments, the color filter and the thin film transistor array substrate may also be disposed on the same substrate.
  • the liquid crystal layer 130 is formed between the first substrate 110 and the second substrate 120 .
  • the first polarizer 140 is a side on which the first substrate 110 is disposed, and is opposite to the liquid crystal layer 130 (ie, the light incident side of the first substrate 110), and the second polarizer 150 is a side on which the second substrate 120 is disposed, and is opposite.
  • the liquid crystal layer 130 ie, the light exiting side of the second substrate 120).
  • FIGS. 2A to 2C are schematic cross-sectional views showing a process of a thin film transistor array substrate of a display panel according to a preferred embodiment of the present invention.
  • a substrate 111 is provided on which a first metal layer is sequentially deposited.
  • the first metal layer is etched by the first photomask, and the gate electrode 112 is formed on the first metal layer to form the structure shown in FIG. 2A.
  • the first metal layer is preferably composed of a combination of a first aluminum metal layer and a first molybdenum metal layer, and of course other materials such as silver (Ag), copper (Cu), chromium (Cr), tungsten (W) may also be used. ), tantalum (Ta), titanium (Ti), metal nitride or an alloy of any combination thereof may also be a multilayer structure having a heat resistant metal film and a low resistivity film.
  • the first metal layer is preferably formed on the substrate 111 by a sputtering method.
  • the first metal layer is then patterned by a photolithography process and an etching process of the first photomask to form the gate electrode 112.
  • the first metal layer is preferably wet-etched using a mixed solution of nitric acid, phosphoric acid and acetic acid.
  • the gate insulating layer 113 and the semiconductor layer 114 are sequentially deposited on the substrate 111, and the semiconductor layer 114 is patterned by the second mask to retain the semiconductor layer above the gate 112. 114, the structure shown in Fig. 2B is formed.
  • the present invention preferably deposits the gate insulating layer 113 and the semiconductor layer 114 using chemical vapor deposition, such as plasma enhanced chemical vapor deposition (Plasma Enhanced). Chemical Vapor Deposition, In the PECVD method, it is of course possible to deposit the gate insulating layer 113 and the semiconductor layer 114 by other means, which are not enumerated here.
  • chemical vapor deposition such as plasma enhanced chemical vapor deposition (Plasma Enhanced).
  • the material of the gate insulating layer 113 is, for example, silicon nitride (SiNx) or silicon oxide (SiOx), and the material of the semiconductor layer 114 is preferably polysilicon (Poly-Silicon).
  • the semiconductor layer 114 may be first deposited with an amorphous silicon (a-Si) layer, and then the amorphous silicon layer is rapidly thermally annealed (Rapid). A thermal annealing, RTA) step of recrystallizing the amorphous silicon layer into a polysilicon layer.
  • the transparent conductive layer and the second metal layer are continuously deposited by sputtering on the substrate 111, and the thickness of the transparent conductive layer is preferably equal to or less than 100 ⁇ m. And patterning the transparent conductive layer and the second metal layer by using a multi-stage adjustment mask, and forming a source 116 and a drain 117 including the transparent conductive layer and the second metal layer on the semiconductor layer 114, A common electrode 115 is formed on the insulating layer by the transparent conductive layer, and a reflective layer 118 is formed on the common electrode 115 by the second metal layer.
  • the transparent conductive layer is preferably formed using a transparent conductive metal such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
  • a transparent conductive metal such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
  • the second metal layer is sequentially formed by a combination of a second molybdenum metal layer, a second aluminum metal layer, and a third molybdenum metal layer.
  • a second molybdenum metal layer e.g., silver (Ag), copper (Cu), and chromium may also be used.
  • the alloy of (Cr), tungsten (W), tantalum (Ta), titanium (Ti), metal nitride or any combination thereof may also be a multilayer structure having a heat resistant metal film and a low resistivity film.
  • the multi-segment adjustment mask adopts a multi-stage adjustment photomask
  • the multi-stage adjustment photomask can be, for example, a Gray Tone Mask (GTM), a stack diagram. Stacked Layer Mask (SLM) or Halftone Photomask (Half) Tone Mask, HTM), etc.
  • the multi-segment adjustment photomask may include an exposed region, a partially exposed region, and an unexposed region, etc., wherein the source 116 and the drain 117 are formed in the transparent conductive layer and the second metal layer, in the gate insulating layer
  • a common electrode 115 is formed on the transparent conductive layer, and a reflective layer 118 is formed on the common electrode 115 by the second metal layer.
  • the reflective layer 118 is connected to the drain 117.
  • a mixed solution of nitric acid, phosphoric acid and acetic acid for the first
  • Two metal layers are wet etched using RIE (Reactive Ion Etching: reactive ion etching) or the like: dry etching the transparent conductive layer; patterning the transparent conductive layer by a multi-stage adjustment mask to form the common electrode 115, preferably using an RIE etching method
  • RIE Reactive Ion Etching: reactive ion etching
  • a planarization layer may be deposited on the common electrode 115, the reflective layer 118, the semiconductor layer 114, and the source 116 and the drain 117 constituting the thin film transistor (not shown). Out) to achieve the effect of flattening and protecting components.
  • the planarization layer is formed of a transparent insulating material, and may of course be other materials, which are not enumerated here.
  • the transparent conductive layer and the second metal layer are patterned by using a multi-stage adjustment mask, and a source 116 and a drain 117 are formed on the semiconductor layer, and the gate is insulated.
  • a common electrode 115 is formed on the layer, and when the reflective layer 118 is formed by the second metal layer on the common electrode 115, the reflective layer 118 and the drain 117 are spaced apart, that is, disconnected.
  • a planarization layer can be deposited on the common electrode 115, the reflective layer 118, the semiconductor layer 114, and the source 116 and drain 117 constituting the thin film transistor.
  • the present invention also provides a thin film transistor array substrate including a substrate 111 and a plurality of thin film transistors disposed on the substrate 111.
  • the thin film transistor includes a gate electrode 112, a gate insulating layer 113, a semiconductor layer 114, a source electrode 116, and a drain electrode 117.
  • the gate electrode 112, the gate insulating layer 113, and the semiconductor layer 114 are sequentially formed on the substrate 111, and the gate electrode 112 is formed by a first metal layer deposited on the substrate 111.
  • the source 116 and the drain 117 are formed on the semiconductor layer 114 and are formed of a transparent conductive layer and a second metal layer which are sequentially deposited on the semiconductor layer 114.
  • the thin film transistor array substrate further includes a common electrode 115 and a reflective layer 118.
  • the common electrode 115 is formed of a transparent conductive layer deposited on the gate insulating layer 113, and the reflective layer 118 is formed of a second metal layer on the common electrode 115.
  • the thin film transistor matrix substrate and the manufacturing method of the display panel of the invention only need three photomasks to complete the thin film transistor array substrate of the transflective liquid crystal display, and the reflective layer is not required to be specially processed, thereby reducing the light required for the process The number of masks, which in turn reduces process cost and time.

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Abstract

一种薄膜晶体管阵列基板及其制作方法，在基板（111）上沉积第一金属层，利用第一光罩图案化形成栅极（112）；在基板（111）上沉积栅绝缘层（113）和半导体层（114），利用第二光罩图案化保留栅极（112）上方的半导体层（114）；在基板（111）上沉积透明导电层和第二金属层，利用多段式调整光罩来图案化形成源极（116）、漏极（117）和共通电极（115），在共通电极（115）上由第二金属层形成反射层（118）。

Description

一种薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及液晶生产技术领域，特别涉及一种薄膜晶体管阵列基板的制作方法。
 背景技术
随着液晶显示器的不断推广和普及，对液晶显示器的显示性能提出了很高的要求。以半穿半反型液晶显示器为例，由于半穿半反型液晶显示器在日光直射的户外环境下仍能够提供清晰的图像显示效果，因此被越来越多地应用在液晶显示领域。
在半穿半反型液晶显示器的薄膜晶体管(Thin Film Transistor，TFT) 阵列基板制程中，需使用多道光罩来进行光刻制程(Photo-lithography)，尤其是在形成透明的像素电极之后，需要额外的制程形成反射层，但是光罩次数越多则薄膜晶体管制程所需的成本越高，且增加制程时间及复杂度。
因此，现有技术中，由于需要专门增加一光罩制程形成反射层，使得半穿半反型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度。
 技术问题
本发明的一个目的在于提供一种薄膜晶体管阵列基板的制作方法，以解决现有技术中由于需要专门增加一光罩制程形成反射层，使得半穿半反型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
本发明的又一个目的在于提供一种薄膜晶体管阵列基板，以解决现有技术中由于需要专门增加一光罩制程形成反射层，使得半穿半反型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
 技术解决方案
本发明提供了一种薄膜晶体管阵列基板的制作方法，其中所述方法包括以下步骤：
提供基板；
在所述基板上沉积第一金属层，并利用第一光罩对所述第一金属层进行图案化，形成栅极；
在所述基板上依次沉积栅绝缘层和半导体层，利用第二光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
在所述基板上依次沉积透明导电层和第二金属层，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成；利用多段式调整光罩来图案化所述透明导电层和第二金属层，在半导体层上形成包括所述透明导电层和第二金属层的源极及漏极，在栅绝缘层上由所述透明导电层形成共通电极，在所述共通电极上由所述第二金属层形成反射层；
在所述共通电极，反射层、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
在本发明的薄膜晶体管阵列基板的制作方法中，其中所述反射层连接所述漏极。
在本发明的薄膜晶体管阵列基板的制作方法中，其中所述反射层和所述漏极间隔设置。
在本发明的薄膜晶体管阵列基板的制作方法中，其中所述多段式调整光罩为灰阶色调光罩、堆栈图层光罩或半色调光罩。
在本发明的薄膜晶体管阵列基板的制作方法中，其中所述第一金属层依次由第一铝金属层和第一钼金属层组合形成。
在本发明的薄膜晶体管阵列基板的制作方法中，其中利用第一光罩对所述第一金属层进行图案化形成栅极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀。
在本发明的薄膜晶体管阵列基板的制作方法中，其中利用第一光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层，使用反应离子刻蚀方法。
在本发明的薄膜晶体管阵列基板的制作方法中，其中利用多段式调整光罩在半导体层上形成反射层、以及包括所述透明导电层和第二金属层的源极及漏极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，使用反应离子刻蚀方法对所述透明导电层进行干法刻蚀；
利用多段式调整光罩在栅绝缘层上由所述透明导电层形成共通电极的过程中，使用反应离子刻蚀方法对所述透明导电层进行干法刻蚀。
本发明的另一个目的在于提供一种薄膜晶体管阵列基板的制作方法，以解决现有技术中由于需要专门增加一光罩制程形成反射层，使得半穿半反型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
为解决上述问题，本发明提供了一种薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：
提供基板；
在所述基板上沉积第一金属层，并利用第一光罩对所述第一金属层进行图案化，形成栅极；
在所述基板上依次沉积栅绝缘层和半导体层，利用第二光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
在所述基板上依次沉积透明导电层和第二金属层，利用多段式调整光罩来图案化所述透明导电层和第二金属层，在半导体层上形成包括所述透明导电层和第二金属层的源极及漏极，在栅绝缘层上由所述透明导电层形成共通电极，在所述共通电极上由所述第二金属层形成反射层。
在本发明的薄膜晶体管阵列基板的制作方法中，所述反射层连接所述漏极。
在本发明的薄膜晶体管阵列基板的制作方法中，所述反射层和所述漏极间隔设置。
在本发明的薄膜晶体管阵列基板的制作方法中，在形成所述源极、漏极、共通电极和反射层后，所述方法还包括以下步骤：
在所述共通电极，反射层、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述多段式调整光罩为灰阶色调光罩、堆栈图层光罩或半色调光罩。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
在本发明的薄膜晶体管阵列基板的制作方法中，利用第一光罩对所述第一金属层进行图案化形成栅极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀。
在本发明的薄膜晶体管阵列基板的制作方法中，利用第一光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层，使用反应离子刻蚀方法。
在本发明的薄膜晶体管阵列基板的制作方法中，利用多段式调整光罩在半导体层上形成反射层、以及包括所述透明导电层和第二金属层的源极及漏极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，使用反应离子刻蚀方法对所述透明导电层进行干法刻蚀；
利用多段式调整光罩在栅绝缘层上由所述透明导电层形成共通电极的过程中，使用反应离子刻蚀方法对所述透明导电层进行干法刻蚀。
本发明的又一个目的在于提供一种薄膜晶体管阵列基板，以解决现有技术中由于需要专门增加一光罩制程形成反射层，使得半穿半反型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
为解决上述问题，本发明提供了一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
基板；
多个薄膜晶体管，设置于所述基板上，其中每一所述薄膜晶体管包括栅极、栅绝缘层、半导体层、源极及漏极，所述栅极、所述栅绝缘层、所述半导体层及所述源极及漏极是依序形成于所述基板上，所述源极及所述漏极包括透明导电层和金属层；
共通电极，形成于所述栅绝缘层上；
反射层，由所述共通电极上的所述第二金属层形成。
在本发明的薄膜晶体管阵列基板中，其中所述反射层连接所述漏极。
在本发明的薄膜晶体管阵列基板中，其中所述反射层和所述漏极间隔设置。
 有益效果
本发明相对于现有技术，通过所述基板上沉积第一金属层后进行第一光罩制程形成栅极，在所述基板上继续沉积栅绝缘层和半导体层后进行第二光罩制程，在所述基板上继续沉积透明导电层和第二金属层后进行多段式调整光罩形成源极、漏极、共通电极以及反射层，进而形成半穿半反型液晶显示器的薄膜晶体管阵列基板，本发明简化了工艺程序，降低了制作难度以及制作成本，提高了液晶显示器的产量。
 附图说明
图1为本发明一较佳实施例的显示面板与背光模块的剖面示意图；
图2A-2C为本发明一较佳实施例的显示面板的薄膜晶体管阵列基板的制程剖面示意图；
图2D为本发明另一较佳实施例的显示面板的薄膜晶体管阵列基板的制程剖面示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的一较佳实施例的显示面板与背光模块的剖面示意图。
其中，本实施例的薄膜晶体管(TFT)阵列基板的制作方法可应用于显示面板100(譬如液晶显示面板)的制造过程中，以制造晶体管的保护层。当应用本实施例的显示面板100来制造一液晶显示装置时，可设置液晶显示面板100于背光模块200上，因而形成液晶显示装置。此显示面板100可包括第一基板110、第二基板120、液晶层130、第一偏光片140及第二偏光片150。第一基板110和第二基板120的基板材料可为玻璃基板或可挠性塑料基板，在本实施例中，第一基板110可例如为薄膜晶体管阵列基板，而第二基板120可例如为彩色滤光片(Color Filter，CF)基板。值得注意的是，在一些实施例中，彩色滤光片和薄膜晶体管阵列基板亦可配置在同一基板上。
如图1所示，液晶层130是形成于第一基板110与第二基板120之间。第一偏光片140是设置第一基板110的一侧，并相对于液晶层130(即第一基板110的入光侧)，第二偏光片150是设置第二基板120的一侧，并相对于液晶层130(即第二基板120的出光侧)。
请参照图2A至图2C，其显示依照本发明的一较佳实施例的显示面板的薄膜晶体管阵列基板的制程剖面示意图。
在图2A中，提供基板111，在所述基板111上依次沉积第一金属层。利用第一光罩对所述第一金属层进行刻蚀处理，在所述第一金属层形成栅极112，形成图2A所示的结构。
其中，所述第一金属层优选由第一铝金属层和第一钼金属层组合构成，当然也可以使用其它材料，譬如银（Ag）、铜（Cu）、铬（Cr）、钨（W）、钽（Ta）、钛（Ti）、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构。
在具体实施过程中，优选采用溅射法在基板111形成所述第一金属层。之后通过第一光罩的光刻程序和蚀刻程序对所述第一金属层进行图案化处理形成所述栅极112。其中，利用第一光罩在所述第一金属层形成所述栅极112的过程中，优选使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀。
请继续参阅图2B，继续在所述基板111上依次沉积栅绝缘层113和半导体层114，利用第二光罩对所述半导体层114进行图案化，保留位于所述栅极112上方的半导体层114，形成图2B所示的结构。
本发明优选使用化学气相沉积法沉积所述栅绝缘层113和所述半导体层114，譬如等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition, PECVD)方式，当然还可以通过其它方式沉积所述栅绝缘层113和所述半导体层114，此处不一一列举。
所述栅绝缘层113的材料例如为氮化硅(SiNx)或氧化硅(SiOx)，所述半导体层114的材料优选为多晶硅(Poly-Silicon)。在本实施例中，所述半导体层114可先沉积一非晶硅(a-Si)层，接着，对该非晶硅层进行快速热退火(Rapid thermal annealing, RTA)步骤，藉以使该非晶硅层再结晶成一多晶硅层。
请参阅图2C， 继续在所述基板111上通过溅射法依次沉积形成透明导电层和第二金属层，所述透明导电层的厚度优选是等于或小于100μm。并利用多段式调整光罩对所述透明导电层和第二金属层进行图案化，在半导体层114上形成包括所述透明导电层和第二金属层的源极116及漏极117，在栅绝缘层上由所述透明导电层形成共通电极115，在所述共通电极115上由所述第二金属层形成反射层118。
所述透明导电层优选使用透明导电金属形成，譬如铟锡氧化物（ITO）、锡氧化物（TO）、铟锌氧化物（IZO）以及铟锡锌氧化物（ITZO）。
优选的，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成，当然也可以使用其它材料，譬如银（Ag）、铜（Cu）、铬（Cr）、钨（W）、钽（Ta）、钛（Ti）、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构。
在具体实施过程中，所述多段式调整光罩采用一多段式调整光掩膜，所述多段式调整光掩膜可例如为灰阶色调光掩膜(Gray Tone Mask，GTM)、堆栈图层光掩膜(Stacked Layer Mask，SLM)或半色调光掩膜(Half Tone Mask，HTM)等。所述多段式调整光掩膜可包括曝光区域、部分曝光区域以及未曝光区域等，籍以在所述透明导电层和第二金属层形成所述源极116和漏极117，在栅绝缘层上由所述透明导电层形成共通电极115，在所述共通电极115上由所述第二金属层形成反射层118。其中，所述反射层118连接所述漏极117。
其中，通过多段式调整光罩在所述透明导电层和第二金属层形成所述源极116、漏极117以及反射层118过程中，优选使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，采用RIE（Reactive Ion Etching：反应离子刻蚀）等刻蚀方法对所述透明导电层进行干法刻蚀；通过多段式调整光罩来图案化所述透明导电层形成共通电极115过程中，优选采用RIE刻蚀方法对所述透明导电层进行干法刻蚀。
在一实施例中，在形成图2C所示结构后，可在共通电极115，反射层118、半导体层114以及构成薄膜晶体管的源极116和漏极117上沉积一平坦化层（图未示出），以达到平坦化及保护组件的功效。优选的，所述平坦化层由透明绝缘材质形成，当然也可以为其它材质，此处不一一列举。
在另一实施例中，请参阅图2D，在利用多段式调整光罩对所述透明导电层和第二金属层进行图案化，在半导体层上形成源极116及漏极117，在栅绝缘层上形成共通电极115，在所述共通电极115上由所述第二金属层形成反射层118时，使得所述反射层118和所述漏极117间隔设置，即断开连接。当然，在形成图2D所示结构后，仍可在共通电极115，反射层118、半导体层114以及构成薄膜晶体管的源极116和漏极117上沉积一平坦化层。
本发明还提供一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括基板111以及设置在所述基板111上的多个薄膜晶体管。
所述薄膜晶体管包括栅极112、栅绝缘层113、半导体层114、源极116和漏极117。所述栅极112、所述栅绝缘层113、所述半导体层114是依序形成于所述基板111上，栅极112由沉积在基板111上的第一金属层形成。所述源极116及所述漏极117是位于半导体层114上，由依次沉积在所述半导体层114上的透明导电层和第二金属层形成。
所述薄膜晶体管阵列基板还包括共通电极115和反射层118。所述共通电极115由沉积在所述栅绝缘层113上的透明导电层形成，所述反射层118由共通电极115上的第二金属层形成。
本发明的薄膜晶体管矩阵基板及显示面板的制造方法仅需三道光掩膜来完成半穿半反型液晶显示器的薄膜晶体管阵列基板，无需专门的制程制作反射层，因而可减少制程所需的光掩膜数，进而减少制程成本及时间。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (18)

  1. 一种薄膜晶体管阵列基板的制作方法，其中所述方法包括以下步骤：
    提供基板；
    在所述基板上沉积第一金属层，并利用第一光罩对所述第一金属层进行图案化，形成栅极；
    在所述基板上依次沉积栅绝缘层和半导体层，利用第二光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
    在所述基板上依次沉积透明导电层和第二金属层，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成；利用多段式调整光罩来图案化所述透明导电层和第二金属层，在半导体层上形成包括所述透明导电层和第二金属层的源极及漏极，在栅绝缘层上由所述透明导电层形成共通电极，在所述共通电极上由所述第二金属层形成反射层；
    在所述共通电极，反射层、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
  2. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中所述反射层连接所述漏极。
  3. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中所述反射层和所述漏极间隔设置。
  4. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中所述多段式调整光罩为灰阶色调光罩、堆栈图层光罩或半色调光罩。
  5. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中所述第一金属层依次由第一铝金属层和第一钼金属层组合形成。
  6. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中利用第一光罩对所述第一金属层进行图案化形成栅极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀。
  7. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中利用第一光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层，使用反应离子刻蚀方法。
  8. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中利用多段式调整光罩在半导体层上形成反射层、以及包括所述透明导电层和第二金属层的源极及漏极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，使用反应离子刻蚀方法对所述透明导电层进行干法刻蚀；
    利用多段式调整光罩在栅绝缘层上由所述透明导电层形成共通电极的过程中，使用反应离子刻蚀方法对所述透明导电层进行干法刻蚀。
  9. 一种薄膜晶体管阵列基板的制作方法，其中所述方法包括以下步骤：
    提供基板；
    在所述基板上沉积第一金属层，并利用第一光罩对所述第一金属层进行图案化，形成栅极；
    在所述基板上依次沉积栅绝缘层和半导体层，利用第二光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
    在所述基板上依次沉积透明导电层和第二金属层，利用多段式调整光罩来图案化所述透明导电层和第二金属层，在半导体层上形成包括所述透明导电层和第二金属层的源极及漏极，在栅绝缘层上由所述透明导电层形成共通电极，在所述共通电极上由所述第二金属层形成反射层。
  10. 根据权利要求9所述的薄膜晶体管阵列基板的制作方法，其中所述反射层连接所述漏极。
  11. 根据权利要求9所述的薄膜晶体管阵列基板的制作方法，其中所述反射层和所述漏极间隔设置。
  12. 根据权利要求9所述的薄膜晶体管阵列基板的制作方法，其中在形成所述源极、漏极、共通电极和反射层后，所述方法还包括以下步骤：
    在所述共通电极，反射层、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
  13. 根据权利要求9所述的薄膜晶体管阵列基板的制作方法，其中所述多段式调整光罩为灰阶色调光罩、堆栈图层光罩或半色调光罩。
  14. 根据权利要求9所述的薄膜晶体管阵列基板的制作方法，其中所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
  15. 根据权利要求9所述的薄膜晶体管阵列基板的制作方法，其中利用第一光罩对所述第一金属层进行图案化形成栅极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀。
  16. 根据权利要求9所述的薄膜晶体管阵列基板的制作方法，其中利用第一光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层，使用反应离子刻蚀方法。
  17. 根据权利要求9所述的薄膜晶体管阵列基板的制作方法，其中利用多段式调整光罩在半导体层上形成反射层、以及包括所述透明导电层和第二金属层的源极及漏极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，使用反应离子刻蚀方法对所述透明导电层进行干法刻蚀；
    利用多段式调整光罩在栅绝缘层上由所述透明导电层形成共通电极的过程中，使用反应离子刻蚀方法对所述透明导电层进行干法刻蚀。
  18. 一种薄膜晶体管阵列基板，其中所述薄膜晶体管阵列基板包括：
    基板；
    多个薄膜晶体管，设置于所述基板上，其中每一所述薄膜晶体管包括栅极、栅绝缘层、半导体层、源极及漏极，所述栅极、所述栅绝缘层、所述半导体层及所述源极及漏极是依序形成于所述基板上，所述源极及所述漏极包括透明导电层和金属层；
    共通电极，形成于所述栅绝缘层上；
    反射层，由所述共通电极上的所述第二金属层形成。
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