WO2013082755A1 - 液晶基板及其制作方法 - Google Patents

液晶基板及其制作方法 Download PDF

Info

Publication number
WO2013082755A1
WO2013082755A1 PCT/CN2011/083528 CN2011083528W WO2013082755A1 WO 2013082755 A1 WO2013082755 A1 WO 2013082755A1 CN 2011083528 W CN2011083528 W CN 2011083528W WO 2013082755 A1 WO2013082755 A1 WO 2013082755A1
Authority
WO
WIPO (PCT)
Prior art keywords
transparent electrode
electrode layer
liquid crystal
crystal substrate
insulating layer
Prior art date
Application number
PCT/CN2011/083528
Other languages
English (en)
French (fr)
Inventor
徐亮
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/380,895 priority Critical patent/US9366905B2/en
Publication of WO2013082755A1 publication Critical patent/WO2013082755A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G02F1/139—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent
    • G02F1/1393—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133776—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers having structures locally influencing the alignment, e.g. unevenness

Definitions

  • the present invention relates to the field of liquid crystal display panel manufacturing, and more particularly to a liquid crystal display panel in a vertical alignment display mode and a method of fabricating the same.
  • liquid crystal display panels Due to its low weight, small size and low energy consumption, liquid crystal display panels have gradually become mainstream flat panel display devices.
  • the vertical alignment display mode includes multi-domain vertical alignment display mode (MVA: Multi-domain) Vertical Alignment), graphical vertical alignment display mode (PVA: Patterned Vertical Alignment), polymer stabilized vertical alignment display mode (PSVA: Polymer Sustained Vertical Alignment).
  • MVA Multi-domain vertical alignment display mode
  • PVA Patterned Vertical Alignment
  • PSVA Polymer Sustained Vertical Alignment
  • FIG. 1A is a schematic structural view of a first transparent electrode layer of a liquid crystal display panel of a conventional polymer stable vertical alignment display mode
  • FIG. 1B is a polymer stable vertical alignment of FIG.
  • FIG. 1C is a schematic structural view of the A-A' cross section of the liquid crystal display panel of the polymer stable vertical alignment display mode of FIG. 1A when the display mode liquid crystal display panel is not energized;
  • FIG. 1A is a schematic structural view of a first transparent electrode layer of a liquid crystal display panel of a conventional polymer stable vertical alignment display mode
  • FIG. 1B is a polymer stable vertical alignment of FIG.
  • FIG. 1C is a schematic structural view of the A-A' cross section of the liquid crystal display panel of the polymer stable vertical alignment display mode of FIG. 1A when the display mode liquid crystal display panel is not energized
  • FIG. 1A is a schematic structural view of a first transparent electrode layer of a liquid crystal display panel of a conventional polymer stable vertical alignment display mode
  • the liquid crystal display panel 100 of the display mode includes CF (Color) Filter, color filter layer) substrate 110, TFT (Thin Film Transistor, thin film field effect transistor) substrate 120 and liquid crystal molecules 130 are provided with a transparent electrode layer 140 inside the CF substrate 110 and the TFT substrate 120, and a transparent electrode layer 141 on the TFT substrate 120 is formed with a slit 142.
  • a reaction monomer is added to the liquid crystal molecule 130, and these reactive monomers are reacted by applying a voltage and ultraviolet light to form a polymer chain 150, thereby tilting the liquid crystal molecules by a predetermined angle, thereby accelerating the response of the liquid crystal molecules 130. speed.
  • the transparent electrode layer 140 of the TFT substrate 120 has the slit 142, the electric field driving force at the slit 142 is weak, resulting in poor transmittance of the liquid crystal display panel 100 at the slit 142.
  • An object of the present invention is to provide a liquid crystal substrate by increasing the electric field intensity at the slit of the transparent electrode layer and a method for fabricating the same, to solve the problem of insufficient electric field strength at the gap of the existing polymer stable vertical alignment display mode.
  • the present invention relates to a liquid crystal substrate having a transparent electrode layer formed with a slit, and a transparent electrode layer disposed under the slit.
  • the transparent electrode layer includes a first transparent electrode layer and a second transparent electrode layer, the second transparent electrode layer forms the slit, and the first transparent electrode layer is disposed at the Below the gap.
  • a third insulating layer is provided between the first transparent electrode layer and the second transparent electrode layer.
  • the liquid crystal substrate further includes a second insulating layer, the first transparent electrode layer is disposed on the second insulating layer, and the third insulating layer covers the second insulating layer a layer and a first transparent electrode layer.
  • the liquid crystal substrate further includes a second insulating layer, the first transparent electrode layer is disposed on the second insulating layer, and the third insulating layer covers only the first Transparent electrode layer.
  • the second transparent electrode layer is made of the same material as the first transparent electrode layer.
  • the second transparent electrode layer is disposed on a surface of the first transparent electrode layer.
  • the second transparent electrode layer is different from the material of the first transparent electrode layer.
  • the liquid crystal substrate includes a second insulating layer, the second insulating layer is formed with a plurality of grooves, and the transparent electrode layer is disposed in the groove And on the second insulating layer, the slit is disposed above the groove.
  • the groove penetrates the second insulating layer.
  • the liquid crystal substrate further includes a plurality of data lines and a drain, and the transparent electrode layer is connected to the drain through the contact holes.
  • the invention further relates to a method for fabricating a liquid substrate, comprising the steps of: A, forming a transparent electrode layer on the substrate; B, forming a slit on the transparent electrode layer, and having a transparent electrode layer under the slit.
  • the step A is specifically: forming a first transparent electrode layer and a second transparent electrode layer on the substrate; the step B is specifically: at the second transparent electrode A gap is formed in the layer.
  • the first transparent electrode layer in a polycrystalline state is formed under conditions of more than 100 degrees Celsius.
  • the second transparent electrode layer in an amorphous state is formed at room temperature in the step B.
  • the method further includes the step of: annealing the liquid crystal substrate to convert the second transparent electrode layer in the amorphous state into a polycrystalline state.
  • the slit is formed by etching a second transparent electrode layer by an etching solution, and the etching liquid is a weak acid.
  • the step A is specifically: forming a first transparent electrode layer, a third insulating layer, and a second transparent electrode layer on the substrate.
  • the third insulating layer is provided only between the first transparent electrode layer and the second transparent electrode layer.
  • the step A is specifically: forming a second insulating layer on the substrate, forming a recess on the second insulating layer, and on the second insulating layer
  • the transparent electrode layer is formed in the recess.
  • the electric field intensity at the slit is increased, thereby increasing the light transmittance of the liquid crystal display panel.
  • 1A is a schematic structural view of a first transparent electrode layer of a liquid crystal display panel in a polymer stable vertical alignment display mode
  • FIG. 1B is a schematic structural view of the A-A cross section of the liquid crystal display panel of the polymer stable vertical alignment display mode of FIG. 1A when the liquid crystal display panel is not energized;
  • FIG. 1C is a schematic structural view of the A-A cross section of the liquid crystal display panel of the polymer stable vertical alignment display mode of FIG. 1A when it is energized;
  • FIG. 2 is a schematic plan view showing a planar structure of a liquid crystal substrate of the present invention
  • FIG. 3 is a schematic cross-sectional view showing a first preferred embodiment of a liquid crystal substrate of the present invention
  • FIG. 4 is a flow chart showing a method of fabricating the liquid crystal substrate shown in FIG. 3;
  • Figure 5 is a cross-sectional view showing a second preferred embodiment of the liquid crystal substrate of the present invention.
  • Figure 6 is a cross-sectional view showing a third preferred embodiment of the liquid crystal substrate of the present invention.
  • FIG. 7 is a schematic view showing a method of fabricating the liquid crystal substrate shown in FIG. 6;
  • Figure 8 is a cross-sectional view showing a fourth preferred embodiment of the liquid crystal substrate of the present invention.
  • Figure 9 is a cross-sectional view showing a fifth preferred embodiment of the liquid crystal substrate of the present invention.
  • the liquid crystal substrate 200 includes a substrate 210, a plurality of parallel data lines 220, a plurality of scan lines 230 perpendicular to the data lines, and a plurality of pixel units 240.
  • the pixel unit 240 is disposed in a rectangular area formed by the intersection of the data line and the scan line.
  • a thin film field effect transistor is formed at the intersection of the data line 220 and the scan line 230 (Thin Film Transistor (TFT) 250, the pixel unit 240 is electrically connected to the thin film field effect transistor 250 through a contact hole 251.
  • the pixel unit 240 includes a transparent electrode 241 and a plurality of grooves 242.
  • the present invention is only described by taking the shape of the pixel unit 240 as an example. In a specific embodiment, the shape of the pixel unit 240 may be determined according to actual conditions.
  • FIG. 3 is a cross-sectional view showing a first preferred embodiment of the liquid crystal substrate of the present invention, which is a cross-sectional view of the first preferred embodiment of the liquid crystal substrate of the present invention taken along line BB of FIG. schematic diagram.
  • the liquid crystal substrate 300 includes a substrate 310 on which a first insulating layer 320 is deposited, a first insulating layer 320 is spaced apart from the data line 330, and a second insulating layer 340 covers the first insulating layer 320.
  • the data line 330, the second insulating layer 340 preferably has a thickness of 100 nm to 400 nm.
  • a first transparent electrode layer 350 is deposited on the second insulating layer 340 between the data lines 330, the first transparent electrode layer 350 has a second transparent electrode layer 360 thereon, and the second transparent electrode layer The material of 360 is different from the first transparent electrode layer 350.
  • the second transparent electrode layer 360 is partially removed to form a plurality of slits 370, and the width of the slits 370 is preferably from 0.5 micrometers to 7.5 micrometers.
  • FIG. 3 and FIG. 4 are flowcharts of a method for fabricating a first preferred embodiment of a liquid crystal substrate according to the present invention.
  • the manufacturing method includes:
  • Step S301 sequentially forming a first insulating layer 320, a data line 330 and a second insulating layer 340 on the substrate 310;
  • the step 301 is specifically:
  • Step 3011 A scan line is formed on the surface of the substrate 310 by metal sputtering, and a scan line is obtained on the surface of the substrate by exposure, development, etching, and the like;
  • Step 3012 depositing a first insulating layer 320 on the scan line, which may be chemical vapor deposition or the like;
  • Step 3013 forming an amorphous silicon layer and a doped amorphous silicon layer by chemical vapor deposition or the like on the first insulating layer 320.
  • the doped amorphous silicon may be an electron donor such as phosphine or an electron such as borane.
  • the amorphous silicon layer is preferably 100 nm to 250 nm, and the amorphous silicon layer is exposed, developed, and etched to form an amorphous silicon portion of the thin film field effect transistor;
  • Step 3014 deposit a data line layer on the amorphous silicon portion by metal sputtering.
  • the data line layer is formed into a data line 330 by exposure, development, etching, etc., and the data line 330 is crossed with the scan line.
  • the portion of the data line layer located at the intersection of the data line 330 and the scan line is etched and disconnected to form a source (not shown) and a drain (not shown), the source and the data
  • the wire is connected, and the doped amorphous silicon layer under the broken portion is also etched and broken.
  • Step 3015 deposit a second insulating layer 340 on the data line 330, which may be chemical vapor deposition or the like.
  • Step 302 fabricating the first transparent electrode layer 350
  • the step 302 is specifically as follows:
  • Step 3021 depositing a first transparent electrode layer 350 on the second insulating layer 340 under conditions of more than 100 degrees Celsius.
  • the material of the first transparent electrode layer 350 may be indium tin oxide, indium zinc oxide, indium tin zinc oxide. , aluminum-doped zinc oxide or the like, thereby forming a first transparent electrode layer 350 in a polycrystalline state on the second insulating layer 340;
  • Step 3022 forming a contact hole on the second insulating layer 340 by a process such as exposure, development, etching, etc., and etching the first transparent electrode layer 350 at a portion other than the region where the scan line and the data line 330 intersect, in order to achieve Forming a contact hole and etching the first transparent electrode layer 350 and not completely destroying the scan line and the second insulating layer 340 over the data line 330, using a suitable transmittance at a corresponding position of the contact hole and the first transparent electrode layer 350 Grayscale mask (gray Mask).
  • a process such as exposure, development, etching, etc.
  • Step S303 forming a second transparent electrode layer 360
  • the step S303 is specifically:
  • Step S3031 depositing a second transparent electrode layer 360 in an amorphous state on the upper side of the first transparent electrode layer 350 by sputtering, the material of the second transparent electrode layer 360 may be indium tin oxide. Indium zinc oxide, indium tin zinc oxide, aluminum-doped zinc oxide, or the like, and the material of the second transparent electrode layer 360 is different from the first transparent electrode layer 350; the second transparent electrode layer 360 passes through the contact hole and the drain Extremely connected.
  • Step S3031 forming a slit 370 on the second transparent electrode layer 360 by using a process such as exposure, development, etching, etc., and etching the portion of the second transparent electrode layer 360 outside the region where the scan line and the data line 330 intersect, in this step.
  • the etching solution used in the present invention is a weak acid such as oxalic acid or oxalic acid, and the etching solution can only etch the second transparent electrode layer 360 in an amorphous state, and cannot etch the first transparent electrode layer in a polycrystalline state. 350.
  • the liquid crystal substrate 300 may also be annealed at a certain temperature, for example, 200-250 degrees Celsius, so that the second transparent electrode layer 360 is non- The crystalline state transitions to a polycrystalline state.
  • the liquid crystal substrate 300 is provided with a second transparent electrode layer 350 under the second transparent electrode layer 360 and the slit 370, and the electric field intensity of the slit 370 can be increased when a voltage is applied.
  • FIG. 5 is a cross-sectional view showing a second preferred embodiment of the liquid crystal substrate of the present invention, which is a cross-sectional view of the second preferred embodiment of the liquid crystal substrate of the present invention taken along line B-B of FIG.
  • the difference between the present embodiment and the first preferred embodiment is that in the embodiment, the materials and deposition conditions of the first transparent electrode layer 450 and the second transparent electrode layer 460 are the same, thereby forming a transparent electrode layer 480.
  • the transparent electrode layer is partially etched to form a slit 470.
  • the liquid crystal substrate 400 of the present embodiment is different from the method of fabricating the liquid crystal substrate 300 of the first embodiment in that:
  • Step S402 forming a contact hole in the second insulating layer 440;
  • Step S403 The transparent electrode layer 480 is formed.
  • the transparent electrode layer 480 is deposited on the second insulating layer 440, and the transparent electrode layer 480 is etched by exposure, development, etching, and the like.
  • the slit 470 is etched and the transparent electrode layer 480 is located at a portion other than the region where the scanning line and the data line 430 intersect.
  • the liquid crystal substrate 400 is transparent to the electrode layer 480 below the slit 470, and the electric field strength of the slit 470 can be increased when a voltage is applied.
  • FIG. 6 is a cross-sectional view showing a third preferred embodiment of the liquid crystal substrate of the present invention, which is a cross-sectional view of the liquid crystal substrate according to the third preferred embodiment of the present invention taken along line B-B of FIG. 2 .
  • the difference between the present embodiment and the first preferred embodiment is that: in the embodiment, a second insulating layer 590 is further deposited on the second insulating layer 540 and the first transparent electrode layer 550, and the second transparent electrode layer is further disposed. 560 and the slit 570 are located above the third insulating layer 590.
  • the materials and deposition conditions of the first transparent electrode layer 550 and the second transparent electrode layer 560 may be the same or different.
  • FIG. 6 and FIG. 7 are flowcharts of a method for fabricating the liquid crystal substrate 500 of the present embodiment
  • the manufacturing method of the present embodiment is different from the method for fabricating the liquid crystal substrate 300 of the first preferred embodiment in that:
  • Step 502 forming a first transparent electrode layer 540 and a third insulating layer 590;
  • This step is specifically as follows:
  • Step S5021 depositing a first transparent electrode layer 550 on the second insulating layer 540, and removing the first transparent electrode layer 550 outside the region surrounded by the scan line and the data line 530 by exposure, development, etching, or the like. And retaining a portion of the first transparent electrode layer 550 above the drain (not shown);
  • Step S5022 depositing a third insulating layer 590 on the second insulating layer 540 and the first transparent electrode layer 550, and forming a contact hole through a process of exposure, development, etching, etc., the contact hole penetrating through the second insulating layer 540, a first transparent electrode layer 550 and a third insulating layer 590;
  • Step 503 forming a second transparent electrode layer 560
  • the step 503 is specifically:
  • Step 5031 depositing a second transparent electrode layer 560 on the third insulating layer 590, the material and deposition conditions of the second transparent electrode layer 560 may be the same as or different from the material and deposition conditions of the first transparent electrode layer 550;
  • the second transparent electrode layer 560 is connected to the drain and the first transparent electrode layer 550 through the contact hole;
  • Step 5032 Form the slit 570 by a process such as exposure, development, etching, etc., and etch the portion of the second transparent electrode layer 560 outside the region where the scanning line and the data line 530 intersect.
  • the liquid crystal substrate 500 is provided with a second transparent electrode layer 550 under the second transparent electrode layer 560 and the slit 570, and the electric field intensity of the slit 570 can be increased when a voltage is applied.
  • FIG. 8 is a cross-sectional view showing a fourth preferred embodiment of the liquid crystal substrate of the present invention, which is a cross-sectional view of the fourth preferred embodiment of the liquid crystal substrate of the present invention taken along line B-B of FIG. 2 .
  • the difference between this embodiment and the third preferred embodiment is that in the embodiment, the third insulating layer 690 is disposed only between the first transparent electrode layer 650 and the second transparent electrode layer 660.
  • the method of fabricating the liquid crystal substrate 600 of the present embodiment is different from the method of fabricating the liquid crystal substrate 500 of the third embodiment in that:
  • Step 6022 depositing a third insulating layer 690 on the second insulating layer 640 and the first transparent electrode layer 650, and forming a contact hole through a process of exposure, development, etching, etc., the contact hole penetrating through the second insulating layer 640,
  • the first transparent electrode layer 650 and the third insulating layer 690 are etched and the third insulating layer 690 is etched except for the upper portion of the first transparent electrode layer 650.
  • FIG. 9 is a cross-sectional view showing a fifth preferred embodiment of the liquid crystal substrate of the present invention, which is a cross-sectional view of the fifth preferred embodiment of the liquid crystal substrate of the present invention taken along line B-B of FIG.
  • the second insulating layer 740 is formed with a plurality of grooves, and the transparent electrode layer 750 is disposed in the groove and the second insulation.
  • the slit 770 is located above the groove.
  • the manufacturing method of the liquid crystal substrate 700 of the present embodiment is different from the manufacturing method of the liquid crystal substrate 300 of the first preferred embodiment in that:
  • Step 702 fabricating a second insulating layer 740
  • the step is specifically: forming, by the processes of exposure, development, etching, etc., the second insulating layer 740 to form a contact hole and a plurality of grooves;
  • Step 703 forming a transparent electrode layer 780
  • the step is specifically: depositing a transparent electrode layer 780, forming a slit 770 over the groove by a process such as exposure, development, etching, etc., and etching the portion of the second transparent electrode layer 760 outside the region formed by the intersection of the scan line and the data line 730 .
  • the groove penetrates the second insulating layer 740.
  • the groove may also have its depth according to actual conditions.
  • the liquid crystal substrate 700 has a transparent electrode layer 780 under the slit 770, and when a voltage is applied, the electric field intensity of the slit 770 can be increased.
  • the liquid crystal substrate has only TFTs, data lines, and scan lines.
  • the liquid crystal substrate may have a color filter layer, that is, the liquid crystal substrate is COA (Color-filter On Array) substrate.
  • the electric field intensity at the slit can be increased.
  • the present invention also provides a liquid crystal panel comprising any one of the above liquid crystal substrates, a second substrate, and liquid crystal molecules disposed between the liquid crystal substrate and the second substrate, the structure of the liquid crystal substrate and the structure having the liquid crystal substrate The same, will not be described here.
  • the transparent electrode layer is provided under the slit of the transparent electrode layer to increase the electric field intensity at the slit, thereby improving the light transmittance of the liquid crystal display panel.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Mathematical Physics (AREA)

Abstract

一种液晶基板（200）及其制作方法，所述液晶基板（200）包括基板（210），形成在所述基板（210）上的透明电极层，在所述透明电极层上形成缝隙（370），并使所述缝隙（370）下方具有透明电极层。该液晶基板（200）及其制作方法，使所述缝隙（370）下方还设置有透明电极层，从而在施加电压时，增强所述缝隙（370）处的电场强度，进而提高液晶面板的透过率。

Description

液晶基板及其制作方法 技术领域
本发明涉及液晶显示面板制作领域，特别是涉及一种垂直配向显示模式的液晶显示面板及其制作方法。
 背景技术
液晶显示面板由于其重量低、体积小以及能耗低等优点，逐渐成为主流的平板显示设备。
垂直配向（VA：Vertical Alignment）显示模式技术由于其良好的广视角显示效果，已广泛应用在液晶显示领域中。其中垂直配向显示模式包括多畴垂直配向显示模式（MVA：Multi-domain Vertical Alignment）、图形化垂直配向显示模式（PVA：Patterned Vertical Alignment）、高分子稳定垂直配向显示模式（PSVA：Polymer Sustained Vertical Alignment）等。
高分子稳定垂直配向显示模式（PSVA：Polymer Sustained Vertical Alignment）的垂直配向显示模式。如图1A、图1B和图1C所示，图1A为现有的高分子稳定垂直配向显示模式的液晶显示面板的第一透明电极层的结构示意图；图1B为图1A的高分子稳定垂直配向显示模式的液晶显示面板不通电时的A-A’截面的结构示意图；图1C为图1A的高分子稳定垂直配向显示模式的液晶显示面板通电时的A-A’截面的结构示意图。所述这种显示模式的液晶显示面板100包括CF（Color Filter，彩色滤光层）基板110、TFT（Thin Film Transistor，薄膜场效应晶体管）基板120以及液晶分子130，在CF基板110和TFT基板120的内侧设置有透明电极层140，所述TFT基板120上的透明电极层141形成有狭缝142。所述液晶分子130中添加了反应单体，通过施加电压和紫外光照射，使这些反应单体发生反应生成高分子链150，从而使液晶分子的倾斜预定角度，进而加快了液晶分子130的响应速度。
但是由于TFT基板120的透明电极层140具有狭缝142，该狭缝142处的电场驱动力较弱，导致液晶显示面板100在狭缝142处的透光率较差。要提高该高分子稳定垂直配向显示模式的液晶显示面板100的透光率，需要降低狭缝142的宽度，以克服狭缝142处的电场驱动力弱的缺陷；但是这受制约于曝光机的能力，狭缝142无法达到预定的宽度，使得狭缝142处的电场强度不足，从而造成液晶显示面板100的透过率不高。
故，有必要提供一种液晶显示面板及其制作方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种通过增加透明电极层的缝隙处的电场强度的液晶基板及其制作方法，以解决现有的高分子稳定垂直配向显示模式的缝隙处的电场强度不足而造成液晶显示面板透光率较低的技术问题。
 技术解决方案
本发明提供的技术方案如下：
本发明涉及一种液晶基板，其具有透明电极层，所述透明电极层形成有缝隙，所述缝隙的下方还设置有透明电极层。
在本发明所述的液晶基板中，所述透明电极层包括第一透明电极层及第二透明电极层，所述第二透明电极层形成所述缝隙，所述第一透明电极层设置在所述缝隙下方。
在本发明所述的液晶基板中，所述第一透明电极层与所述第二透明电极层之间具有第三绝缘层。
在本发明所述的液晶基板中，所述液晶基板还包括第二绝缘层，所述第一透明电极层设置在所述第二绝缘层上，所述第三绝缘层覆盖所述第二绝缘层及第一透明电极层。
在本发明所述的液晶基板中，所述液晶基板还包括第二绝缘层，所述第一透明电极层设置在所述第二绝缘层上，所述第三绝缘层仅覆盖所述第一透明电极层。
在本发明所述的液晶基板中，所述第二透明电极层与第一透明电极层的材质相同。
在本发明所述的液晶基板中，所述第二透明电极层设置在第一透明电极层的表面上。
在本发明所述的液晶基板中，所述第二透明电极层与第一透明电极层的材质不同。
在本发明所述的液晶基板中，所述液晶基板包括第二绝缘层，所述第二绝缘层形成有若干凹槽，所述透明电极层，所述透明电极层设置在所述凹槽内及第二绝缘层上，所述缝隙设置在所述凹槽的上方。
在本发明所述的液晶基板中，所述凹槽贯穿所述第二绝缘层。
在本发明所述的液晶基板中，所述液晶基板还包括若干数据线及漏极，所述透明电极层通过所述接触孔与所述漏极连接。
本发明还涉及一种液基板的制作方法，其中包括步骤：A、在基板上形成透明电极层；B、在所述透明电极层上形成缝隙，并使所述缝隙下方具有透明电极层。
在本发明所述的液晶基板的制作方法中，所述步骤A具体为：在基板上形成第一透明电极层及第二透明电极层；所述步骤B具体为：在所述第二透明电极层上形成缝隙。
在本发明所述的液晶基板的制作方法中，所述步骤A中，在大于100摄氏度的条件下形成呈多晶状态的所述第一透明电极层。
在本发明所述的液晶基板的制作方法中，在所述步骤B中在室温下形成呈非晶状态的第二透明电极层。
在本发明所述的液晶基板的制作方法中，在所述步骤B之后还包括步骤：对所述液晶基板进行退火处理将所述非晶状态的第二透明电极层转变为多晶态。
在本发明所述的液晶基板的制作方法中，在所述步骤B中，通过刻蚀液刻蚀第二透明电极层形成所述缝隙，所述刻蚀液为弱酸。
在本发明所述的液晶基板的制作方法中，所述步骤A具体为：在基板上形成第一透明电极层、第三绝缘层及第二透明电极层。
在本发明所述的液晶基板的制作方法中，所述第三绝缘层仅设置在所述第一透明电极层与所述第二透明电极层之间。
在本发明所述的液晶基板的制作方法中，所述步骤A具体为：在基板上形成第二绝缘层，在所述第二绝缘层上形成凹槽，在所述第二绝缘层上及凹槽内形成所述透明电极层。
 有益效果
本发明的液晶基板及其制作方法，通过在透明电极层的缝隙下方设置透明电极层，以增加缝隙处的电场强度，从而增加提高了液晶显示面板的透光率。
附图说明
图1A为高分子稳定垂直配向显示模式的液晶显示面板的第一透明电极层的结构示意图；
图1B为图1A的高分子稳定垂直配向显示模式的液晶显示面板不通电时的A-A截面的结构示意图；
图1C为图1A的高分子稳定垂直配向显示模式的液晶显示面板通电时的A-A截面的结构示意图；
图2为本发明的液晶基板的平面结构示意图；
图3为本发明的液晶基板的第一优选实施例的剖面示意图；
图4为图3所示的液晶基板的制作方法流程图；
图5为本发明的液晶基板的第二优选实施例的剖面示意图；
图6为本发明的液晶基板的第三优选实施例的剖面示意图；
图7为图6所示的液晶基板的制作方法示意图；
图8为本发明的液晶基板的第四优选实施例的剖面示意图；
图9为本发明的液晶基板的第五优选实施例的剖面示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
请参阅图2,其为本发明液晶基板的部分俯视图，所述液晶基板200包括基板210、若干条平行设置的数据线220、若干条与数据线垂直的扫描线230及若干个像素单元240，所述像素单元240设置在所述数据线与扫描线交叉形成的矩形区域内。所述数据线220与扫描线230的交叉处形成有薄膜场效应晶体管（Thin Film Transistor，TFT）250，所述像素单元240通过一接触孔251与该薄膜场效应晶体管250电性连接。所述像素单元240包括透明电极241及若干凹槽242。当然，本发明仅以上述像素单元240的形状为例说明，在具体实施例中，所述像素单元240的形状可根据实际情况而定。
请参阅图2及图3，图3为本发明的液晶基板的第一优选实施例的剖面示意图，其为本发明的液晶基板的第一优选实施例沿图2所示的B-B线位置的剖面示意图。所述液晶基板300包括基板310，所述基板310上沉积有第一绝缘层320，第一绝缘层320上间隔设置有数据线330，一第二绝缘层340覆盖所述第一绝缘层320及数据线330，所述第二绝缘层340的厚度优选为100纳米至400纳米。位于所述数据线330之间的第二绝缘层340上具沉积有第一透明电极层350，所述第一透明电极层350上具有第二透明电极层360，且所述第二透明电极层360的材料与第一透明电极层350不同。所述第二透明电极层360部分被除去形成若干缝隙370，该缝隙370的宽度优选为0.5微米至7.5微米。
请一并参阅图3及图4，其为本发明液晶基板的第一优选实施例的制作方法流程图，该制作方法包括：
步骤S301：依次在基板310上形成第一绝缘层320、数据线330及第二绝缘层340；
所述步骤301具体为：
步骤3011：在基板310表面通过金属溅镀的方式制作扫描线，通过曝光、显影、刻蚀等工序在基板表面得到扫描线；
步骤3012：在扫描线上沉积第一绝缘层320，该沉积方式可以为化学气相沉积等；
步骤3013：在第一绝缘层320上通过化学气相沉积等方式制作非晶硅层和掺杂非晶硅层，该掺杂非晶硅呈可以是磷烷等电子给体或是硼烷等电子受体，所述非晶硅成的厚度优选为100纳米至250纳米，所述非晶硅层经过曝光、显影、刻蚀形成薄膜场效应晶体管的非晶硅部分；
步骤3014：在所述非晶硅部分上通过金属溅镀的方式沉积数据线层，该数据线层经过曝光、显影、刻蚀等工序形成数据线330，所述数据线330与扫描线交叉设置,并且所述数据线层位于数据线330与扫描线交叉处的部分被刻蚀并断开，形成源极（图未示）和漏极（图未示），所述源极与所述数据线连接,该断开部分下方的掺杂非晶硅层也被刻蚀并断开。
步骤3015：在所述数据线330沉积第二绝缘层340，该沉积方式可以为化学气相沉积等。
步骤302：制作所述第一透明电极层350；
所述步骤302具体为：
步骤3021：在大于100摄氏度的条件下，所述第二绝缘层340上沉积第一透明电极层350，该第一透明电极层350的材料可以是氧化铟锡、氧化铟锌、氧化铟锡锌、铝掺杂氧化锌等，从而在第二绝缘层340上形成呈多晶状态的第一透明电极层350；
步骤3022：通过曝光、显影、刻蚀等工序在第二绝缘层340上形成接触孔，并且刻蚀第一透明电极层350位于扫描线和数据线330交叉形成的区域以外的部分，为了达到同时形成接触孔和刻蚀第一透明电极层350且不完全破坏扫描线以及数据线330上方的第二绝缘层340，在接触孔和第一透明电极层350的对应位置上使用合适透过率的灰阶光罩（gray mask）。
步骤S303：制作第二透明电极层360，
所述步骤S303具体为：
步骤S3031：在室温下，在第一透明电极层350的上侧通过溅镀的方式沉积得到呈非晶状态的第二透明电极层360，该第二透明电极层360的材料可以为氧化铟锡、氧化铟锌、氧化铟锡锌、铝掺杂氧化锌等，且所述第二透明电极层360的材料与第一透明电极层350不同；所述第二透明电极层360通过接触孔与漏极连接。
步骤S3031：使用曝光、显影、刻蚀等工艺在第二透明电极层360上形成缝隙370并刻蚀第二透明电极层360位于扫描线和数据线330交叉形成的区域以外的部分，在本步骤中采用的刻蚀液为弱酸，如草酸、乙二酸等，刻蚀液只能刻蚀呈非晶状态的第二透明电极层360，而不能刻蚀呈多晶状态的第一透明电极层350。
在本实施例中，在第二透明电极层360制作完成后，所述液晶基板300也可以在一定温度下进行退火处理，例如200-250摄氏度，从而使所述第二透明电极层360由非晶状态转变为多晶态。
在本实施例中，液晶基板300在第二透明电极层360和缝隙370的下方设置第二透明电极层350，在施加电压时，可增加缝隙370的电场强度。
请参阅图5，其为本发明液晶基板的第二优选实施例的剖面示意图，其为本发明的液晶基板的第二优选实施例沿图2所示的B-B线位置的剖面示意图。本实施例与第一优选实施例的不同在于：在本实施例中，所述第一透明电极层450与第二透明电极层460的材质和沉积条件均相同，从而形成一透明电极层480，该透明电极层经过部分刻蚀形成缝隙470。
本实施例的液晶基板400与第一实施例的液晶基板300的制作方法不同在于：
步骤S402：在第二绝缘层440形成接触孔；
步骤S403：制作透明电极层480，本步骤具体为：在第二绝缘层440上沉积透明电极层480，并通过曝光、显影、刻蚀等工序，使透明电极层480的部分被刻蚀而形成缝隙470并刻蚀透明电极层480位于扫描线和数据线430交叉形成的区域以外的部分。
在本实施例中，液晶基板400在缝隙470的下方透明电极层480，在施加电压时，可增加缝隙470的电场强度。
请参阅图6，其为本发明液晶基板的第三优选实施例的剖面示意图，其为本发明的液晶基板的第三优选实施例沿图2所示的B-B线位置的剖面示意图。本实施例与第一优选实施例的不同在于：在本实施例中，所述第二绝缘层540及第一透明电极层550上还沉积有一第三绝缘层590，所述第二透明电极层560及缝隙570位于第三绝缘层590的上方，所述第一透明电极层550与所述第二透明电极层560的材质和沉积条件可以相同也可以不同。
请一并参阅图6及图7，其为本实施例的液晶基板500的制作方法的流程图，本实施例的制作方法与第一优选实施例的液晶基板300的制作方法不同在于：
步骤502：形成第一透明电极层540及第三绝缘层590；
本步骤具体为：
步骤S5021：在所述第二绝缘层540上沉积第一透明电极层550，并通过曝光、显影、刻蚀等工序除去第一透明电极层550位于扫描线与数据线530交叉围成的区域外的部分并保留第一透明电极层550位于漏极（图未示）上方的部分；
步骤S5022：在所述第二绝缘层540及第一透明电极层550上沉积第三绝缘层590，并通过曝光、显影、刻蚀等工序形成接触孔，该接触孔贯穿第二绝缘层540、第一透明电极层550及第三绝缘层590；
步骤503：形成第二透明电极层560；
所述步骤503具体为：
步骤5031：在第三绝缘层590上沉积第二透明电极层560，该第二透明电极层560的材质和沉积条件可以与第一透明电极层550的材质和沉积条件相同，也可以不同；所述第二透明电极层560通过接触孔与漏极及第一透明电极层550连接；
步骤5032：通过曝光、显影、刻蚀等工序形成缝隙570并刻蚀第二透明电极层560位于扫描线和数据线530交叉形成的区域以外的部分。
在本实施例中，液晶基板500在第二透明电极层560和缝隙570的下方设置第二透明电极层550，在施加电压时，可增加缝隙570的电场强度。
请参阅图8，其为本发明液晶基板的第四优选实施例的剖面示意图，其为本发明的液晶基板的第四优选实施例沿图2所示的B-B线位置的剖面示意图。本实施例与第三优选实施例的不同在于：在本实施例中，所述第三绝缘层690仅设置在所述第一透明电极层650与第二透明电极层660之间。
本实施例的液晶基板600的制作方法与第三实施例的液晶基板500的制作方法不同在于：
步骤6022：在所述第二绝缘层640及第一透明电极层650上沉积第三绝缘层690，并通过曝光、显影、刻蚀等工序形成接触孔，该接触孔贯穿第二绝缘层640、第一透明电极层650及第三绝缘层690，并刻蚀第三绝缘层690除第一透明电极层650上方以外的部分。
请参阅图9，其为本发明液晶基板的第五优选实施例的剖面示意图，其为本发明的液晶基板的第五优选实施例沿图2所示的B-B线位置的剖面示意图。本实施例与第一优选实施例的不同在于：在本实施例中，所述第二绝缘层740形成有多条凹槽，所述透明电极层750设置在所述凹槽中及第二绝缘层740的上方，所述缝隙770位于凹槽的上方。
本实施例的液晶基板700的制作方法与第一优选实施例的液晶基板300的制作方法不同在于：
步骤702：制作第二绝缘层740；
本步骤具体为：通过曝光、显影、刻蚀等工序，使第二绝缘层740形成接触孔和若干条凹槽；
步骤703：制作透明电极层780；
本步骤具体为：沉积透明电极层780，通过曝光、显影、刻蚀等工序在凹槽上方形成缝隙770、刻蚀第二透明电极层760位于扫描线和数据线730交叉形成的区域以外的部分。
本实施例中，所述凹槽贯穿第二绝缘层740，当然在其他实施例中，所述凹槽也可以根据实际情况设置其深度。
在本实施例中，液晶基板700在缝隙770的下方具有透明电极层780，在施加电压时，可增加缝隙770的电场强度。
上述第一至第五优选实施例的中，液晶基板仅具有TFT、数据线及扫描线，当然在其他实施例中，所述液晶基板还可有具有彩色滤光层，即所述液晶基板为COA（Color-filter On Array）基板。
在本发明的实施例通过在在缝隙的下方透明电极层，在施加电压时，可增加缝隙处的电场强度。
本发明还提供一种液晶面板，该液晶面板包括上述任意一种液晶基板、第二基板及设置液晶基板与第二基板之间的液晶分子，所述液晶基板的结构与具有上述液晶基板的结构相同，在此不作赘述。
本发明的液晶基板及其制作方法，通过在透明电极层的缝隙下方设置透明电极层，以增加缝隙处的电场强度的，从而提高了的液晶显示面板的透光率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (20)

  1. 一种液晶基板，其特征在于，所述液晶基板具有透明电极层，所述透明电极层形成有缝隙，所述缝隙的下方还设置有透明电极层。
  2. 根据权利要求1所述的液晶基板，其特征在于，所述透明电极层包括第一透明电极层及第二透明电极层，所述第二透明电极层形成所述缝隙，所述第一透明电极层设置在所述缝隙下方。
  3. 根据权利要求2所述的液晶基板，其特征在于，所述第一透明电极层与所述第二透明电极层之间具有第三绝缘层。
  4. 根据权利要求3所述的液晶基板，其特征在于，所述液晶基板还包括第二绝缘层，所述第一透明电极层设置在所述第二绝缘层上，所述第三绝缘层覆盖所述第二绝缘层及第一透明电极层。
  5. 根据权利要求3所述的液晶基板，其特征在于，所述液晶基板还包括第二绝缘层，所述第一透明电极层设置在所述第二绝缘层上，所述第三绝缘层仅覆盖所述第一透明电极层。
  6. 根据权利要求3所述的液晶基板，其特征在于，所述第二透明电极层与第一透明电极层的材质相同。
  7. 根据权利要求2所述的液晶基板，其特征在于，所述第二透明电极层设置在第一透明电极层的表面上。
  8. 根据权利要求2所述的液晶基板，其特征在于，所述第二透明电极层与第一透明电极层的材质不同。
  9. 根据权利要求1所述的液晶基板，其特征在于，所述液晶基板包括第二绝缘层，所述第二绝缘层形成有若干凹槽，所述透明电极层，所述透明电极层设置在所述凹槽内及所述第二绝缘层上，所述缝隙设置在所述凹槽的上方。
  10. 根据权利要求9所述的液晶基板，其特征在于，所述凹槽贯穿所述第二绝缘层。
  11. 根据权利要求1的液晶基板，其特征在于，所述液晶基板还包括若干数据线及漏极，所述透明电极层通过接触孔与所述漏极连接。
  12. 一种液晶基板的制作方法，其特征在于，包括步骤：
    A、在基板上形成透明电极层；
    B、在所述透明电极层上形成缝隙，并使所述缝隙下方具有透明电极层。
  13. 根据权利要求12所述的液晶基板的制作方法，其特征在于，
    所述步骤A具体为：在基板上形成第一透明电极层及第二透明电极层；
    所述步骤B具体为：在所述第二透明电极层上形成缝隙。
  14. 根据权利要求13所述的液晶基板的制作方法，其特征在于，所述步骤A中，在大于100摄氏度的条件下形成呈多晶状态的所述第一透明电极层。
  15. 根据权利要求14所述的液晶基板的制作方法，其特征在于，在所述步骤B中在室温下形成呈非晶状态的第二透明电极层。
  16. 根据权利要求15所述的液晶基板的制作方法，其特征在于，在步骤B之后还包括步骤：对所述液晶基板进行退火处理将所述非晶状态的第二透明电极层转变为多晶态。
  17. 根据权利要求16所述的液晶基板的制作方法，其特征在于，在所述步骤B中，通过刻蚀液刻蚀第二透明电极层形成所述缝隙，所述刻蚀液为弱酸。
  18. 根据权利要求13所述的液晶基板的制作方法，其特征在于，所述步骤A具体为：在基板上形成第一透明电极层、第三绝缘层及第二透明电极层。
  19. 根据权利要求18所述的液晶基板的制作方法，其特征在于，所述第三绝缘层仅设置在所述第一透明电极层与所述第二透明电极层之间。
  20. 根据权利要求12所述的液晶基板的制作方法，其特征在于，所述步骤A具体为：在基板上形成第二绝缘层，在所述第二绝缘层上形成凹槽，在所述第二绝缘层上及所述凹槽内形成所述透明电极层。
PCT/CN2011/083528 2011-12-05 2011-12-06 液晶基板及其制作方法 WO2013082755A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/380,895 US9366905B2 (en) 2011-12-05 2011-12-06 Liquid crystal panel and manufacturing method for the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110398043.6A CN102566158B (zh) 2011-12-05 2011-12-05 液晶基板及其制作方法
CN201110398043.6 2011-12-05

Publications (1)

Publication Number Publication Date
WO2013082755A1 true WO2013082755A1 (zh) 2013-06-13

Family

ID=46411937

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/083528 WO2013082755A1 (zh) 2011-12-05 2011-12-06 液晶基板及其制作方法

Country Status (2)

Country Link
CN (1) CN102566158B (zh)
WO (1) WO2013082755A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103472627B (zh) * 2013-09-24 2017-01-04 深圳市华星光电技术有限公司 一种psva液晶面板制造方法和psva液晶面板
US9535291B2 (en) 2013-09-24 2017-01-03 Shenzhen China Star Optoelectronics Technology Co., Ltd PSVA LCD panel and method for manufacturing the PSVA LCD panel
CN104950533A (zh) * 2014-03-25 2015-09-30 深圳莱宝高科技股份有限公司 一种显示面板
CN104950532A (zh) * 2014-03-25 2015-09-30 深圳莱宝高科技股份有限公司 显示面板
CN110398863A (zh) * 2019-07-22 2019-11-01 深圳市华星光电半导体显示技术有限公司 显示面板
CN115826303A (zh) * 2022-12-07 2023-03-21 北海惠科光电技术有限公司 像素单元、阵列基板及显示面板
CN115793328A (zh) * 2022-12-07 2023-03-14 北海惠科光电技术有限公司 像素电极结构、阵列基板及显示面板

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001174821A (ja) * 1999-12-20 2001-06-29 Nec Corp アクティブマトリクス型液晶表示装置
JP2003073860A (ja) * 2001-08-30 2003-03-12 Ulvac Japan Ltd 積層型の透明導電膜、及びその透明導電膜のパターニング方法
CN1638547A (zh) * 2003-12-26 2005-07-13 三洋电机株式会社 显示装置的制造方法
JP2005316330A (ja) * 2004-04-30 2005-11-10 Toshiba Matsushita Display Technology Co Ltd 液晶表示装置
CN1967361A (zh) * 2006-11-02 2007-05-23 上海广电光电子有限公司 垂直配向模式的液晶显示装置及其阵列基板的制造方法
CN101093330A (zh) * 2006-05-29 2007-12-26 Nec液晶技术株式会社 板内切换有源矩阵液晶显示装置
CN101620346A (zh) * 2008-07-02 2010-01-06 爱普生映像元器件有限公司 液晶显示面板
WO2011061982A1 (ja) * 2009-11-18 2011-05-26 シャープ株式会社 透明電極基板、前駆透明電極基板、及び透明電極基板の製造方法
JP2011221400A (ja) * 2010-04-13 2011-11-04 Sony Corp 液晶表示装置、液晶表示装置の製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001174821A (ja) * 1999-12-20 2001-06-29 Nec Corp アクティブマトリクス型液晶表示装置
JP2003073860A (ja) * 2001-08-30 2003-03-12 Ulvac Japan Ltd 積層型の透明導電膜、及びその透明導電膜のパターニング方法
CN1638547A (zh) * 2003-12-26 2005-07-13 三洋电机株式会社 显示装置的制造方法
JP2005316330A (ja) * 2004-04-30 2005-11-10 Toshiba Matsushita Display Technology Co Ltd 液晶表示装置
CN101093330A (zh) * 2006-05-29 2007-12-26 Nec液晶技术株式会社 板内切换有源矩阵液晶显示装置
CN1967361A (zh) * 2006-11-02 2007-05-23 上海广电光电子有限公司 垂直配向模式的液晶显示装置及其阵列基板的制造方法
CN101620346A (zh) * 2008-07-02 2010-01-06 爱普生映像元器件有限公司 液晶显示面板
WO2011061982A1 (ja) * 2009-11-18 2011-05-26 シャープ株式会社 透明電極基板、前駆透明電極基板、及び透明電極基板の製造方法
JP2011221400A (ja) * 2010-04-13 2011-11-04 Sony Corp 液晶表示装置、液晶表示装置の製造方法

Also Published As

Publication number Publication date
CN102566158B (zh) 2014-12-17
CN102566158A (zh) 2012-07-11

Similar Documents

Publication Publication Date Title
WO2013082755A1 (zh) 液晶基板及其制作方法
WO2013116992A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
JP3238020B2 (ja) アクティブマトリクス表示装置の製造方法
WO2013116994A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2013116995A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2013063805A1 (zh) 液晶显示装置及其制造方法
CN103278979B (zh) 平面式液晶显示器的阵列基板及其制造方法
KR20090027920A (ko) 표시 기판 및 이를 구비한 표시 패널
WO2019047357A1 (zh) 一种oled显示面板及其制程
WO2015100801A1 (zh) 液晶面板及其制作方法
WO2013131384A1 (zh) 薄膜晶体管阵列基板及其制造方法和电子器件
WO2017008318A1 (zh) 一种阵列基板及其制作方法
CN105702687A (zh) Tft基板及其制作方法
WO2018032670A1 (zh) Tft基板的制作方法
KR20070072179A (ko) 액정표시장치의 제조방법
US7414691B2 (en) Liquid crystal display device with prevention of defective disconnection of drain/pixel electrodes by forming two conductive layers on top of entire pixel electrode and then removing a portion of both therefrom
WO2013139045A1 (zh) 薄膜晶体管阵列基板及其制作方法
WO2017020322A1 (zh) 一种ffs阵列基板及其制造方法和显示装置
CN106024705B (zh) Tft基板的制作方法
WO2017152450A1 (zh) Ffs模式的阵列基板及制作方法
WO2013166668A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2013159398A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2013116990A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2013159396A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2019100495A1 (zh) Ffs型薄膜晶体管阵列基板及其制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13380895

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11876948

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11876948

Country of ref document: EP

Kind code of ref document: A1