WO2017020322A1 - 一种ffs阵列基板及其制造方法和显示装置 - Google Patents

一种ffs阵列基板及其制造方法和显示装置 Download PDF

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WO2017020322A1
WO2017020322A1 PCT/CN2015/086334 CN2015086334W WO2017020322A1 WO 2017020322 A1 WO2017020322 A1 WO 2017020322A1 CN 2015086334 W CN2015086334 W CN 2015086334W WO 2017020322 A1 WO2017020322 A1 WO 2017020322A1
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array substrate
gate
common electrode
ito
layer
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PCT/CN2015/086334
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to US14/896,406 priority Critical patent/US9658501B2/en
Publication of WO2017020322A1 publication Critical patent/WO2017020322A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an FFS array substrate, a manufacturing method thereof, and a display device.
  • Fringe Field Switch (Fringe Field Switching (FFS) technology is a current liquid crystal display technology, which is a wide viewing angle technology developed by the liquid crystal industry to solve large-size, high-definition desktop displays and LCD TV applications.
  • the FFS liquid crystal panel has the advantages of fast response time, high light transmittance, wide viewing angle, etc., but since the FFS liquid crystal panel uses two layers of indium tin oxide (Indium) Tin Oxide (referred to as ITO) to make, its own production process is one or two mask processes than the average LCD panel.
  • ITO indium tin oxide
  • ITO indium Tin Oxide
  • the existing improved technology will pixel ITO is directly fabricated on the source and drain metal, thereby reducing the fabrication process of an insulating protective layer.
  • the semiconductor layer is directly in contact with the ITO etching solution, the active layer of the semiconductor layer is easily damaged by the ITO etching solution. In turn, the conductive properties of the semiconductor active layer are affected.
  • An object of the present invention is to provide a method for fabricating an FFS array substrate, which overcomes the damage of the semiconductor active layer by the pixel electrode ITO etching of the prior art without increasing the fabrication process.
  • the present invention further provides an FFS array substrate and a display device.
  • a method for manufacturing an FFS array substrate includes the following steps:
  • a common electrode structure is formed on the insulating protective layer corresponding to the pixel electrode ITO and the via structure.
  • the thickness of the gate and the common electrode line of the step 1 is 3000 to 5000 am.
  • the gate and common electrode lines of the step 1 are formed by depositing Al or Cu metal by physical sputtering.
  • the thickness of the gate insulating layer of the step 2 is 2000-5000 am.
  • the gate insulating layer of step 2 is formed by precipitation of SiNx by plasma enhanced chemical vapor deposition.
  • the pixel electrode ITO of the step 3 has a thickness of 300 to 1000 am.
  • the pixel electrode ITO of the step 3 is formed by physically sputtering an ITO material.
  • the semiconductor active layer of the step 4 has a thickness of 1300 to 2000 am.
  • the semiconductor active layer of the step 4 is formed by precipitating amorphous silicon or doped amorphous silicon material by plasma enhanced chemical vapor deposition.
  • the insulating protective layer has a thickness of 2000 to 5000 am.
  • the insulating protective layer is made of SiNx.
  • the common electrode has a thickness of 300 to 1000 am.
  • the material of the common electrode is ITO.
  • An FFS array substrate comprising:
  • a gate insulating layer formed on the substrate and covering the gate line, the gate and the common electrode line;
  • a pixel electrode ITO formed on the gate insulating layer between the gate electrode and the common electrode line;
  • a semiconductor active layer formed on the gate insulating layer corresponding to the gate, and a cross-sectional width of the semiconductor active layer is smaller than a cross-sectional width of the gate;
  • a source and a drain are formed on the gate insulating layer, and the source and the drain are respectively in contact with both ends of the semiconductor active layer to form a TFT channel, the drain and the pixel
  • the electrode ITO is partially overlapped and the drain is on the pixel electrode ITO;
  • a via structure formed on the gate insulating layer and the insulating protective layer above the common electrode line, and a cross-sectional width of the via structure is smaller than a cross-sectional width of the common electrode line;
  • the common electrode ITO is formed on the upper surface of the insulating protective layer and the via structure corresponding to the pixel electrode.
  • the gate and the common electrode line have a thickness of 3000 to 5000 am, and the gate insulating layer has a thickness of 2000 to 5000 am.
  • the pixel electrode ITO has a thickness of 300 to 1000 am, and the semiconductor active layer has a thickness of 1300 to 2000 am.
  • the insulating protective layer has a thickness of 2000 to 5000 am
  • the common electrode has a thickness of 300 to 1000 am.
  • the gate insulating layer and the insulating protective layer are made of SiNx, and the semiconductor active layer is made of amorphous silicon or doped amorphous silicon.
  • the material of the pixel electrode and the common electrode is ITO.
  • a display device comprising the above-described FFS array substrate.
  • the invention relates to a method for manufacturing an FFS array substrate.
  • the prior art pixel electrode ITO etching pair is overcome without increasing the fabrication process. Damage to the semiconductor active layer.
  • the pixel electrode ITO is under the drain, and the structure is simpler.
  • FIG. 1 is a flow chart showing a method of manufacturing an FFS array substrate of the present invention
  • FIG. 2 is a schematic structural view showing formation of a gate electrode and a common electrode line on a substrate of the present invention
  • FIG. 3 is a schematic structural view showing formation of a gate insulating layer and a pixel electrode ITO on a substrate of the present invention
  • FIG. 4 is a schematic structural view showing formation of a semiconductor active layer on a substrate of the present invention.
  • FIG. 5 is a schematic structural view showing formation of a source and a drain on a substrate of the present invention.
  • FIG. 6 is a schematic view showing an insulating protective layer and a via structure formed on a substrate of the present invention
  • FIG. 7 is a schematic view showing the complete structure of a common electrode on a substrate of the present invention.
  • FIG. 8 is a schematic structural view of a prior art FFS array substrate
  • FIG. 9 is a schematic structural view of a prior art FFS array substrate when a semiconductor active layer is formed
  • FIG. 10 is a schematic structural view of a prior art FFS array substrate when a source and a drain are formed;
  • FIG. 11 is a schematic structural view of a prior art FFS array substrate when a pixel electrode ITO is formed.
  • FIG. 1 is a flow chart showing a manufacturing method of an FFS array substrate according to the present invention
  • FIGS. 2 to 7 are manufacturing sequence diagrams of an FFS array substrate according to the present invention, as can be seen from FIG. 1 to FIG.
  • the method for manufacturing an FFS array substrate of the present invention comprises the following steps:
  • Step S101 depositing a metal or metal alloy such as Mo/Al/Cu having a film thickness of 3000 to 5000 am by physical sputtering on the substrate 1, and then forming a gate by coating, exposure, development, wet etching, and lift-off. 2 and the common electrode line 3, as shown in FIG.
  • Step S102 depositing a SiNx gate insulating layer 4 having a thickness of 2000-5000 am on the gate electrode 2 and the common electrode line 3 by plasma enhanced chemical vapor deposition, the gate insulating layer 4 covering the entire substrate.
  • Step S103 A transparent conductive material such as ITO of 300 to 1000 am is deposited by physical sputtering, and the pixel electrode structure 5 is formed by coating, exposure, development, wet etching, and lift-off, as shown in FIG.
  • FIG. 8 is a schematic structural view of a prior art FFS array substrate
  • FIGS. 9 to 11 are a part of a manufacturing process sequence diagram of the prior art FFS array substrate.
  • the FFS array substrate of the prior art does not directly form the pixel electrode ITO of the present invention on the gate insulating layer 4 as in the present invention. 5, but a semiconductor active layer 6 is formed on the gate insulating layer 4 corresponding to the gate 2, and then the source 7 and the drain 8 are formed, and then the pixel electrode ITO of the prior art is formed. 5.
  • the semiconductor active layer 6 directly contacts the etching liquid phase of the pixel electrode ITO 5, the semiconductor active layer 6 is exposed to the pixel electrode ITO.
  • the present step of the present invention is exactly the opposite. After the gate insulating layer 4 is completed, the pixel electrode ITO is directly formed on the gate insulating layer 4. 5, then the semiconductor active layer 6 and the source 7 and the drain 8 are formed, thus avoiding damage to the semiconductor active layer 6 by the etching solution of the pixel electrode ITO 5.
  • Step S104 depositing a layer of amorphous silicon and doped amorphous silicon having a film thickness of 1300 A to 2000 am on the gate insulating layer 4 on the gate 2 by plasma enhanced chemical vapor deposition, and then coating A semiconductor active layer 6 structure is formed by a method such as cloth, exposure, development, dry etching, and lift-off, and the cross-sectional width of the semiconductor active layer 6 is smaller than the cross-sectional width of the gate electrode 2, which is advantageous for the TFT channel to be in the gate.
  • a method such as cloth, exposure, development, dry etching, and lift-off
  • Step S105 depositing a metal or metal alloy such as Mo/Al/Cu having a film thickness of 3000 to 5000 am on the semiconductor active layer 6 and the gate insulating layer 4 by physical sputtering, and then coating and exposing a metal structure of the source 7 and the drain 8 by a method such as development, wet etching, channel n+ etching, and lift-off, and the drain 8 and the pixel electrode ITO A portion of 5 is in overlapping contact and a drain 8 is above the pixel electrode ITO 5 as shown in FIG.
  • a metal or metal alloy such as Mo/Al/Cu having a film thickness of 3000 to 5000 am on the semiconductor active layer 6 and the gate insulating layer 4 by physical sputtering, and then coating and exposing a metal structure of the source 7 and the drain 8 by a method such as development, wet etching, channel n+ etching, and lift-off, and the drain 8 and the pixel electrode ITO A portion of 5 is in overlapping contact and
  • Step S106 at the source 7, the drain 8, the semiconductor active layer 6, and the pixel electrode ITO 5 and the gate insulating layer 4, a layer of SiNx insulating protective layer 9 having a thickness of 2000-5000 am is deposited by plasma enhanced chemical vapor deposition, and then coated, exposed, developed, dry etched and stripped, etc.
  • a via structure is formed on the gate insulating layer 4 and the insulating protective layer 9 on the common electrode line 3, and a cross-sectional width of the via structure is smaller than a cross-sectional width of the common electrode line 3, which is advantageous for the latter common electrode 10 is in better contact with the common electrode line 3 as shown in FIG.
  • Step S107 at the pixel electrode ITO 5 corresponding insulating protective layer 9 and a transparent conductive material such as ITO of 300-1000 am deposited by physical sputtering on the via structure, and then the common electrode 10 structure is formed by coating, exposure, development, wet etching and peeling. As shown in Figure 7.
  • an FFS array substrate of the present invention includes a substrate 1 , a gate line (not shown), a gate 2 , a common electrode line 3 , a gate insulating layer 4 , and a data line ( Not shown in the figure), pixel electrode ITO 5.
  • a gate line, a gate electrode 2, and a common electrode line 3 are formed on the substrate 1.
  • a gate insulating layer 4 is formed on the substrate 1 , the gate insulating layer 4 covers the gate line, the gate 2 and the common electrode line 3 , and a data line is further formed on the gate insulating layer 4 .
  • Pixel electrode ITO of the FFS array substrate of the present invention 5 formed on the gate insulating layer 4 between the gate 2 and the common electrode line 3, a semiconductor active layer 6, formed on the gate insulating layer 4 corresponding to the gate 2, and
  • the cross-sectional width of the semiconductor active layer 6 is smaller than the cross-sectional width of the gate 2, which is advantageous for making the TFT channel within the range of the gate 2, as shown in FIG.
  • the source 7 and the drain 8 of the FFS array substrate of the present invention are both formed on the gate insulating layer 4, and the source 7 and the drain 8 are respectively in contact with both ends of the semiconductor active layer 6. Forming a TFT channel, the drain 8 and the pixel electrode ITO A portion of 5 is in overlapping contact and a drain 8 is above the pixel electrode ITO 5 .
  • the FFS array substrate of the present invention is at the pixel electrode ITO 5.
  • the semiconductor active layer 6, the source 7, the drain 8 and the gate insulating layer 4 are covered with an insulating protective layer 9, and the gate insulating layer 4 and the insulating layer on the common electrode line 3 are insulated.
  • the protective layer 9 is formed with a via structure, and the cross-sectional width of the via structure is smaller than the cross-sectional width of the common electrode line 3, which is advantageous for the later common electrode 10 and the common electrode line 3 to better contact, as shown in FIG. Show.
  • the common electrode ITO is formed on the upper surface of the insulating protective layer and the via structure corresponding to the pixel electrode.
  • the thickness of the gate electrode 2 and the common electrode line 3 is 3000 to 5000 am, and the thickness of the gate insulating layer 4 is 2000 to 5000 am, and the pixel electrode ITO
  • the thickness of 5 is 300 to 1000 am
  • the thickness of the semiconductor active layer 6 is 1300 to 2000 am
  • the thickness of the insulating protective layer 9 is 2000 to 5000 am
  • the thickness of the common electrode 10 is 300 to 1000 am
  • the gate insulation The material of the layer 4 and the insulating protective layer 9 is SiNx
  • the material of the semiconductor active layer 6 is amorphous silicon or doped amorphous silicon
  • the pixel electrode is ITO.
  • the material of the 5 and the common electrode 10 is ITO.
  • a display device comprising the FFS array substrate described in Embodiments 1 and 2 above.

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Abstract

一种FFS阵列基板的制造方法、一种FFS阵列基板和一种显示装置，该显示装置包括上述FFS阵列基板。该方法包括：在阵列基板（1）上形成栅极（2）与公共电极线（3）；形成栅极绝缘层（4）；形成一层像素电极ITO（5）；形成一层半导体有源层（6）；形成源极（7）及漏极（8）；形成一层绝缘保护层（9）并形成过孔结构；形成公共电极（10）结构。

Description

一种FFS阵列基板及其制造方法和显示装置 技术领域
本发明涉及液晶显示器技术领域，特别涉及一种FFS阵列基板及其制造方法和显示装置。
 背景技术
边缘场开关（Fringe Field Switching，简称FFS）技术，是目前的一种液晶显示器技术，是液晶界为解决大尺寸，高清晰桌面显示器和液晶电视应用而开发的一种广视角技术。FFS液晶面板具有响应时间快、光透过率高，宽视角等优点，但是由于FFS液晶面板采用两层氧化铟锡(Indium tin oxide,简称ITO)来制作，它本身的制作流程要比一般的液晶面板要多一到两道掩膜工艺。为了提升像素ITO与金属间的接触电导性，减少掩膜工艺，现有改进技术将像素 ITO直接制作在源漏极金属上，从而减少了一层绝缘保护层的制作工艺，但是由于半导体层会直接与ITO刻蚀液接触，因此半导体层有源层容易受到ITO刻蚀液的损伤，进而影响到半导体有源层的导电特性。
 技术问题
本发明的目的在于提供一种FFS阵列基板的制造方法，该制造方法在不增加制作工艺的基础上，克服了现有技术的像素电极ITO刻蚀对半导体有源层的损伤。本发明另外提供一种FFS阵列基板和一种显示装置。
 技术解决方案
本发明的技术方案如下：
一种FFS阵列基板的制造方法，包括以下步骤：
（1）在阵列基板上形成金属层，并通过图形化处理得到栅极与公共电极线；
（2）在所述栅极和公共电极线上形成栅极绝缘层，所述栅极绝缘层覆盖整个阵列基板；
（3）在所述栅极和公共电极线之间的栅极绝缘层上形成一层像素电极ITO；
(4)在所述栅极处上的栅极绝缘层上形成一层半导体有源层，且所述半导体有源层的截面宽度小于所述栅极的截面宽度；
(5)在所述半导体有源层与栅极绝缘层上面形成源极及漏极，且所述漏极与所述像素电极ITO的一部分重叠接触且漏极在所述像素电极ITO上面；
(6)在所述源极、漏极、半导体有源层、像素电极ITO及栅极绝缘层上形成一层绝缘保护层，并在所述公共电极线上面的栅极绝缘层与绝缘保护层上形成过孔结构，且过孔结构的截面宽度小于所述公共电极线的截面宽度；
(7)在所述像素电极ITO对应的绝缘保护层与过孔结构上面形成公共电极结构。
优选地，所述步骤1的栅极与公共电极线的厚度为3000～5000am。
优选地，所述步骤1的栅极与公共电极线是通过物理溅射沉淀Al或Cu金属形成的。
优选地，所述步骤2的栅极绝缘层厚度为2000～5000am。
优选地，步骤2的栅极绝缘层是通过等离子体增强化学气相沉积法沉淀SiNx形成的。
优选地，所述步骤3的像素电极ITO厚度为300～1000am。
优选地，所述步骤3的像素电极ITO是通过物理溅射ITO材料形成的。
优选地，所述步骤4的半导体有源层的厚度为1300～2000am。
优选地，所述步骤4的半导体有源层是通过等离子体增强化学气相沉积法沉淀非晶硅或掺杂非晶硅材料所形成的。
优选地，所述绝缘保护层的厚度为2000～5000am。
优选地，所述绝缘保护层的制作材料为SiNx。
优选地，所述公共电极的厚度为300～1000am。
优选地，所述公共电极的制作材料为ITO。
一种FFS阵列基板，包括：
基板；
栅线，形成于所述基板上；
栅极，形成于所述基板上；
公共电极线，形成于所述基板上；
栅极绝缘层，形成在所述基板上，并覆盖所述栅线、栅极与公共电极线；
数据线，形成在所述栅极绝缘层上面；
像素电极ITO，形成在栅极与公共电极线之间的所述栅极绝缘层上面；
半导体有源层，形成在所述栅极对应的所述栅极绝缘层上，且所述半导体有源层的截面宽度小于所述栅极的截面宽度；
源极与漏极，均形成在所述栅极绝缘层上面，所述源极和漏极分别与所述半导体有源层两端相接触，形成TFT沟道，所述漏极与所述像素电极ITO一部分重叠接触且漏极在所述像素电极ITO上面；
绝缘保护层，所述绝缘保护层覆盖在所述像素电极ITO、半导体有源层、源极、漏极与栅极绝缘层上；
过孔结构，形成在所述公共电极线上面的所述栅极绝缘层与绝缘保护层上，且过孔结构的截面宽度小于所述公共电极线的截面宽度；以及
公共电极ITO，所述公共电极ITO形成在所述像素电极对应的绝缘保护层与过孔结构的上面。
优选地，所述栅极与公共电极线的厚度为3000～5000am，所述栅极绝缘层厚度为2000～5000am。
优选地，所述像素电极ITO厚度为300～1000am，所述半导体有源层的厚度为1300～2000am。
优选地，所述绝缘保护层的厚度为2000～5000am，所述公共电极的厚度为300～1000am。
优选地，所述栅极绝缘层与绝缘保护层的制作材料为SiNx，所述半导体有源层的制作材料为非晶硅或掺杂非晶硅。
优选地，所述像素电极与公共电极的制作材料为ITO。
一种显示装置，其包括上述的FFS阵列基板。
 有益效果
本发明一种FFS阵列基板的制造方法，将像素电极ITO的制作工艺提到半导体有源层的制作工艺之前，在不增加制作工艺的基础上，克服了现有技术的像素电极ITO刻蚀对半导体有源层的损伤。本发明的一种FFS阵列基板，像素电极ITO处于漏极的下面，结构更加简单。
 附图说明
图1为本发明的FFS阵列基板的制造方法流程图；
图2为本发明的基板上形成栅极与公共电极线的结构示意图；
图3为本发明的基板上形成栅极绝缘层与像素电极ITO的结构示意图；
图4为本发明的基板上形成半导体有源层的结构示意图；
图5为本发明的基板上形成源极和漏极的结构示意图；
图6为本发明的基板上形成绝缘保护层和过孔结构的示意图；
图7 为本发明的基板上形成公共电极后的完整结构示意图；
图8 为现有技术的FFS阵列基板的结构示意图；
图9为现有技术的FFS阵列基板形成半导体有源层时的结构示意图；
图10为现有技术的FFS阵列基板形成源极和漏极时的结构示意图；
图11为现有技术的FFS阵列基板形成像素电极ITO时的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例1
如图1所示，为本发明的一种FFS阵列基板的制造方法的流程图，图2至图7为本发明一种FFS阵列基板的制造工艺顺序图，从图1至图7可以看出，本发明的一种FFS阵列基板的制造方法包括以下几个步骤：
步骤S101：在基板1上通过物理溅射沉淀一层膜厚为3000～5000am的Mo/Al/Cu等金属或金属合金，然后通过涂布、曝光、显影、湿蚀刻和剥离等方法形成栅极2与公共电极线3，如图2所示。
步骤S102：在所述栅极2和公共电极线3上，通过等离子体增强化学气相沉积法沉淀一层厚度为2000～5000am的SiNx栅极绝缘层4，所述栅极绝缘层4覆盖整个基板1。
步骤S103：然后通过物理溅射沉淀一层300～1000am的ITO等透明导电材料，通过涂布、曝光、显影、湿蚀刻和剥离等方法形成像素电极结构5，如图3所示。
本步骤与现有技术存在很大的不同，如图8为现有技术的FFS阵列基板的结构示意图，图9至图11是该现有技术的FFS阵列基板的制造工艺顺序图的一部分，从图9可以看出，现有技术的FFS阵列基板在完成栅极绝缘层4后，不是像本发明那样直接在栅极绝缘层4上形成本发明的像素电极ITO 5，而是在栅极2对应的栅极绝缘层4形成半导体有源层6，然后形成源极7和漏极8，接着才是形成现有技术的像素电极ITO 5。现有技术的这种制造方法，由于半导体有源层6会直接与像素电极ITO 5的刻蚀液相接触，会导致半导体有源层6受到像素电极ITO 5的刻蚀液的损伤，进而影响到半导体有源层6的导电特性。而本发明的本步骤的做法恰恰相反，在完成栅极绝缘层4后，直接在栅极绝缘层4上形成像素电极ITO 5，然后再形成半导体有源层6以及源极7和漏极8，这样就避免了像素电极ITO 5的刻蚀液对半导体有源层6的损伤。
步骤S104：在所述栅极2处上的栅极绝缘层4上，用等离子体增强化学气相沉积法沉淀一层膜厚为1300A～2000am的非晶硅和掺杂非晶硅，然后通过涂布、曝光、显影、干蚀刻和剥离等方法形成半导体有源层6结构，且所述半导体有源层6的截面宽度小于所述栅极2的截面宽度，这样有利于使TFT沟道处于栅极2的范围之内，如图4所示；
步骤S105：在所述半导体有源层6与栅极绝缘层4上面，通过物理溅射沉淀一层膜厚为3000～5000am的Mo/Al/Cu等金属或金属合金，然后通过涂布、曝光、显影、湿蚀刻、沟道n+刻蚀和剥离等方法形成源极7和漏极8的金属结构，且所述漏极8与所述像素电极ITO 5的一部分重叠接触且漏极8在所述像素电极ITO 5的上面，如图5所示。
步骤S106：在所述源极7、漏极8、半导体有源层6、像素电极ITO 5及栅极绝缘层4上，通过等离子体增强化学气相沉积法沉淀一层厚度为2000～5000am的SiNx绝缘保护层9材料，然后通过涂布、曝光、显影、干蚀刻和剥离等方法，在所述公共电极线3上面的栅极绝缘层4与绝缘保护层9上形成过孔结构，且过孔结构的截面宽度小于所述公共电极线3的截面宽度，这样做有利于后面的公共电极10和公共电极线3更好地接触，如图6所示。
步骤S107：在所述像素电极ITO 5对应的绝缘保护层9与过孔结构上面通过物理溅射沉淀一层300～1000am的ITO等透明导电材料，然后通过涂布、曝光、显影、湿蚀刻和剥离等方法形成公共电极10结构，如图7所示。
至此，本发明的FFS阵列基板的制造方法的各个步骤全部完成。
实施例2
如图2至图7所示，本发明的一种FFS阵列基板，包括基板1、栅线（图中未标出）、栅极2、公共电极线3、栅极绝缘层4、数据线（图中未标出）、像素电极ITO 5、半导体有源层6、源极7、漏极8、绝缘保护层9和公共电极10。所述基板1上形成有栅线、栅极2和公共电极线3。所述基板1上形成有栅极绝缘层4，所述栅极绝缘层4覆盖所述栅线、栅极2与公共电极线3，所述栅极绝缘层4上面还形成有数据线。
本发明的FFS阵列基板的像素电极ITO 5，形成在栅极2与公共电极线3之间的所述栅极绝缘层4上面，半导体有源层6，形成在所述栅极2对应的所述栅极绝缘层4上，且所述半导体有源层6的截面宽度小于所述栅极2的截面宽度，这样有利于使TFT沟道处于栅极2的范围之内，如图4所示。
本发明的FFS阵列基板的源极7与漏极8，均形成在所述栅极绝缘层4上面，所述源极7和漏极8分别与所述半导体有源层6两端相接触，形成TFT沟道，所述漏极8与所述像素电极ITO 5的一部分重叠接触且漏极8在所述像素电极ITO 5上面。
本发明的FFS阵列基板在所述像素电极ITO 5、半导体有源层6、源极7、漏极8与栅极绝缘层4上，覆盖有一层绝缘保护层9，且在所述公共电极线3上面的所述栅极绝缘层4与绝缘保护层9上形成有过孔结构，过孔结构的截面宽度小于所述公共电极线3的截面宽度，这样做有利于后面的公共电极10和公共电极线3更好地接触，如图6所示。所述公共电极ITO形成在所述像素电极对应的绝缘保护层与过孔结构的上面。
另外，本实施例优选所述栅极2与公共电极线3的厚度为3000～5000am，栅极绝缘层4的厚度为2000～5000am，像素电极ITO 5的厚度为300～1000am，半导体有源层6的厚度为1300～2000am，所述绝缘保护层9的厚度为2000～5000am，所述公共电极10的厚度为300～1000am，所述栅极绝缘层4与绝缘保护层9的制作材料为SiNx，所述半导体有源层6的制作材料为非晶硅或掺杂非晶硅，所述像素电极ITO 5与公共电极10的制作材料为ITO。
实施例3
一种显示装置，包括上述实施例1和实施例2所述的FFS阵列基板。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种FFS阵列基板的制造方法，其包括以下步骤：
    （1）在阵列基板上形成金属层，并通过图形化处理得到栅极与公共电极线；
    （2）在所述栅极和公共电极线上形成栅极绝缘层，所述栅极绝缘层覆盖整个阵列基板；
    （3）在所述栅极和公共电极线之间的栅极绝缘层上形成一层像素电极ITO；
    （4）在所述栅极处上的栅极绝缘层上形成一层半导体有源层，且所述半导体有源层的截面宽度小于所述栅极的截面宽度；
    （5）在所述半导体有源层与栅极绝缘层上面形成源极及漏极，且所述漏极与所述像素电极ITO的一部分重叠接触且漏极在所述像素电极ITO上面；
    （6）在所述源极、漏极、半导体有源层、像素电极ITO及栅极绝缘层上形成一层绝缘保护层，并在所述公共电极线上面的栅极绝缘层与绝缘保护层上形成过孔结构，且过孔结构的截面宽度小于所述公共电极线的截面宽度；
    （7）在所述像素电极ITO对应的绝缘保护层与过孔结构上面形成公共电极结构。
  2. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述步骤1的栅极与公共电极线的厚度为3000～5000am。
  3. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述步骤1的栅极与公共电极线是通过物理溅射沉淀Al或Cu金属形成的。
  4. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述步骤2的栅极绝缘层厚度为2000～5000am。
  5. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述步骤2的栅极绝缘层是通过等离子体增强化学气相沉积法沉淀SiNx形成的。
  6. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述步骤3的像素电极ITO厚度为300～1000am。
  7. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述步骤3的像素电极ITO是通过物理溅射ITO材料形成的。
  8. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述步骤4的半导体有源层的厚度为1300～2000am。
  9. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述步骤4的半导体有源层是通过等离子体增强化学气相沉积法沉淀非晶硅或掺杂非晶硅材料所形成的。
  10. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述绝缘保护层的厚度为2000～5000am。
  11. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述绝缘保护层的制作材料为SiNx。
  12. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述公共电极的厚度为300～1000am。
  13. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述公共电极的制作材料为ITO。
  14. 一种FFS阵列基板，其包括：
    基板；
    栅线，形成于所述基板上；
    栅极，形成于所述基板上；
    公共电极线，形成于所述基板上；
    栅极绝缘层，形成在所述基板上，并覆盖所述栅线、栅极与公共电极线；
    数据线，形成在所述栅极绝缘层上面；
    像素电极ITO，形成在栅极与公共电极线之间的所述栅极绝缘层上面；
    半导体有源层，形成在所述栅极对应的所述栅极绝缘层上，且所述半导体有源层的截面宽度小于所述栅极的截面宽度；
    源极与漏极，均形成在所述栅极绝缘层上面，所述源极和漏极分别与所述半导体有源层两端相接触，形成TFT沟道，所述漏极与所述像素电极ITO一部分重叠接触且漏极在所述像素电极ITO上面；
    绝缘保护层，所述绝缘保护层覆盖在所述像素电极ITO、半导体有源层、源极、漏极与栅极绝缘层上；
    过孔结构，形成在所述公共电极线上面的所述栅极绝缘层与绝缘保护层上，且过孔结构的截面宽度小于所述公共电极线的截面宽度；以及
    公共电极ITO，所述公共电极ITO形成在所述像素电极对应的绝缘保护层与过孔结构的上面。
  15. 根据权利要求14所述的FFS阵列基板，其中所述栅极与公共电极线的厚度为3000～5000am，栅极绝缘层厚度为2000～5000am。
  16. 根据权利要求14所述的FFS阵列基板，其中所述像素电极ITO厚度为300～1000am，半导体有源层的厚度为1300～2000am。
  17. 根据权利要求14所述的FFS阵列基板，其中所述绝缘保护层的厚度为2000～5000am，所述公共电极的厚度为300～1000am。
  18. 根据权利要求14所述的FFS阵列基板，其中所述栅极绝缘层与绝缘保护层的制作材料为SiNx，所述半导体有源层的制作材料为非晶硅或掺杂非晶硅。
  19. 根据权利要求7所述的FFS阵列基板，其中所述像素电极与公共电极的制作材料为ITO。
  20. 一种显示装置，其包括权利要求14～19所述的FFS阵列基板。
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CN104037126A (zh) * 2014-05-16 2014-09-10 京东方科技集团股份有限公司 一种阵列基板的制备方法、阵列基板和显示装置

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