WO2017024573A1 - 一种阵列基板及其制作方法 - Google Patents

一种阵列基板及其制作方法 Download PDF

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Publication number
WO2017024573A1
WO2017024573A1 PCT/CN2015/086821 CN2015086821W WO2017024573A1 WO 2017024573 A1 WO2017024573 A1 WO 2017024573A1 CN 2015086821 W CN2015086821 W CN 2015086821W WO 2017024573 A1 WO2017024573 A1 WO 2017024573A1
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Prior art keywords
layer
forming
metal layer
array substrate
semiconductor layer
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PCT/CN2015/086821
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English (en)
French (fr)
Inventor
王笑笑
杜鹏
王聪
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深圳市华星光电技术有限公司
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Priority to US14/779,545 priority Critical patent/US9865619B2/en
Publication of WO2017024573A1 publication Critical patent/WO2017024573A1/zh

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    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • LTPS Low temperature polysilicon Poly-silicon
  • the reticle process on the array substrate side is more complicated, and generally adopts about ten reticle process, which greatly reduces the production capacity of the product, and is affected by the complexity of the process, and the product yield is also low. Therefore, it is difficult to promote it greatly, and it can only be applied to small-sized products.
  • a conventional method for fabricating an array substrate includes forming a light shielding layer 11 on a substrate 10; Forming the buffer layer 12, forming a semiconductor layer 13 on the buffer layer 12, the semiconductor layer 13 needs to be heavily doped and lightly doped by means of exposure development, and forming a first insulating layer 14 on the semiconductor layer 13, in the first insulating layer A first metal layer 15 is formed on the first metal layer 15, a second insulating layer 16 is formed on the first metal layer 15, a second metal layer 17 is formed on the second insulating layer 16, and a flat layer 18 is formed on the second metal layer 17, a first transparent conductive layer 101 is formed on the flat layer 18 not corresponding to the source and drain regions; the first transparent conductive layer 101 is connected to the non-source drain portion of the second metal layer through the via, corresponding to the source and drain regions A second transparent conductive layer 102 is formed on the flat layer 18, the second transparent conductive layer 102 is connected to the source
  • the light shielding layer, the semiconductor layer, the heavily doped, the lightly doped, and the flat layer, the source and drain electrodes, the second insulating layer, the first transparent conductive layer, the third insulating layer, and the second transparent conductive layer are all produced.
  • the mask is required for exposure, so the process is complicated, the process requirements of the process are high, and the production cost is high.
  • the object of the present invention is to provide an array substrate and a manufacturing method thereof, which solve the technical problems that the prior art process is complicated, the production cost is high, and the application is not suitable for large size.
  • the present invention constructs a method for fabricating an array substrate, comprising the following steps:
  • the material of the light shielding layer is amorphous silicon
  • the semiconductor layer is used to form a channel;
  • first transparent conductive layer Forming a first transparent conductive layer on the flat layer; the first transparent conductive layer is connected to the second metal layer through the first via.
  • the method further includes:
  • a first triggering conductive material by diffusion or ion implantation; the first triggering conductive material for improving conductivity of the semiconductor layer; a concentration of the first triggering conductive substance in the patterned semiconductor layer is greater than a first predetermined concentration, wherein the first portion is not covered by the gate in the patterned semiconductor layer section.
  • the method further includes:
  • the method further includes: disposing on the second insulating layer and the first insulating layer There is a second via; the source and the drain are connected to the semiconductor layer through the second via.
  • the material of the insulating film is silicon dioxide.
  • the method before the step of forming a planar layer on the second metal layer and the second insulating layer not covered by the second metal layer, the method further includes:
  • a second transparent conductive layer is formed on the second metal layer corresponding to the common electrode.
  • the first transparent conductive layer includes a pixel electrode.
  • the material of the semiconductor layer is low temperature polysilicon.
  • the present invention constructs a method for fabricating an array substrate, comprising the following steps:
  • the semiconductor layer is used to form a channel
  • first transparent conductive layer Forming a first transparent conductive layer on the flat layer; the first transparent conductive layer is connected to the second metal layer through the first via.
  • the method further includes:
  • a first triggering conductive material by diffusion or ion implantation; the first triggering conductive material for improving conductivity of the semiconductor layer; a concentration of the first triggering conductive substance in the patterned semiconductor layer is greater than a first predetermined concentration, wherein the first portion is not covered by the gate in the patterned semiconductor layer section.
  • the method further includes:
  • the method further includes: disposing on the second insulating layer and the first insulating layer There is a second via; the source and the drain are connected to the semiconductor layer through the second via.
  • the material of the light shielding layer is amorphous silicon
  • the method further includes: performing an oxidation treatment on the light shielding layer to form an insulating film on a surface of the light shielding layer; the material of the insulating film is silicon dioxide.
  • the method further includes:
  • a third via is disposed on the second insulating layer corresponding to the common electrode to bring the second metal layer into contact with the common electrode.
  • the method before the step of forming a planar layer on the second metal layer and the second insulating layer not covered by the second metal layer, the method further includes:
  • a second transparent conductive layer is formed on the second metal layer corresponding to the common electrode.
  • the first transparent conductive layer includes a pixel electrode.
  • the invention also provides an array substrate comprising:
  • the semiconductor layer being used to form a channel
  • the first metal layer including a gate region and a common electrode region of the thin film transistor
  • the second metal layer including a drain region and a source region of the thin film transistor
  • the flat layer is provided with a first via hole
  • first transparent conductive layer on the flat layer; the first transparent conductive layer being connected to the second metal layer through the first via.
  • a second transparent conductive layer is further disposed on the second metal layer corresponding to the common electrode.
  • the first transparent conductive layer includes a pixel electrode.
  • the material of the semiconductor layer is low temperature polysilicon.
  • the array substrate of the present invention and the manufacturing method thereof are improved by the existing process method, thereby simplifying the production process and reducing the production cost.
  • FIG. 1 is a schematic structural view of a prior art array substrate
  • FIG. 2 is a schematic structural view of an array substrate of the present invention
  • FIG. 3 is a schematic structural view of the first to third steps of the method for fabricating the array substrate of the present invention.
  • FIG. 4 is a schematic structural view of a fourth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 5 is a schematic structural view of a fifth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 6 is a schematic structural view of a sixth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 7 is a schematic structural view of a seventh step of a method for fabricating an array substrate according to the present invention.
  • FIG. 8 is a schematic structural view of an eighth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 9 is a schematic structural view of a ninth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 10 is a schematic structural view of a tenth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 11 is a schematic structural view of an eleventh step of a method for fabricating an array substrate according to the present invention.
  • FIG. 12 is a schematic structural view of a twelfth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 13 is a schematic structural view of a thirteenth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 14 is a schematic structural view of a fourteenth step of a method for fabricating an array substrate according to the present invention.
  • FIG. 15 is a schematic structural view of the fifteenth step of the method for fabricating the array substrate of the present invention.
  • FIG. 2 is a schematic structural view of an array substrate according to the present invention.
  • the array substrate of the present invention includes a base substrate 21, a buffer layer 22, a light shielding layer 23, a semiconductor layer 24, a first insulating layer 25, a first metal layer, a second insulating layer 27, and a second metal layer. 28, a flat layer 29, a first transparent conductive layer 30;
  • the buffer layer 22 is located on the base substrate 21; the light shielding layer 23 is located on the buffer layer 22; the semiconductor layer 24 is located on the light shielding layer 23, and the semiconductor layer 24 and the light shielding layer An insulating film 231 is disposed between the layers 23, the semiconductor layer 24 is for forming a channel; the first insulating layer 25 is located on the semiconductor layer 24; and the first metal layer is located at the first insulating layer 25.
  • the second insulating layer 27 is located on the first metal layer; the second metal layer 28 is located on the second insulating layer 27
  • the second metal layer 28 includes a drain region and a source region of the thin film transistor; the planar layer 29 is located on the second metal layer 28 and the second insulating layer 27 not covered by the second metal layer.
  • a first via 201 is disposed on the flat layer 29; the first transparent conductive layer 30 is located on the flat layer 29; the first transparent conductive layer 30 passes through the first via 201 and the second The metal layer 28 is joined.
  • the first transparent conductive layer 30 includes a pixel electrode.
  • a second transparent conductive layer 31 is further disposed on the second metal layer 28 corresponding to the common electrode 261.
  • the manufacturing method of the above array substrate comprises:
  • a buffer layer 22 is formed on the base substrate 21;
  • the material of the light shielding layer is amorphous silicon, such as a-si.
  • the light shielding layer is oxidized to form an insulating film 231 on the surface of the light shielding layer;
  • the silicon dioxide insulating film 231 is formed on the surface thereof, and the charge in the channel can be effectively prevented from being transferred to the amorphous silicon.
  • the entire semiconductor layer and the entire light shielding layer are simultaneously exposed and developed by the first mask, and only part of the light shielding layer 23, the insulating film 231, and the semiconductor layer 24 are sequentially covered.
  • the buffer layer 22; the semiconductor layer 24 is used to form a channel; the material of the semiconductor layer 24 is, for example, low temperature poly polysilicon.
  • the insulating film 231 can effectively prevent charge in the channel from being transferred into the light shielding layer 23.
  • the material of the first insulating layer 25 may be an inorganic transparent material.
  • the step 106 is specifically: forming a gate electrode 26 and a common electrode 261 by exposing and developing the first metal layer through a patterned mask (second mask); The first metal layer other than the gate electrode 26 and the common electrode 261 is etched away in the process.
  • the material of the first metal layer may be chromium, molybdenum, aluminum or copper or the like.
  • the method further comprises:
  • the first portion of the patterned semiconductor layer 24 is heavily doped; the first triggering conductive material is used to improve the conductivity of the semiconductor layer; a concentration of the conductive material in the patterned semiconductor layer is greater than a first predetermined concentration, wherein the first portion 241 is not covered by the gate 26 in the patterned semiconductor layer 24. section.
  • the first triggering conductive material is, for example, an atom such as a pentavalent element such as arsenic, antimony or phosphorus; and in step S201, the drain and source obtained by the process can be brought into ohmic contact with the semiconductor layer, respectively.
  • S203, in the second portion of the patterned semiconductor layer 24 is doped with a second triggering conductive material by diffusion or ion implantation;
  • the second portion of the patterned semiconductor layer is lightly doped, and the second triggering conductive material is used to improve the conductivity of the semiconductor layer; a concentration of the conductive material in the patterned semiconductor layer is less than a second predetermined concentration, wherein the second portion 242 is a gate that is not etched in the patterned semiconductor layer A portion that covers and does not overlap the first portion 241.
  • the second triggering conductive material is, for example, an atom such as a pentavalent element such as arsenic, antimony or phosphorus; wherein the first predetermined concentration is greater than the second predetermined concentration.
  • the present invention when heavily doping, it is necessary to use a mask to perform light-shielding treatment, and the present invention directly shields the semiconductor layer by using the gate region of the first metal layer, thereby further saving the process procedure.
  • the present invention when lightly doping, it is also required to perform a light-shielding process using a mask, and the present invention etches the gate region of the first metal layer and uses the gate region of the first metal layer after etching. The semiconductor layer is shielded from light, which further saves the process.
  • the second insulating layer 27 is formed on the first metal layer and the first insulating layer 25 not covered by the first metal layer.
  • the material of the second insulating layer 27 may be an organic transparent material.
  • the method further comprises:
  • step S302 a third via hole 203 is provided on the second insulating layer 27 corresponding to the common electrode 261.
  • the method further comprises:
  • S301 simultaneously exposing and developing the second insulating layer and the first insulating layer through a third mask; to provide a second on the second insulating layer and the first insulating layer Via 202.
  • the second metal layer 28 is subjected to exposure development and etching to form a drain and a source through a patterned mask (fourth mask); the second metal layer
  • the material of 28 may be chromium, molybdenum, aluminum or copper.
  • a second metal layer 28 is formed on the second insulating layer 27 and the third via 203 such that the second metal layer 28 is in direct contact with the common electrode 261. Therefore, when the third via hole is formed, since the thickness of the second insulating layer 27 is relatively large, the first metal layer is prevented from being damaged.
  • the source and the drain are connected to the semiconductor layer 24 through the two second vias 202.
  • the method further comprises:
  • the second transparent conductive layer 31 is connected to the common electrode 261 for forming a storage capacitor.
  • S109 specifically includes the second metal layer 28, the second transparent conductive layer 31, and the second metal layer 28, which are not covered by the second transparent conductive layer 31.
  • a flat layer 29 is formed on the second insulating layer 27 covered by the second transparent conductive layer 31.
  • the flat via layer 29 is formed with a first via hole 201; the first via hole 201 is formed by developing exposure of the flat layer through a sixth mask.
  • the first transparent conductive layer 30 may be formed on the flat layer 29 provided with a first via hole by a sputtering plating method.
  • a pixel electrode is disposed on the first transparent conductive layer 30, and the first transparent conductive layer is developed and exposed through a seventh mask to form the pixel electrode.
  • the first transparent conductive layer 30 is connected to the second metal layer 28 through the first via 201, and the first transparent conductive layer 30 is connected to a source or a drain.
  • the material of the prior art light shielding layer is usually a metal for preventing the mobility of carriers in the semiconductor layer from changing when the backlight is irradiated.
  • the material of the light shielding layer of the present invention is amorphous silicon, and since amorphous silicon can absorb light that changes the mobility of carriers in the semiconductor layer, it is possible to prevent the mobility of the semiconductor layer from changing when the backlight is irradiated. Therefore, the same mask can be used to simultaneously expose the material of the light shielding layer and the material of the semiconductor layer, thereby saving the exposure process, simplifying the production process, and reducing the production cost.
  • the array substrate of the present invention and the manufacturing method thereof can improve the existing process method, and only need seven masks to complete the process of the array substrate, thereby simplifying the production process and reducing the production cost.

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Abstract

一种阵列基板及其制作方法，所述方法包括：在衬底基板(21)上形成缓冲层(22)、遮光层(23)、整层半导体层(24)，并对所述半导体层(24)和所述遮光层(23)同时进行图形化处理；然后在图形化处理后的半导体层(24)上依次形成第一绝缘层(25)、第一金属层(26,261)、第二绝缘层(27)、第二金属层(28)、平坦层(29)、第一透明导电层(30)。

Description

一种阵列基板及其制作方法 技术领域
本发明涉及液晶显示器技术领域，特别是涉及一种阵列基板及其制作方法。
 背景技术
低温多晶硅（Low temperature poly-silicon，简称LTPS），由于其具有高的电子迁移率，可以有效的减小TFT的器件的面积，提升像素的开口率，能够增大面板显示亮度的同时降低整体的功耗，使得面板的制造成本大幅度降低，目前已成为液晶显示领域的研究热点。
传统的LTPS设计中，阵列基板侧的光罩流程较为复杂，一般都采用十道左右光罩制程，这样大大的降低了产品生产制造的产能，而且受到工艺复杂的影响，产品良率也很低，所以很难大幅度的推广，目前只能应用在小尺寸产品上。
请参照图1，图1为现有技术的阵列基板的结构示意图，如图1所示，现有的阵列基板的制作方法，包括在衬底基板10上形成遮光层11；在遮光层11上形成缓冲层12，在缓冲层12上形成半导体层13，半导体层13需要通过曝光显影的方式重掺杂和轻掺杂，以及在半导体层13上形成第一绝缘层14，在第一绝缘层14上形成第一金属层15，在第一金属层15上第二绝缘层16，在第二绝缘层16上形成第二金属层17，并在第二金属层17上形成平坦层18，在未与源漏极区对应的平坦层18上形成第一透明导电层101；第一透明导电层101通过过孔与第二金属层的非源漏极部分连接，在与源漏极区对应的平坦层18上形成第二透明导电层102，第二透明导电层102与源极或者漏极连接，第一透明导电层101和第二透明导电层102之间设置有第三绝缘层19。
上述制程中遮光层、半导体层、重掺杂、轻掺杂、以及平坦层、源漏极、第二绝缘层、第一透明导电层、第三绝缘层、第二透明导电层的制作中都需要掩膜板进行曝光，因此制程比较复杂，对工艺的制程要求较高，导致生产成本较高。
因此，有必要提供一种阵列基板及其制作方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种阵列基板及其制作方法，以解决现有技术制程过程比较复杂，生产成本较高，不利于在大尺寸上应用的技术问题。
 技术解决方案
为解决上述技术问题，本发明构造了一种阵列基板的制作方法，包括以下步骤：
在衬底基板上形成缓冲层；
在所述缓冲层上形成整层遮光层；所述遮光层的材料为非晶硅；
对所述遮光层进行氧化处理，以在所述遮光层的表面形成绝缘膜；
在所述绝缘膜上形成整层半导体层，并对所述半导体层和具有所述绝缘膜的所述遮光层同时进行图形化处理，以使部分所述遮光层和部分所述半导体层依次覆盖在所述缓冲层上；所述半导体层用于形成沟道；
在所述图形化处理后的半导体层上形成第一绝缘层；
在所述第一绝缘层上形成第一金属层，对所述第一金属层进行图形化处理形成栅极和公共电极；
在所述第一金属层上形成第二绝缘层；
在与所述公共电极对应的所述第二绝缘层上设置第三过孔，以使所述第二金属层与所述公共电极接触；
在所述第二绝缘层上形成第二金属层，对所述第二金属层进行图形化处理形成漏极和源极；
在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层，所述平坦层上形成有第一过孔；
在所述平坦层上形成第一透明导电层；所述第一透明导电层通过所述第一过孔与所述第二金属层连接。
在本发明的阵列基板的制作方法中，所述在所述第一绝缘层上形成第一金属层的步骤之后，所述方法还包括：
在所述图形化处理后的半导体层的第一部分中通过扩散或者离子注入法掺入第一触发导电性物质；所述第一触发导电性物质用于提高所述半导体层的导电性能；所述第一触发导电性物质在所述图形化处理后的半导体层中的浓度大于第一预设浓度，其中所述第一部分为所述图形化处理后的半导体层中未被所述栅极覆盖的部分。
在本发明的阵列基板的制作方法中，所述方法还包括：
对所述栅极进一步蚀刻，以使得所述栅极覆盖在所述图形化处理后的半导体上的面积减小；
在所述图形化处理后的半导体层的第二部分中通过扩散或者离子注入法掺入第二触发导电性物质；所述第二触发导电性物质用于提高所述半导体层的导电性能；所述第二触发导电性物质在所述图形化处理后的半导体层中的浓度小于第二预设浓度，其中所述第二部分为所述图形化处理后的半导体层中未被所述蚀刻后的栅极覆盖，且与所述第一部分不重叠的部分。
在本发明的阵列基板的制作方法中，所述在所述第二绝缘层上形成第二金属层的步骤之后，所述方法还包括：在所述第二绝缘层以及第一绝缘层上设置有第二过孔；所述源极和所述漏极通过所述第二过孔与所述半导体层连接。
在本发明的阵列基板的制作方法中，所述绝缘膜的材料为二氧化硅。
在本发明的阵列基板的制作方法中，所述在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层的步骤之前，所述方法还包括：
在与所述公共电极对应处的第二金属层上形成第二透明导电层。
在本发明的阵列基板的制作方法中，所述第一透明导电层包括像素电极。
在本发明的阵列基板的制作方法中，所述半导体层的材料为低温多晶硅。
为解决上述技术问题，本发明构造了一种阵列基板的制作方法，包括以下步骤：
在衬底基板上形成缓冲层；
在所述缓冲层上形成整层遮光层；
在所述遮光层上形成整层半导体层，并对所述半导体层和所述遮光层同时进行图形化处理，以使部分所述遮光层和部分所述半导体层依次覆盖在所述缓冲层上；所述半导体层用于形成沟道；
在所述图形化处理后的半导体层上形成第一绝缘层；
在所述第一绝缘层上形成第一金属层，对所述第一金属层进行图形化处理形成栅极和公共电极；
在所述第一金属层上形成第二绝缘层；
在所述第二绝缘层上形成第二金属层，对所述第二金属层进行图形化处理形成漏极和源极；
在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层，所述平坦层上形成有第一过孔；
在所述平坦层上形成第一透明导电层；所述第一透明导电层通过所述第一过孔与所述第二金属层连接。
在本发明的阵列基板的制作方法中，所述在所述第一绝缘层上形成第一金属层的步骤之后，所述方法还包括：
在所述图形化处理后的半导体层的第一部分中通过扩散或者离子注入法掺入第一触发导电性物质；所述第一触发导电性物质用于提高所述半导体层的导电性能；所述第一触发导电性物质在所述图形化处理后的半导体层中的浓度大于第一预设浓度，其中所述第一部分为所述图形化处理后的半导体层中未被所述栅极覆盖的部分。
在本发明的阵列基板的制作方法中，所述方法还包括：
对所述栅极进一步蚀刻，以使得所述栅极覆盖在所述图形化处理后的半导体上的面积减小；
在所述图形化处理后的半导体层的第二部分中通过扩散或者离子注入法掺入第二触发导电性物质；所述第二触发导电性物质用于提高所述半导体层的导电性能；所述第二触发导电性物质在所述图形化处理后的半导体层中的浓度小于第二预设浓度，其中所述第二部分为所述图形化处理后的半导体层中未被所述蚀刻后的栅极覆盖，且与所述第一部分不重叠的部分。
在本发明的阵列基板的制作方法中，所述在所述第二绝缘层上形成第二金属层的步骤之后，所述方法还包括：在所述第二绝缘层以及第一绝缘层上设置有第二过孔；所述源极和所述漏极通过所述第二过孔与所述半导体层连接。
在本发明的阵列基板的制作方法中，所述遮光层的材料为非晶硅；
所述方法还包括：对所述遮光层进行氧化处理，以在所述遮光层的表面形成绝缘膜；所述绝缘膜的材料为二氧化硅。
在本发明的阵列基板的制作方法中，所述在所述第一金属层上形成第二绝缘层的步骤之后，所述方法还包括：
在与所述公共电极对应的所述第二绝缘层上设置第三过孔，以使所述第二金属层与所述公共电极接触。
在本发明的阵列基板的制作方法中，所述在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层的步骤之前，所述方法还包括：
在与所述公共电极对应处的第二金属层上形成第二透明导电层。
在本发明的阵列基板的制作方法中，所述第一透明导电层包括像素电极。
本发明还提供一种阵列基板，其包括：
缓冲层，位于衬底基板上；
遮光层，位于所述缓冲层上；
半导体层，位于所述遮光层上，所述半导体层用于形成沟道；
第一绝缘层，位于所述半导体层上；
第一金属层，位于所述第一绝缘层上，所述第一金属层包括薄膜晶体管的栅极区和公共电极区；
第二绝缘层，位于所述第一金属层上；
第二金属层，位于所述第二绝缘层上，所述第二金属层包括薄膜晶体管的漏极区和源极区；
平坦层，位于所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上；所述平坦层上设置有第一过孔；
第一透明导电层，位于所述平坦层上；所述第一透明导电层通过所述第一过孔与所述第二金属层连接。
在本发明的阵列基板中，在与所述公共电极对应处的第二金属层上还设置有第二透明导电层。
在本发明的阵列基板中，所述第一透明导电层包括像素电极。
在本发明的阵列基板中，所述半导体层的材料为低温多晶硅。
 有益效果
本发明的阵列基板及其制作方法，通过对现有的制程方法进行改进，从而简化生产过程，降低生产成本。
 附图说明
图1为现有技术的阵列基板的结构示意图；
图2为本发明阵列基板的结构示意图；
图3为本发明阵列基板的制作方法的第一至三步的结构示意图；
图4为本发明阵列基板的制作方法的第四步的结构示意图；
图5为本发明阵列基板的制作方法的第五步的结构示意图；
图6为本发明阵列基板的制作方法的第六步的结构示意图；
图7为本发明阵列基板的制作方法的第七步的结构示意图；
图8为本发明阵列基板的制作方法的第八步的结构示意图；
图9为本发明阵列基板的制作方法的第九步的结构示意图；
图10为本发明阵列基板的制作方法的第十步的结构示意图；
图11为本发明阵列基板的制作方法的第十一步的结构示意图；
图12为本发明阵列基板的制作方法的第十二步的结构示意图；
图13为本发明阵列基板的制作方法的第十三步的结构示意图；
图14为本发明阵列基板的制作方法的第十四步的结构示意图；
图15为本发明阵列基板的制作方法的第十五步的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明阵列基板的结构示意图。
本发明的阵列基板如图2所示，包括衬底基板21、缓冲层22、遮光层23、半导体层24、第一绝缘层25、第一金属层、第二绝缘层27、第二金属层28、平坦层29、第一透明导电层30；
所述缓冲层22位于所述衬底基板21上；所述遮光层23位于所述缓冲层22上；所述半导体层24位于所述遮光层23上，在所述半导体层24与所述遮光层23之间设置有绝缘膜231，所述半导体层24用于形成沟道；所述第一绝缘层25位于所述半导体层24上；所述第一金属层位于所述第一绝缘层25上，包括薄膜晶体管的栅极区26和公共电极区261；所述第二绝缘层27位于所述第一金属层上；所述第二金属层28位于所述第二绝缘层27上，所述第二金属层28包括薄膜晶体管的漏极区和源极区；所述平坦层29位于所述第二金属层28以及未被所述第二金属层覆盖的第二绝缘层27上，所述平坦层29上设置有第一过孔201；所述第一透明导电层30位于所述平坦层29上；所述第一透明导电层30通过所述第一过孔201与所述第二金属层28连接。所述第一透明导电层30包括像素电极。在与所述公共电极261对应的第二金属层28上还设置有第二透明导电层31。
上述阵列基板的制作方法包括：
如图3所示，S101、在衬底基板21上形成缓冲层22；
S102、在所述缓冲层22上形成整层遮光层23，
所述遮光层的材料为非晶硅，譬如a-si。
S103、对所述遮光层进行氧化处理，以在所述遮光层的表面形成绝缘膜231；
当所述遮光层23的材料为非晶硅时，经过氧化处理后，在其表面形成二氧化硅绝缘膜231，能够有效地防止沟道内的电荷转移到非晶硅中。
S104、在所述绝缘膜231上形成整层半导体层，并对所述半导体层和所述遮光层同时进行图形化处理；
如图4所示，通过第一道掩膜板对整层半导体层和整层遮光层同时进行曝光显影，仅部分所述遮光层23、所述绝缘膜231、所述半导体层24依次覆盖在所述缓冲层22上；所述半导体层24用于形成沟道；所述半导体层24的材料譬如为低温多多晶硅。所述绝缘膜231能够有效地防止沟道内的电荷转移到遮光层23中。
S105、在所述图形化处理后的半导体层24上形成第一绝缘层25；
如图5所示，所述第一绝缘层25的材料可为无机透明材料。
S106、在所述第一绝缘层25上形成第一金属层；
如图6所示，所述步骤106具体是通过带有图形的掩模板（第二道掩模板），对所述第一金属层经过曝光显影、蚀刻后形成栅极26和公共电极261；所述栅极26和所述公共电极261以外的第一金属层在制程中被蚀刻掉。所述第一金属层的材料可为铬、钼、铝或铜等。
优选地，在步骤S106之后，即在所述第一绝缘层上形成第一金属层的步骤之后，所述方法还包括：
S201、在所述图形化处理后的半导体层的第一部分中通过扩散或者离子注入法掺入第一触发导电性物质；
如图7所示，即对所述图形化处理后的半导体层24的第一部分进行重掺杂；所述第一触发导电性物质用于提高所述半导体层的导电性能；所述第一触发导电性物质在所述图形化处理后的半导体层中的浓度大于第一预设浓度，其中所述第一部分241为所述图形化处理后的半导体层24中未被所述栅极26覆盖的部分。所述第一触发导电性物质譬如为五价元素砷、锑、磷等原子；通过步骤S201，能够使得制程得到的漏极和源极分别与半导体层达到欧姆接触的效果。
S202、对所述栅极进一步蚀刻，以使得所述栅极覆盖在所述半导体上的面积减小；
S203、在所述图形化处理后的半导体层24的第二部分中通过扩散或者离子注入法掺入第二触发导电性物质；
如图8所示，即对所述图形化处理后的半导体层的第二部分进行轻掺杂，所述第二触发导电性物质用于提高所述半导体层的导电性能；所述第二触发导电性物质在所述图形化处理后的半导体层中的浓度小于第二预设浓度，其中所述第二部分242为所述图形化处理后的半导体层中未被所述蚀刻后的栅极覆盖，且与所述第一部分241不重叠的部分。所述第二触发导电性物质譬如为五价元素砷、锑、磷等原子；其中第一预设浓度大于第二预设浓度。经过S203处理后，使得半导体层中低温多晶硅的电子迁移率更好。
现有技术在重掺杂时，需要使用掩膜板进行遮光处理，而本发明直接使用第一金属层的栅极区对所述半导体层进行遮光，从而进一步节省了制程程序。现有技术在轻掺杂时，也需要使用掩膜板进行遮光处理，而本发明通过对第一金属层的栅极区蚀刻，并使用蚀刻后的第一金属层的栅极区对所述半导体层进行遮光，从而更加节省了制程程序。
S107、在所述第一金属层上形成第二绝缘层27；
如图9所示，具体是在第一金属层以及未被第一金属层覆盖的第一绝缘层25上形成所述第二绝缘层27。所述第二绝缘层27的材料可为有机透明材料。
优选地，在S107步骤之后，即所述在所述第一金属层上形成第二绝缘层的步骤之后，所述方法还包括：
如图10所示，S302、在与所述公共电极261对应的所述第二绝缘层27上设置第三过孔203。
优选地，在步骤S108之前，即在所述第二绝缘层上形成第二金属层的步骤之前，所述方法还包括：
如图11所示，S301、通过第三道掩膜板对所述第二绝缘层以及第一绝缘层同时进行曝光显影；以在所述第二绝缘层以及第一绝缘层上设置有第二过孔202。
S108、在所述第二绝缘层27上形成第二金属层28；
如图12所示，具体是通过带有图形的掩模板（第四道掩模板），对所述第二金属层28经过曝光显影、蚀刻后形成漏极和源极；所述第二金属层28的材料可为铬、钼、铝或铜等。
优选地，在所述第二绝缘层27上及所述第三过孔203形成第二金属层28，以使所述第二金属层28与所述公共电极261直接接触。从而防止制作第三过孔时，由于第二绝缘层27的厚度比较大，防止第一金属层被损坏。所述源极和所述漏极通过两个所述第二过孔202与所述半导体层24连接。
优选地，在步骤S109之前，即在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层的步骤之前，所述方法还包括：
如图13所示，S303、在与所述公共电极261对应处的第二金属层上形成第二透明导电层31；
在所述第二金属层上涂布整层第二透明导电层，通过第五道掩模板对所述第二透明导电层进行显影曝光，留下与所述公共电极261对应的部分；剩余部分被显影掉。
所述第二透明导电层31与所述公共电极261连接，用于形成存储电容。
S109、在所述第二金属层28以及未被所述第二金属层28覆盖的第二绝缘层27上形成平坦层29；
如图14所示，S109具体包括在未被所述第二透明导电层31覆盖的所述第二金属层28、所述第二透明导电层31以及未被所述第二金属层28和所述第二透明导电层31覆盖的第二绝缘层27上形成平坦层29。
优选地，如图15所示，其中所述平坦层29上形成有第一过孔201；通过第六道掩模板对所述平坦层进行显影曝光形成所述第一过孔201。
S110、在所述平坦层29上形成第一透明导电层30；
如图2所示，可以利用溅射镀膜法，在设置有第一过孔的所述平坦层29上形成所述第一透明导电层30。所述第一透明导电层30上设置有像素电极，通过第七道掩模板对所述第一透明导电层进行显影曝光，形成所述像素电极。所述第一透明导电层30通过所述第一过孔201与所述第二金属层28连接，所述第一透明导电层30与源极或者漏极连接。
现有技术的遮光层的材料通常为金属，用于防止背光源照射时，半导体层中载流子的迁移率发生变化。而本发明遮光层的材料为非晶硅，由于非晶硅能够吸收使半导体层中载流子的迁移率发生变化的光，因此能够防止在背光源照射时，半导体层的迁移率发生变化。从而可以使用同一掩膜板对遮光层的材料和半导体层的材料进行同时曝光，从而节省了曝光工序，简化了生产过程，降低生产成本。
本发明的阵列基板及其制作方法，通过对现有的制程方法进行改进，只需要七道掩模板就可以完成阵列基板的制程，从而简化生产过程，降低生产成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板的制作方法，其包括：
    在衬底基板上形成缓冲层；
    在所述缓冲层上形成整层遮光层；所述遮光层的材料为非晶硅；
    对所述遮光层进行氧化处理，以在所述遮光层的表面形成绝缘膜；
    在所述绝缘膜上形成整层半导体层，并对所述半导体层和具有所述绝缘膜的所述遮光层同时进行图形化处理，以使部分所述遮光层和部分所述半导体层依次覆盖在所述缓冲层上；所述半导体层用于形成沟道；
    在所述图形化处理后的半导体层上形成第一绝缘层；
    在所述第一绝缘层上形成第一金属层，对所述第一金属层进行图形化处理形成栅极和公共电极；
    在所述第一金属层上形成第二绝缘层；
    在与所述公共电极对应的所述第二绝缘层上设置第三过孔，以使所述第二金属层与所述公共电极接触；
    在所述第二绝缘层上形成第二金属层，对所述第二金属层进行图形化处理形成漏极和源极；
    在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层，所述平坦层上形成有第一过孔；以及
    在所述平坦层上形成第一透明导电层；所述第一透明导电层通过所述第一过孔与所述第二金属层连接。
  2. 根据权1所述的阵列基板的制作方法，其中所述在所述第一绝缘层上形成第一金属层的步骤之后，所述方法还包括：
    在所述图形化处理后的半导体层的第一部分中通过扩散或者离子注入法掺入第一触发导电性物质；所述第一触发导电性物质用于提高所述半导体层的导电性能；所述第一触发导电性物质在所述图形化处理后的半导体层中的浓度大于第一预设浓度，其中所述第一部分为所述图形化处理后的半导体层中未被所述栅极覆盖的部分。
  3. 根据权2所述的阵列基板的制作方法，其中所述方法还包括：
    对所述栅极进一步蚀刻，以使得所述栅极覆盖在所述图形化处理后的半导体上的面积减小；以及
    在所述图形化处理后的半导体层的第二部分中通过扩散或者离子注入法掺入第二触发导电性物质；所述第二触发导电性物质用于提高所述半导体层的导电性能；所述第二触发导电性物质在所述图形化处理后的半导体层中的浓度小于第二预设浓度，其中所述第二部分为所述图形化处理后的半导体层中未被所述蚀刻后的栅极覆盖，且与所述第一部分不重叠的部分。
  4. 根据权1所述的阵列基板的制作方法，其中所述在所述第二绝缘层上形成第二金属层的步骤之后，所述方法还包括：在所述第二绝缘层以及第一绝缘层上设置有第二过孔；所述源极和所述漏极通过所述第二过孔与所述半导体层连接。
  5. 根据权1所述的阵列基板的制作方法，其中
    所述绝缘膜的材料为二氧化硅。
  6. 根据权1所述的阵列基板的制作方法，其中所述在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层的步骤之前，所述方法还包括：
    在与所述公共电极对应处的第二金属层上形成第二透明导电层。
  7. 根据权1所述的阵列基板的制作方法，其中所述第一透明导电层包括像素电极。
  8. 根据权1所述的阵列基板的制作方法，其中所述半导体层的材料为低温多晶硅。
  9. 一种阵列基板的制作方法，其包括：
    在衬底基板上形成缓冲层；
    在所述缓冲层上形成整层遮光层；
    在所述遮光层上形成整层半导体层，并对所述半导体层和所述遮光层同时进行图形化处理，以使部分所述遮光层和部分所述半导体层依次覆盖在所述缓冲层上；所述半导体层用于形成沟道；
    在所述图形化处理后的半导体层上形成第一绝缘层；
    在所述第一绝缘层上形成第一金属层，对所述第一金属层进行图形化处理形成栅极和公共电极；
    在所述第一金属层上形成第二绝缘层；
    在所述第二绝缘层上形成第二金属层，对所述第二金属层进行图形化处理形成漏极和源极；
    在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层，所述平坦层上形成有第一过孔；以及
    在所述平坦层上形成第一透明导电层；所述第一透明导电层通过所述第一过孔与所述第二金属层连接。
  10. 根据权9所述的阵列基板的制作方法，其中所述在所述第一绝缘层上形成第一金属层的步骤之后，所述方法还包括：
    在所述图形化处理后的半导体层的第一部分中通过扩散或者离子注入法掺入第一触发导电性物质；所述第一触发导电性物质用于提高所述半导体层的导电性能；所述第一触发导电性物质在所述图形化处理后的半导体层中的浓度大于第一预设浓度，其中所述第一部分为所述图形化处理后的半导体层中未被所述栅极覆盖的部分。
  11. 根据权10所述的阵列基板的制作方法，其中所述方法还包括：
    对所述栅极进一步蚀刻，以使得所述栅极覆盖在所述图形化处理后的半导体上的面积减小；以及
    在所述图形化处理后的半导体层的第二部分中通过扩散或者离子注入法掺入第二触发导电性物质；所述第二触发导电性物质用于提高所述半导体层的导电性能；所述第二触发导电性物质在所述图形化处理后的半导体层中的浓度小于第二预设浓度，其中所述第二部分为所述图形化处理后的半导体层中未被所述蚀刻后的栅极覆盖，且与所述第一部分不重叠的部分。
  12. 根据权9所述的阵列基板的制作方法，其中所述在所述第二绝缘层上形成第二金属层的步骤之后，所述方法还包括：在所述第二绝缘层以及第一绝缘层上设置有第二过孔；所述源极和所述漏极通过所述第二过孔与所述半导体层连接。
  13. 根据权9所述的阵列基板的制作方法，其中所述遮光层的材料为非晶硅；
    所述方法还包括：对所述遮光层进行氧化处理，以在所述遮光层的表面形成绝缘膜；所述绝缘膜的材料为二氧化硅。
  14. 根据权9所述的阵列基板的制作方法，其中所述在所述第一金属层上形成第二绝缘层的步骤之后，所述方法还包括：
    在与所述公共电极对应的所述第二绝缘层上设置第三过孔，以使所述第二金属层与所述公共电极接触。
  15. 根据权14所述的阵列基板的制作方法，其中所述在所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上形成平坦层的步骤之前，所述方法还包括：
    在与所述公共电极对应处的第二金属层上形成第二透明导电层。
  16. 根据权9所述的阵列基板的制作方法，其中所述第一透明导电层包括像素电极。
  17. 一种阵列基板，其包括：
    缓冲层，位于衬底基板上；
    遮光层，位于所述缓冲层上；
    半导体层，位于所述遮光层上，所述半导体层用于形成沟道；
    第一绝缘层，位于所述半导体层上；
    第一金属层，位于所述第一绝缘层上，所述第一金属层包括薄膜晶体管的栅极区和公共电极区；
    第二绝缘层，位于所述第一金属层上；
    第二金属层，位于所述第二绝缘层上，所述第二金属层包括薄膜晶体管的漏极区和源极区；
    平坦层，位于所述第二金属层以及未被所述第二金属层覆盖的第二绝缘层上；所述平坦层上设置有第一过孔；以及
    第一透明导电层，位于所述平坦层上；所述第一透明导电层通过所述第一过孔与所述第二金属层连接。
  18. 根据权17所述的阵列基板，其中在与所述公共电极对应处的第二金属层上还设置有第二透明导电层。
  19. 根据权17所述的阵列基板，其中所述第一透明导电层包括像素电极。
  20. 根据权17所述的阵列基板，其中所述半导体层的材料为低温多晶硅。
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