WO2013116995A1 - 一种薄膜晶体管阵列基板及其制作方法 - Google Patents

一种薄膜晶体管阵列基板及其制作方法 Download PDF

Info

Publication number
WO2013116995A1
WO2013116995A1 PCT/CN2012/070951 CN2012070951W WO2013116995A1 WO 2013116995 A1 WO2013116995 A1 WO 2013116995A1 CN 2012070951 W CN2012070951 W CN 2012070951W WO 2013116995 A1 WO2013116995 A1 WO 2013116995A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal layer
transparent conductive
thin film
film transistor
Prior art date
Application number
PCT/CN2012/070951
Other languages
English (en)
French (fr)
Inventor
贾沛
杨流洋
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/502,136 priority Critical patent/US9379147B2/en
Publication of WO2013116995A1 publication Critical patent/WO2013116995A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of liquid crystal production technologies, and in particular, to a thin film transistor array substrate and a method of fabricating the same.
  • Boundary field switching technology Feringe Field Switching (FS) is increasingly used in the field of liquid crystal display due to its high transparency and large viewing angle.
  • TFT Thin Film Transistor
  • An object of the present invention is to provide a method for fabricating a thin film transistor array substrate, which solves the complicated process of forming a thin film transistor array substrate of an FFS liquid crystal display through a plurality of photomasks (such as four photomasks) in the prior art.
  • the difficulty and production cost are high, which increases the technical difficulty of the production difficulty of the liquid crystal display.
  • Another object of the present invention is to provide a thin film transistor array substrate, which solves the complicated process of forming a thin film transistor array substrate of an FFS liquid crystal display through a plurality of photomasks (such as four photomasks) in the prior art, and is difficult to manufacture.
  • the production cost is high, which increases the technical problem of the production difficulty of the liquid crystal display.
  • the invention provides a method for fabricating a thin film transistor array substrate, the method comprising the following steps:
  • a first transparent conductive layer and a first metal layer on the substrate by a sputtering method, and patterning the first transparent conductive layer and the first metal layer by using a first multi-stage adjustment mask to form a gate a pole and a common electrode, the gate includes a first transparent conductive layer and a first metal layer, and the common electrode is formed of a first transparent conductive layer;
  • a planarization layer is deposited on the pixel electrode and the source, drain, and semiconductor layers constituting the thin film transistor, and the planarization layer is formed of a transparent insulating material.
  • the first multi-stage adjustment mask and the second multi-section adjustment mask adopt a gray-scale tone mask, a stack layer mask or a halftone light. cover.
  • the gate insulating layer and the semiconductor layer are sequentially deposited by a chemical vapor deposition method.
  • the second transparent conductive layer and the second metal layer are sequentially deposited by a sputtering method.
  • the first metal layer is sequentially formed by a combination of a first aluminum metal layer and a first molybdenum metal layer
  • the second metal layer is sequentially composed of a second molybdenum metal layer, A two-aluminum metal layer and a third molybdenum metal layer are combined.
  • the first metal layer is mixed with a mixture of nitric acid, phosphoric acid, and acetic acid.
  • the wet etching is performed, and the first transparent conductive layer is wet etched using oxalic acid.
  • a mixture of nitric acid, phosphoric acid, and acetic acid is used in the process of forming the source, the drain, and the pixel electrode on the semiconductor layer by using the second multi-stage adjustment mask.
  • the second metal layer is wet etched, and the second transparent conductive layer is wet etched using oxalic acid.
  • Another object of the present invention is to provide a method for fabricating a thin film transistor array substrate, which solves the complicated process of forming a thin film transistor array substrate of an FFS liquid crystal display through a plurality of photomasks (such as four photomasks) in the prior art.
  • the difficulty in production and the high production cost increase the technical problems of the production difficulty of the liquid crystal display.
  • the present invention provides a method of fabricating a thin film transistor array substrate, the method comprising the following steps:
  • first transparent conductive layer and a first metal layer Depositing a first transparent conductive layer and a first metal layer on the substrate, and patterning the first transparent conductive layer and the first metal layer by using a first multi-stage adjustment mask to form a gate and a common electrode
  • the gate is formed by a combination of a first transparent conductive layer and a first metal layer
  • the common electrode is formed by a first transparent conductive layer
  • the method further includes the following steps:
  • a planarization layer is deposited on the pixel electrode and the source, drain, and semiconductor layers constituting the thin film transistor, and the planarization layer is formed of a transparent insulating material.
  • the first multi-stage adjustment mask and the second multi-section adjustment mask adopt a gray-scale tone mask, a stack layer mask or a halftone light. cover.
  • the first transparent conductive layer and the first metal layer are sequentially deposited by a sputtering method.
  • the gate insulating layer and the semiconductor layer are sequentially deposited by a chemical vapor deposition method.
  • the second transparent conductive layer and the second metal layer are sequentially deposited by a sputtering method.
  • the first metal layer is sequentially formed by a combination of a first aluminum metal layer and a first molybdenum metal layer
  • the second metal layer is sequentially composed of a second molybdenum metal layer, A two-aluminum metal layer and a third molybdenum metal layer are combined.
  • the first metal layer is mixed with a mixture of nitric acid, phosphoric acid, and acetic acid.
  • the wet etching is performed, and the first transparent conductive layer is wet etched using oxalic acid.
  • a mixture of nitric acid, phosphoric acid, and acetic acid is used in the process of forming the source, the drain, and the pixel electrode on the semiconductor layer by using the second multi-stage adjustment mask.
  • the second metal layer is wet etched, and the second transparent conductive layer is wet etched using oxalic acid.
  • Another object of the present invention is to provide a thin film transistor array substrate, which solves the complicated process of forming a thin film transistor array substrate of an FFS liquid crystal display through a plurality of photomasks (such as four photomasks) in the prior art, and is difficult to manufacture.
  • the production cost is high, which increases the technical problem of the production difficulty of the liquid crystal display.
  • the present invention provides a thin film transistor array substrate, the thin film transistor array substrate comprising:
  • each of the thin film transistors includes a gate, a gate insulating layer, a semiconductor layer, a source and a drain, the gate, the gate insulating layer, and the semiconductor a layer, the source and the drain are sequentially formed on the substrate;
  • the gate includes a first transparent conductive layer and a first metal layer, and the source and the drain comprise a second transparent conductive layer And a second metal layer;
  • a common electrode formed by a first transparent conductive layer on the substrate
  • a plurality of pixel electrodes are formed by a second transparent conductive layer on the gate insulating layer and connected to the drain of the thin film transistor.
  • the first metal layer is sequentially formed by a combination of a first aluminum metal layer and a first molybdenum metal layer
  • the second metal layer is sequentially composed of a second molybdenum metal layer and a second aluminum metal.
  • the layer and the third molybdenum metal layer are combined to form.
  • the first multi-stage adjustment mask process is performed, and the gate insulating layer and the semiconductor layer are continuously deposited on the substrate.
  • a second multi-stage adjustment mask process is performed to form the thin film transistor array substrate.
  • the invention manufactures the thin film transistor array substrate of the FFS type liquid crystal display through the three mask process, which simplifies the process, reduces the manufacturing difficulty and the manufacturing cost, and improves the output of the liquid crystal display.
  • FIG. 1 is a cross-sectional view of a display panel and a backlight module according to a preferred embodiment of the present invention
  • 2A-2E are schematic cross-sectional views showing a process of a thin film transistor array substrate of a display panel according to a preferred embodiment of the present invention.
  • FIG. 1 shows a cross-sectional view of a display panel and a backlight module according to an embodiment of the invention.
  • the method of manufacturing the thin film transistor (TFT) array substrate of the present embodiment can be applied to the display panel 10 In the manufacturing process of (for example, a liquid crystal display panel), a protective layer of a transistor is fabricated.
  • the liquid crystal display panel 10 can be disposed on the backlight module 20, thereby forming a liquid crystal display device.
  • the display panel 10 can include a first substrate 11 , a second substrate 12 , a liquid crystal layer 13 , a first polarizer 14 , and a second polarizer 15 .
  • the substrate material of the first substrate 11 and the second substrate 12 may be a glass substrate or a flexible plastic substrate.
  • the first substrate 11 may be, for example, a thin film transistor array substrate
  • the second substrate 12 may be, for example, colored. Filter (Color Filter, CF) substrate. It should be noted that in some embodiments, the color filter and the TFT matrix may also be disposed on the same substrate.
  • the liquid crystal layer 13 is formed between the first substrate 11 and the second substrate 12.
  • the first polarizer 14 is a side on which the first substrate 11 is disposed, and is opposite to the liquid crystal layer 13 (that is, the light incident side of the first substrate 11)
  • the second polarizer 15 is the side on which the second substrate 12 is disposed, and is opposite to the liquid crystal layer 13 (i.e., the light exiting side of the second substrate 12).
  • 2A-2E are schematic cross-sectional views showing a process of a thin film transistor array substrate of a display panel according to a preferred embodiment of the present invention.
  • a substrate 110 is provided on which a first transparent conductive layer 120 and a first metal layer 130 are sequentially deposited.
  • the first transparent conductive layer 120 is preferably formed using a transparent conductive metal such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium. Tin zinc oxide (ITZO).
  • a transparent conductive metal such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium. Tin zinc oxide (ITZO).
  • the first metal layer 130 is preferably composed of a combination of a first aluminum metal layer and a first molybdenum metal layer.
  • a first aluminum metal layer preferably composed of silver (Ag), copper (Cu), chromium (Cr), and tungsten (W) may also be used.
  • An alloy of tantalum (Ta), titanium (Ti), a metal nitride or any combination thereof may also be a multilayer structure having a heat resistant metal film and a low resistivity film.
  • the first transparent conductive layer 120 and the first metal layer 130 shown in FIG. 2A are patterned by using a first multi-stage adjustment mask to form a gate 140 and a common electrode 121, wherein the gate
  • the pole 140 includes a first transparent conductive layer 120 and a first metal layer 130, and the common electrode 121 is formed of a first transparent conductive layer 120.
  • the first transparent conductive layer 120 and the first metal layer 130 are sequentially formed on the substrate 110 by a sputtering method.
  • the gate 140 is then formed from the first transparent conductive layer 120 and the first metal layer 130 by a photolithography process and an etching process of the first multi-stage adjustment mask while being formed by the first transparent conductive layer 120.
  • the common electrode 121 may of course be formed by other deposition methods to form the first transparent conductive layer 120 and the first metal layer 130, which are not enumerated here.
  • the gate electrode 140 and the common electrode 121 in the first transparent conductive layer 120 and the first metal layer 130 by using the first multi-stage adjustment mask it is preferable to use nitric acid, phosphoric acid and acetic acid.
  • the first metal layer 130 is wet etched by the mixed solution, and the first transparent conductive layer 120 is wet etched using oxalic acid to form the shape of FIG. 2B.
  • the first multi-stage adjustment mask preferably uses a Gray Tone Mask (GTM), a Stacked Layer Mask (SLM) or a halftone mask (Half). Tone Mask, HTM), etc.
  • GTM Gray Tone Mask
  • SLM Stacked Layer Mask
  • Half halftone mask
  • the first multi-segment adjustment mask may include an exposed area, a partially exposed area, and an unexposed area, etc., so that the first transparent conductive layer 120 and the first metal layer 130 form the gate 140 while making The first transparent conductive layer 120 forms the common electrode 121.
  • the gate insulating layer 150 and the semiconductor layer 160 are sequentially deposited on the substrate 110.
  • the semiconductor layer 160 is patterned using a first mask to retain the semiconductor layer 160 over the gate 140 to form the structure shown in FIG. 2C.
  • the present invention preferably deposits the gate insulating layer 150 and the semiconductor layer 160 using chemical vapor deposition, such as plasma enhanced chemical vapor deposition (Plasma Enhanced). Chemical Vapor Deposition, PECVD), of course, the gate insulating layer 150 and the semiconductor layer 160 may be deposited by other means, which are not enumerated here.
  • chemical vapor deposition such as plasma enhanced chemical vapor deposition (Plasma Enhanced).
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer 150 and the semiconductor layer 160 may be deposited by other means, which are not enumerated here.
  • the material of the gate insulating layer 150 is, for example, silicon nitride (SiNx) or silicon oxide (SiOx), and the material of the semiconductor layer 160 is preferably polysilicon (Poly-Silicon).
  • the semiconductor layer 160 may first deposit an amorphous silicon (a-Si) layer, and then rapidly thermally anneal the amorphous silicon layer (Rapid). A thermal annealing, RTA) step of recrystallizing the amorphous silicon layer into a polysilicon layer.
  • the second transparent conductive layer 170 and the second metal layer 180 are formed by sequentially depositing on the substrate 110 by a sputtering method.
  • the thickness of the second transparent conductive layer 170 is preferably equal to or less than 100 micrometers ( ⁇ m), preferably formed using a transparent conductive metal such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO). ) and indium tin zinc oxide (ITZO).
  • a transparent conductive metal such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO).
  • ITZO indium tin zinc oxide
  • the second metal layer 180 is sequentially formed by a combination of a second molybdenum metal layer, a second aluminum metal layer, and a third molybdenum metal layer.
  • a second molybdenum metal layer e.g., silver (Ag), copper (Cu), or the like
  • other materials such as silver (Ag), copper (Cu), or the like may also be used.
  • the alloy of chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), metal nitride or any combination thereof may also be a multilayer structure having a heat resistant metal film and a low resistivity film.
  • the second transparent conductive layer 170 and the second metal layer 180 are patterned by using a second multi-stage adjustment mask, and the second transparent conductive layer 170 and the first layer are formed on the semiconductor layer 160.
  • the source electrode 191 and the drain electrode 192 of the two metal layer 180 form the pixel electrode 171 on the gate insulating layer 150 from the second transparent conductive layer 170.
  • the second multi-stage adjustment mask preferably adopts a Gray Tone Mask (GTM), a Stacked Layer Mask (SLM) or a halftone mask (Half). Tone Mask, HTM), etc.
  • the second multi-stage adjustment mask may include an exposed area, a partially exposed area, and an unexposed area, etc., such that the second transparent conductive layer 170 and the second metal layer 180 form the source 191 and the drain 192.
  • the second transparent conductive layer 170 is formed to form the pixel electrode 171.
  • the pixel electrode 171 is connected to the drain electrode 192 , and the common electrode 121 is separated from the pixel electrode 171 by the gate insulating layer 150 .
  • the source 191 and the drain 192 including the second transparent conductive layer 170 and the second metal layer 180 are formed on the semiconductor layer 160 by using the second multi-stage adjustment mask, and the gate insulating layer 150 is disposed on the gate insulating layer 150.
  • the second metal layer 180 is preferably wet-etched using a mixed solution of nitric acid, phosphoric acid, and acetic acid, and the second transparent conductive layer 170 is used using oxalic acid. Wet etching is performed.
  • a planarization layer (not shown) may be deposited on the pixel electrode 171, the source 191 constituting the thin film transistor, the drain 192, and the semiconductor layer 160. Achieve flatness and protect components.
  • the planarization layer is formed of a transparent insulating material, and may of course be other materials, which are not enumerated here.
  • the present invention also provides a thin film transistor array substrate including a substrate 110 and a common electrode 121 and a plurality of thin film transistors disposed on the substrate 110.
  • the thin film transistor includes a gate 140, a gate insulating layer 150, a semiconductor layer 160, a source 191, and a drain 192.
  • the gate 140, the gate insulating layer 150, the semiconductor layer 160, the source 191 and the drain 192 are sequentially formed on the substrate 110; the gate 140 includes a first transparent
  • the conductive layer 120 and the first metal layer 130, the source 191 and the drain 192 include a second transparent conductive layer 170 and a second metal layer 180.
  • the common electrode 121 is formed by the first transparent conductive layer 120 on the substrate 110.
  • the thin film transistor array substrate further includes a pixel electrode 171 formed by a second transparent conductive layer 170 on the gate insulating layer 150 corresponding to the common electrode 121, and the drain of the thin film transistor 192 is connected, and the pixel electrode 171 includes a plurality of electrode blocks.
  • the photomask process is repeated in accordance with the steps of preparing the semiconductor layer, preparing the source and drain of the thin film transistor, and preparing the pixel electrode, and fabricating the thin film transistor array substrate, the thin film transistor array substrate and the display panel of the present invention.
  • the manufacturing method is mainly: after sequentially depositing the first transparent conductive layer and the first metal layer on the substrate, forming a gate (formed by the first transparent conductive layer and the first metal layer) and common through the first multi-stage adjustment mask An electrode (formed by the first transparent conductive layer), after the step of preparing the semiconductor layer by the first mask is completed, directly depositing the second transparent conductive layer and the second metal layer, and then using the second multi-stage adjustment mask And forming a source and a drain of the thin film transistor (all composed of the second transparent conductive layer and the second metal layer) and a pixel electrode (formed by the second transparent conductive layer), therefore, the overall process requires only three masks to complete the FFS
  • the thin film transistor array substrate of the liquid crystal display can reduce the number of masks required for the process, thereby reducing the process cost and time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明公开了一种薄膜晶体管阵列基板及其制作方法，在基板上沉积第一透明导电层和第一金属层后利用第一多段式调整光罩形成栅极和共通电极；继续沉积栅绝缘层和半导体层后利用第一光罩保留栅极上方的半导体层；继续沉积第二透明导电层和第二金属层，利用第二多段式调整光罩形成源极、漏极和像素电极。

Description

一种薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及液晶生产技术领域，特别涉及一种薄膜晶体管阵列基板及其制作方法。
 背景技术
随着液晶显示器的不断推广和普及，对液晶显示器的显示性能提出了很高的要求。边界电场切换技术(Fringe Field Switching，FFS)由于具有高穿透性以及大视角的特征，被越来越多地应用在液晶显示领域。
在液晶显示器的薄膜晶体管(Thin Film Transistor，TFT) 阵列基板制程中，需使用多道光罩来进行光刻制程(Photo-lithography)，然而，光罩相当昂贵，光罩次数越多则薄膜晶体管制程所需的成本越高，且增加制程时间及复杂度。
同样地，现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度。
故，有必要提供一种薄膜晶体管阵列基板及其制造方法，以解决现有技术所存在的问题。
 技术问题
本发明的一个目的在于提供一种薄膜晶体管阵列基板的制作方法，以解决现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
本发明的又一个目的在于提供一种薄膜晶体管阵列基板，以解决现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
 技术解决方案
本发明提供了一种薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：
提供基板；
在所述基板上通过溅射法依次沉积第一透明导电层和第一金属层，利用第一多段式调整光罩对所述第一透明导电层和第一金属层进行图案化，形成栅极和共通电极，所述栅极包括第一透明导电层和第一金属层，所述共通电极由第一透明导电层形成；
在所述基板上继续沉积栅绝缘层和半导体层，利用第一光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
在所述基板上继续沉积第二透明导电层和第二金属层，利用第二多段式调整光罩来图案化第二透明导电层和第二金属层，在半导体层上形成包括第二透明导电层和第二金属层的源极和漏极，在所述共通电极对应的栅绝缘层上由所述第二透明导电层形成像素电极；
在所述像素电极、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第一多段式调整光罩和所述第二多段式调整光罩采用灰阶色调光罩、堆栈图层光罩或半色调光罩。
在本发明的薄膜晶体管阵列基板的制作方法中，所述栅绝缘层和所述半导体层通过化学气相沉积法依次沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第二透明导电层和所述第二金属层通过溅射法依次沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
在本发明的薄膜晶体管阵列基板的制作方法中，利用所述第一多段式调整光罩形成栅极及共通电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述第一透明导电层进行湿法刻蚀。
在本发明的薄膜晶体管阵列基板的制作方法中，利用所述第二多段式调整光罩在半导体层上形成源极、漏极以及像素电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，使用草酸对所述第二透明导电层进行湿法刻蚀。
本发明的另一个目的在于提供一种薄膜晶体管阵列基板的制作方法，以解决现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
为解决上述问题，本发明提供了一种薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：
提供基板；
在所述基板上依次沉积第一透明导电层和第一金属层，利用第一多段式调整光罩对所述第一透明导电层和第一金属层进行图案化，形成栅极和共通电极，所述栅极由第一透明导电层和第一金属层组合形成，所述共通电极由第一透明导电层形成；
在所述基板上继续沉积栅绝缘层和半导体层，利用第一光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
在所述基板上继续沉积第二透明导电层和第二金属层，利用第二多段式调整光罩来图案化第二透明导电层和第二金属层，在半导体层上形成包括第二透明导电层和第二金属层的源极和漏极，在所述共通电极对应的栅绝缘层上由所述第二透明导电层形成像素电极。
在本发明的薄膜晶体管阵列基板的制作方法中，在形成所述源极、漏极和像素电极后，所述方法还包括以下步骤：
在所述像素电极、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第一多段式调整光罩和所述第二多段式调整光罩采用灰阶色调光罩、堆栈图层光罩或半色调光罩。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第一透明导电层和所述第一金属层通过溅射法依次沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述栅绝缘层和所述半导体层通过化学气相沉积法依次沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第二透明导电层和所述第二金属层通过溅射法依次沉积形成。
在本发明的薄膜晶体管阵列基板的制作方法中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
在本发明的薄膜晶体管阵列基板的制作方法中，利用所述第一多段式调整光罩形成栅极及共通电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述第一透明导电层进行湿法刻蚀。
在本发明的薄膜晶体管阵列基板的制作方法中，利用所述第二多段式调整光罩在半导体层上形成源极、漏极以及像素电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，使用草酸对所述第二透明导电层进行湿法刻蚀。
本发明的又一个目的在于提供一种薄膜晶体管阵列基板，以解决现有技术中通过多道光罩（譬如四道光罩）形成FFS型液晶显示器的薄膜晶体管阵列基板的工艺制程较为复杂，制作难度和制作成本较高，增加了液晶显示器的生产难度的技术问题。
为解决上述问题，本发明提供了一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
基板；
多个薄膜晶体管，设置于所述基板上，其中每一所述薄膜晶体管包括栅极、栅绝缘层、半导体层、源极及漏极，所述栅极、所述栅绝缘层、所述半导体层、所述源极及漏极是依序形成于所述基板上；所述栅极包括第一透明导电层和第一金属层，所述源极及所述漏极包括第二透明导电层和第二金属层；
共通电极，由所述基板上的第一透明导电层形成；
多个像素电极，由所述栅绝缘层上的第二透明导电层形成，并与所述薄膜晶体管的所述漏极连接。
在本发明的薄膜晶体管阵列基板中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
 有益效果
本发明相对于现有技术，通过基板上依次沉积第一透明导电层和第一金属层后进行第一多段式调整光罩制程，在基板上继续沉积栅绝缘层和半导体层后进行第一光罩制程，在基板上继续沉积第二透明导电层和第二金属层后进行第二多段式调整光罩制程形成薄膜晶体管阵列基板。显然，本发明通过三道光罩制程制作FFS型液晶显示器的薄膜晶体管阵列基板，简化了工艺制程，降低了制作难度以及制作成本，提高了液晶显示器的产量。
 附图说明
图1为本发明的一较佳实施例的显示面板与背光模块的剖面示意图；
图2A-图2E为本发明的一较佳实施例的显示面板的薄膜晶体管阵列基板的制程剖面示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，其显示依照本发明的一实施例的显示面板与背光模块的剖面示意图。本实施例的薄膜晶体管(TFT)阵列基板的制造方法可应用于显示面板10 (例如液晶显示面板)的制造过程中，以制造晶体管的保护层。当应用本实施例的显示面板10来制造一液晶显示装置时，可设置液晶显示面板10于背光模块20上，因而形成液晶显示装置。此显示面板10可包括第一基板11、第二基板12、液晶层13、第一偏光片14及第二偏光片15。第一基板11和第二基板12的基板材料可为玻璃基板或可挠性塑料基板，在本实施例中，第一基板11可例如为薄膜晶体管阵列基板，而第二基板12可例如为彩色滤光片(Color Filter，CF)基板。值得注意的是，在一些实施例中，彩色滤光片和TFT矩阵亦可配置在同一基板上。
如图1所示，液晶层13是形成于第一基板11与第二基板12之间。第一偏光片14是设置第一基板11的一侧，并相对于液晶层13 (即第一基板11的入光侧)，第二偏光片15是设置第二基板12的一侧，并相对于液晶层13 (即第二基板12的出光侧)。
图2A-2E为本发明的一较佳实施例的显示面板的薄膜晶体管阵列基板的制程剖面示意图。
在图2A中，提供基板110，在所述基板110上依次沉积第一透明导电层120和第一金属层130。
在本实施例中，所述第一透明导电层120优选使用透明导电金属形成，该透明导电金属譬如铟锡氧化物（ITO）、锡氧化物（TO）、铟锌氧化物（IZO）以及铟锡锌氧化物（ITZO）。
所述第一金属层130优选由第一铝金属层和第一钼金属层组合构成，当然也可以使用其它材料，譬如银（Ag）、铜（Cu）、铬（Cr）、钨（W）、钽（Ta）、钛（Ti）、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构。
在图2B中，利用第一多段式调整光罩对图2A所示的第一透明导电层120和第一金属层130进行图案化处理形成栅极140和共通电极121，其中，所述栅极140包括第一透明导电层120和第一金属层130，所述共通电极121由第一透明导电层120形成。
在具体实施过程中，优选采用溅射法在基板110依次形成所述第一透明导电层120和第一金属层130。之后通过第一多段式调整光罩的光刻程序和蚀刻程序由所述第一透明导电层120和第一金属层130形成所述栅极140，同时由所述第一透明导电层120形成共通电极121，当然也可以是其它的沉积方法形成所述第一透明导电层120和所述第一金属层130，此处不一一列举。
其中，通过第一多段式调整光罩在所述第一透明导电层120和所述第一金属层130形成所述栅极140及共通电极121的过程中，优选使用硝酸、磷酸以及醋酸的混合液对所述第一金属层130进行湿法刻蚀，使用草酸对所述第一透明导电层120进行湿法刻蚀，形成图2B的形状。
在具体实施过程中，所述第一多段式调整光罩优选采用灰阶色调光罩(Gray Tone Mask，GTM)、堆栈图层光罩(Stacked Layer Mask，SLM)或半色调光罩(Half Tone Mask，HTM)等。所述第一多段式调整光罩可包括曝光区域、部分曝光区域以及未曝光区域等，籍以使所述第一透明导电层120和第一金属层130形成所述栅极140，同时使所述第一透明导电层120形成所述共通电极121。
请参阅图2C，继续在所述基板110上依次沉积栅绝缘层150和半导体层160。利用第一光罩对所述半导体层160进行图案化，保留位于所述栅极140上方的半导体层160，形成图2C所示的结构。
本发明优选使用化学气相沉积法沉积所述栅绝缘层150和所述半导体层160，譬如等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition, PECVD)方式，当然还可以通过其它方式沉积所述栅绝缘层150和所述半导体层160，此处不一一列举。
所述栅绝缘层150的材料例如为氮化硅(SiNx)或氧化硅(SiOx)，所述半导体层160的材料优选为多晶硅(Poly-Silicon)。在本实施例中，所述半导体层160可先沉积一非晶硅(a-Si)层，接着，对该非晶硅层进行快速热退火(Rapid thermal annealing, RTA)步骤，藉以使该非晶硅层再结晶成一多晶硅层。
请参阅图2D， 继续在所述基板110上通过溅射法依次沉积形成第二透明导电层170和第二金属层180。
所述第二透明导电层170的厚度优选是等于或小于100微米（μm），优选使用透明导电金属形成，譬如铟锡氧化物（ITO）、锡氧化物（TO）、铟锌氧化物（IZO）以及铟锡锌氧化物（ITZO）。
优选的，所述第二金属层180依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成，当然也可以使用其它材料，譬如银（Ag）、铜（Cu）、铬（Cr）、钨（W）、钽（Ta）、钛（Ti）、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构。
请参阅图2E，利用第二多段式调整光罩对所述第二透明导电层170和第二金属层180进行图案化，在半导体层160上形成包括所述第二透明导电层170和第二金属层180的源极191及漏极192，在栅绝缘层150上由所述第二透明导电层170形成像素电极171。
在具体实施过程中，所述第二多段式调整光罩优选采用灰阶色调光罩(Gray Tone Mask，GTM)、堆栈图层光罩(Stacked Layer Mask，SLM)或半色调光罩(Half Tone Mask，HTM)等。所述第二多段式调整光罩可包括曝光区域、部分曝光区域以及未曝光区域等，籍以使所述第二透明导电层170和第二金属层180形成所述源极191和漏极192，使所述第二透明导电层170形成所述像素电极171。其中，所述像素电极171连接所述漏极192，所述共通电极121通过所述栅绝缘层150与所述像素电极171隔开。
其中，利用第二多段式调整光罩在半导体层160上形成包括所述第二透明导电层170和第二金属层180的源极191和漏极192、以及在栅绝缘层150上由所述第二透明导电层170形成像素电极171的过程中，优选使用硝酸、磷酸以及醋酸的混合液对所述第二金属层180进行湿法刻蚀，使用草酸对所述第二透明导电层170进行湿法刻蚀。
在一实施例中，在形成图2E所示结构后，可在像素电极171、构成薄膜晶体管的源极191、漏极192和半导体层160上沉积一平坦化层（图未示出），以达到平坦化及保护组件的功效。优选的，所述平坦化层由透明绝缘材质形成，当然也可以为其它材质，此处不一一列举。
本发明还提供一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括基板110以及设置在所述基板110上的共通电极121和多个薄膜晶体管。
所述薄膜晶体管包括栅极140、栅绝缘层150、半导体层160、源极191及漏极192。其中，所述栅极140、所述栅绝缘层150、所述半导体层160、所述源极191及漏极192是依序形成于所述基板110上；所述栅极140包括第一透明导电层120和第一金属层130，所述源极191及所述漏极192包括第二透明导电层170和第二金属层180。
其中，所述共通电极121由所述基板110上的第一透明导电层120形成。所述薄膜晶体管阵列基板还包括像素电极171，所述像素电极171由所述共通电极121对应的栅绝缘层150上的第二透明导电层170形成，并与所述薄膜晶体管的所述漏极192连接，所述像素电极171包含多个电极区块。
相较于一般传统技术是依照制备半导体层、制备薄膜晶体管的源极与漏极以及制备像素电极的顺序来重复进行光罩工序，制作薄膜晶体管阵列基板，本发明的薄膜晶体管阵列基板及显示面板的制造方法主要是在基板上依次沉积第一透明导电层和第一金属层后，通过第一多段式调整光罩形成栅极（由第一透明导电层和第一金属层形成）和共通电极（由第一透明导电层形成），在通过第一光罩制备半导体层的步骤完成之后，直接先行沉积第二透明导电层和第二金属层，再利用第二多段式调整光罩一并形成薄膜晶体管的源极、漏极(皆由第二透明导电层和第二金属层组成)以及像素电极(由第二透明导电层形成)，因此，整体制程仅需三道光罩来完成FFS型液晶显示器的薄膜晶体管阵列基板，因而可减少制程所需的光罩数，进而减少制程成本及时间。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (18)

  1. 一种薄膜晶体管阵列基板的制作方法，其中，所述方法包括以下步骤：
    提供基板；
    在所述基板上通过溅射法依次沉积第一透明导电层和第一金属层，利用第一多段式调整光罩对所述第一透明导电层和第一金属层进行图案化，形成栅极和共通电极，所述栅极包括第一透明导电层和第一金属层，所述共通电极由第一透明导电层形成；
    在所述基板上继续沉积栅绝缘层和半导体层，利用第一光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
    在所述基板上继续沉积第二透明导电层和第二金属层，利用第二多段式调整光罩来图案化第二透明导电层和第二金属层，在半导体层上形成包括第二透明导电层和第二金属层的源极和漏极，在所述共通电极对应的栅绝缘层上由所述第二透明导电层形成像素电极；
    在所述像素电极、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
  2. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，所述第一多段式调整光罩和所述第二多段式调整光罩采用灰阶色调光罩、堆栈图层光罩或半色调光罩。
  3. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，所述栅绝缘层和所述半导体层通过化学气相沉积法依次沉积形成。
  4. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，所述第二透明导电层和所述第二金属层通过溅射法依次沉积形成。
  5. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
  6. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，利用所述第一多段式调整光罩形成栅极及共通电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述第一透明导电层进行湿法刻蚀。
  7. 根据权利要求1所述的薄膜晶体管阵列基板的制作方法，其中，利用所述第二多段式调整光罩在半导体层上形成源极、漏极以及像素电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，使用草酸对所述第二透明导电层进行湿法刻蚀。
  8. 一种薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：
    提供基板；
    在所述基板上依次沉积第一透明导电层和第一金属层，利用第一多段式调整光罩对所述第一透明导电层和第一金属层进行图案化，形成栅极和共通电极，所述栅极包括第一透明导电层和第一金属层，所述共通电极由第一透明导电层形成；
    在所述基板上继续沉积栅绝缘层和半导体层，利用第一光罩对所述半导体层进行图案化，保留位于所述栅极上方的半导体层；
    在所述基板上继续沉积第二透明导电层和第二金属层，利用第二多段式调整光罩来图案化第二透明导电层和第二金属层，在半导体层上形成包括第二透明导电层和第二金属层的源极和漏极，在所述共通电极对应的栅绝缘层上由所述第二透明导电层形成像素电极。
  9. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，在形成所述源极、漏极和像素电极后，所述方法还包括以下步骤：
    在所述像素电极、以及构成薄膜晶体管的所述源极、漏极和半导体层上沉积一平坦化层，所述平坦化层由透明绝缘材质形成。
  10. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述第一多段式调整光罩和所述第二多段式调整光罩采用灰阶色调光罩、堆栈图层光罩或半色调光罩。
  11. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述第一透明导电层和所述第一金属层通过溅射法依次沉积形成。
  12. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述栅绝缘层和所述半导体层通过化学气相沉积法依次沉积形成。
  13. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述第二透明导电层和所述第二金属层通过溅射法依次沉积形成。
  14. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
  15. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，利用所述第一多段式调整光罩形成栅极及共通电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀，使用草酸对所述第一透明导电层进行湿法刻蚀。
  16. 根据权利要求8所述的薄膜晶体管阵列基板的制作方法，其中，利用所述第二多段式调整光罩在半导体层上形成源极、漏极以及像素电极的过程中，使用硝酸、磷酸以及醋酸的混合液对所述第二金属层进行湿法刻蚀，使用草酸对所述第二透明导电层进行湿法刻蚀。
  17. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    基板；
    多个薄膜晶体管，设置于所述基板上，其中每一所述薄膜晶体管包括栅极、栅绝缘层、半导体层、源极及漏极，所述栅极、所述栅绝缘层、所述半导体层、所述源极及漏极是依序形成于所述基板上；所述栅极包括第一透明导电层和第一金属层，所述源极及所述漏极包括第二透明导电层和第二金属层；
    共通电极，由所述基板上的第一透明导电层形成；
    多个像素电极，由所述栅绝缘层上的第二透明导电层形成，并与所述薄膜晶体管的所述漏极连接。
  18. 根据权利要求17所述的薄膜晶体管阵列基板，其中，所述第一金属层依次由第一铝金属层和第一钼金属层组合形成，所述第二金属层依次由第二钼金属层、第二铝金属层以及第三钼金属层组合形成。
PCT/CN2012/070951 2012-02-07 2012-02-08 一种薄膜晶体管阵列基板及其制作方法 WO2013116995A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/502,136 US9379147B2 (en) 2012-02-07 2012-02-08 Thin-film transistor array substrate and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2012100258654A CN102544029A (zh) 2012-02-07 2012-02-07 一种薄膜晶体管阵列基板及其制作方法
CN201210025865.4 2012-02-07

Publications (1)

Publication Number Publication Date
WO2013116995A1 true WO2013116995A1 (zh) 2013-08-15

Family

ID=46350507

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/070951 WO2013116995A1 (zh) 2012-02-07 2012-02-08 一种薄膜晶体管阵列基板及其制作方法

Country Status (3)

Country Link
US (1) US9379147B2 (zh)
CN (1) CN102544029A (zh)
WO (1) WO2013116995A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102629059B (zh) 2012-01-31 2015-05-27 京东方科技集团股份有限公司 阵列基板及制造方法、液晶面板和液晶显示器
CN102769040B (zh) * 2012-07-25 2015-03-04 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制作方法、显示装置
CN102881688B (zh) * 2012-09-19 2015-04-15 北京京东方光电科技有限公司 一种阵列基板、显示面板及阵列基板的制造方法
CN103219341B (zh) * 2013-04-03 2016-08-31 北京京东方光电科技有限公司 一种阵列基板及制备方法、显示装置
CN107768386B (zh) * 2017-11-16 2020-09-01 深圳市华星光电半导体显示技术有限公司 Tft阵列基板及其制作方法以及液晶显示面板
CN108054140B (zh) * 2017-12-06 2020-11-06 深圳市华星光电技术有限公司 Ffs模式阵列基板的制造方法
CN109616443A (zh) * 2018-11-07 2019-04-12 深圳市华星光电半导体显示技术有限公司 阵列基板的制作方法及阵列基板
CN112038221A (zh) * 2020-09-17 2020-12-04 深圳市洁简达创新科技有限公司 一种堆叠态半导体芯片结构及其工艺方法
CN114935857A (zh) * 2022-04-21 2022-08-23 广州华星光电半导体显示技术有限公司 一种显示面板及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101419945A (zh) * 2007-10-23 2009-04-29 株式会社半导体能源研究所 半导体装置的制造方法
CN101527282A (zh) * 2007-12-03 2009-09-09 株式会社半导体能源研究所 半导体装置的制造方法
CN102280408A (zh) * 2011-06-28 2011-12-14 深圳市华星光电技术有限公司 薄膜晶体管矩阵基板及显示面板的制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4920140B2 (ja) * 2001-05-18 2012-04-18 ゲットナー・ファンデーション・エルエルシー 液晶表示装置及びその製造方法
KR101125254B1 (ko) * 2004-12-31 2012-03-21 엘지디스플레이 주식회사 프린지 필드 스위칭 타입의 박막 트랜지스터 기판 및 그제조 방법과, 그를 이용한 액정 패널 및 그 제조 방법
KR101167304B1 (ko) * 2004-12-31 2012-07-19 엘지디스플레이 주식회사 프린지 필드 스위칭 타입의 박막 트랜지스터 기판 및 그제조 방법
CN100483232C (zh) * 2006-05-23 2009-04-29 北京京东方光电科技有限公司 一种tft lcd阵列基板结构及其制造方法
US7847904B2 (en) * 2006-06-02 2010-12-07 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic appliance
US8357937B2 (en) * 2006-12-19 2013-01-22 Lg Display Co., Ltd. Thin film transistor liquid crystal display device
US20090079920A1 (en) * 2007-09-20 2009-03-26 Mitsubishi Electric Corporation Display device and method of manufacturing the same
KR101058461B1 (ko) * 2007-10-17 2011-08-24 엘지디스플레이 주식회사 횡전계형 액정표시장치용 어레이 기판 및 그의 제조방법
US9041202B2 (en) * 2008-05-16 2015-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
CN101807550B (zh) * 2009-02-18 2013-05-22 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
CN102148195B (zh) * 2010-04-26 2013-05-01 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
KR101361925B1 (ko) * 2010-07-07 2014-02-21 엘지디스플레이 주식회사 저저항배선 구조를 갖는 박막 트랜지스터 기판 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101419945A (zh) * 2007-10-23 2009-04-29 株式会社半导体能源研究所 半导体装置的制造方法
CN101527282A (zh) * 2007-12-03 2009-09-09 株式会社半导体能源研究所 半导体装置的制造方法
CN102280408A (zh) * 2011-06-28 2011-12-14 深圳市华星光电技术有限公司 薄膜晶体管矩阵基板及显示面板的制造方法

Also Published As

Publication number Publication date
US20150243691A1 (en) 2015-08-27
CN102544029A (zh) 2012-07-04
US9379147B2 (en) 2016-06-28

Similar Documents

Publication Publication Date Title
WO2013116992A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2013116995A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2013116994A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
WO2017128565A1 (zh) 低温多晶硅阵列基板的制作方法
WO2013071800A1 (zh) 显示装置、薄膜晶体管、阵列基板及其制造方法
US11087985B2 (en) Manufacturing method of TFT array substrate
WO2014012334A1 (zh) 阵列基板的制造方法及阵列基板、显示装置
WO2014206035A1 (zh) 阵列基板及其制作方法、显示面板和显示装置
KR101900170B1 (ko) 어레이 기판의 제조 방법, 어레이 기판 및 디스플레이 디바이스
JPS60103676A (ja) 薄膜トランジスタアレイの製造方法
WO2013013438A1 (zh) 储存电容架构及其制造方法与像素结构
WO2014166181A1 (zh) 薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置
WO2013131384A1 (zh) 薄膜晶体管阵列基板及其制造方法和电子器件
WO2016045238A1 (zh) 阵列基板及其制作方法、液晶显示装置
WO2013086909A1 (zh) 阵列基板及其制造方法、显示装置
WO2019095482A1 (zh) Tft基板及其制作方法
WO2019047357A1 (zh) 一种oled显示面板及其制程
WO2013166668A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2017020322A1 (zh) 一种ffs阵列基板及其制造方法和显示装置
TW200824125A (en) TFT substrate and method of fabricating the same
WO2016090690A1 (zh) 一种ltps像素单元及其制造方法
WO2019210776A1 (zh) 阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法
WO2013020322A1 (zh) 薄膜晶体管矩阵基板及显示面板的制造方法
WO2013159396A1 (zh) 一种薄膜晶体管阵列基板及其制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13502136

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12867775

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12867775

Country of ref document: EP

Kind code of ref document: A1