WO2019047357A1 - 一种oled显示面板及其制程 - Google Patents

一种oled显示面板及其制程 Download PDF

Info

Publication number
WO2019047357A1
WO2019047357A1 PCT/CN2017/109534 CN2017109534W WO2019047357A1 WO 2019047357 A1 WO2019047357 A1 WO 2019047357A1 CN 2017109534 W CN2017109534 W CN 2017109534W WO 2019047357 A1 WO2019047357 A1 WO 2019047357A1
Authority
WO
WIPO (PCT)
Prior art keywords
multilayer film
film
layer
display panel
auxiliary electrode
Prior art date
Application number
PCT/CN2017/109534
Other languages
English (en)
French (fr)
Inventor
张良芬
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/574,538 priority Critical patent/US10388707B2/en
Publication of WO2019047357A1 publication Critical patent/WO2019047357A1/zh
Priority to US16/460,741 priority patent/US10593740B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a control method for a display panel and a display panel gate signal.
  • the existing display panel mainly includes liquid crystal (Liquid Crystal) Display, LCD) display panel and OLED (Organic Light Emitting Diode, OLED) display panel.
  • the OLED display panel has self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180° viewing angle, wide temperature range, flexible display and large-area full-color display. It is recognized by the industry as the most promising display panel. With the improvement of the process and process of OLED display panels and the reduction of cost, OLED TVs have become popular and more recognized and accepted by more people.
  • OLEDs have advantages over the display characteristics and quality of LCDs, such as thinness and lightness, short reaction time, low display voltage, better display color, and display angle of view, they have received widespread attention, and their development has been changing with each passing day. Not only can the surface display be produced, but also gradually develop to a large size. But large size still exists IR Drop Issue, even visually visible Mura, so the auxiliary electrode and the cathode isolation column are fabricated on the process, and the cathode is isolated to achieve separate control of the cathode, thereby reducing IR Drop issues to improve display issues.
  • the conventional cathode isolation column is fabricated by organic photoresist coating, exposure and development, and forms an inverted trapezoid by controlling process parameters; the stability is poor.
  • the object of the present invention is to provide a display panel and a process thereof, which solve the problem that the stability of the conventional cathode isolation column is not good.
  • the manufacturing process of the display panel provided by the present invention adopts the following technical solutions:
  • a process for displaying a panel comprising the steps of:
  • the coating photoresist on the multilayer film is removed to form an inverted trapezoidal cathode isolation column.
  • the step of sequentially depositing a plurality of thin films on the auxiliary electrode layer comprises:
  • the step of sequentially depositing a plurality of thin films on the auxiliary electrode layer comprises:
  • a multilayer film is deposited in multiple steps on the auxiliary electrode layer.
  • one or more gases of SiNx, N2, NH3, TEOS, and N2O are introduced during the process.
  • the auxiliary electrode is formed of one or more of ITO, Mo, AL, Ti, Cu, and alloys thereof.
  • the planarization layer is a film formed by chemical vapor deposition deposition.
  • a process for displaying a panel comprising the steps of:
  • the coating photoresist on the multilayer film is removed to form an inverted trapezoidal cathode isolation column.
  • the density of the single-layer film in the multilayer film is gradually increased from the bottom to the top, including:
  • the multilayer film includes at least three films, and the difference in density of adjacent films in the multilayer film gradually increases from bottom to top.
  • the density of the single-layer film in the multilayer film is gradually increased from the bottom to the top, including:
  • the multilayer film includes at least three films, and the difference in density of adjacent films in the multilayer film gradually decreases from bottom to top.
  • auxiliary electrode layer sequentially deposited on the auxiliary electrode layer, including:
  • a multilayer film is sequentially deposited on the auxiliary electrode layer by chemical vapor deposition.
  • the step of sequentially depositing a plurality of thin films on the auxiliary electrode layer comprises:
  • the step of sequentially depositing a plurality of thin films on the auxiliary electrode layer comprises:
  • a multilayer film is deposited in multiple steps on the auxiliary electrode layer.
  • one or more gases of SiNx, N2, NH3, TEOS, and N2O are introduced during the process.
  • the auxiliary electrode is formed of one or more of ITO, Mo, AL, Ti, Cu, and alloys thereof.
  • the planarization layer is a film formed by chemical vapor deposition deposition.
  • a display panel comprising:
  • the cathode separation column comprising a multilayer film, wherein a density of the single layer film in the multilayer film is gradually increased from bottom to top, in the multilayer film The width of the single layer film gradually increases from the bottom to the top, and the cathode separator column has an inverted trapezoidal shape.
  • the multilayer film includes at least three films, and the difference in density of adjacent films in the multilayer film gradually increases from the bottom to the top.
  • the multilayer film includes at least three films, and the difference in density of adjacent films in the multilayer film gradually decreases from the bottom to the top.
  • the auxiliary electrode is formed of one or more of ITO, Mo, AL, Ti, Cu, and alloys thereof.
  • the planarization layer is a thin film formed by chemical vapor deposition deposition.
  • the invention has the beneficial effects that a cathode separation column is formed by using a film having different layers of compactness, and the density of the multilayer film is gradually increased from the bottom to the top, and finally dry etching is performed due to the characteristics of the film.
  • Trapezoidal cathode isolation column The cathode isolating column formed in this manner has the characteristics of good process stability, good uniformity of the large plate, and is not easily detached from the substrate in the subsequent process.
  • the process of making the inverted trapezoidal cathode isolation column is simplified, and the efficiency is improved.
  • Figure 1 is a schematic view showing the formation of a conventional cathode isolation column
  • FIG. 2 is a flow chart of a process of a display panel according to an embodiment of the present invention.
  • FIG. 3 is a schematic view showing a step 1-3 of forming a cathode isolation column according to an embodiment of the present invention
  • FIG. 4 is a schematic view showing a step 4-7 of forming a cathode isolation column according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a display panel according to an embodiment of the present invention.
  • FIGS. 1 through 5 A display panel and a process thereof according to an embodiment of the present invention are described below with reference to FIGS. 1 through 5.
  • FIG. 1 is a schematic view showing the formation of a conventional cathode isolation column
  • FIG. 2 is a flow chart of a process for displaying a panel according to an embodiment of the present invention
  • FIG. 3 is a cathode isolation method according to an embodiment of the present invention.
  • FIG. 4 is a schematic view showing a step 4-7 of forming a cathode isolation column according to an embodiment of the present invention
  • FIG. 5 is a schematic view showing a display panel according to an embodiment of the present invention.
  • the conventional cathode isolation column fabrication process includes:
  • a substrate 110 is provided.
  • the substrate 110 is provided with a fabricated TFT device (not shown), and the substrate 110 is provided with an auxiliary electrode 120.
  • step 2 a layer of photoresist 130 is applied over the auxiliary electrode 120.
  • step 3 the substrate coated with the photoresist 130 is exposed.
  • step 4 development is performed and an inverted trapezoidal cathode isolation column 141 is formed.
  • an embodiment of the present invention discloses a process for displaying a display panel, and the process of the display panel includes steps S101-S108.
  • the substrate layer can be low temperature polysilicon (LTPS, low temperature) Poly-silicon) substrate.
  • LTPS low temperature polysilicon
  • a glass substrate, a resin substrate, or the like may be used. It can also be any TFT such as Oxide TFT or SPC.
  • S102 Form a thin film transistor on the substrate layer. Forming a first metal layer on the substrate layer, the first metal layer including a gate line; forming a first insulating layer on the first metal layer; and forming a second metal layer on the first insulating layer The second metal layer and the gate line form a thin film transistor.
  • the planarization layer can be CVD (Chemical Vapor) Deposition, chemical vapor deposition) film deposited or PI material, or a combination of the two.
  • the auxiliary electrode may be a metal such as Mo, AL, Ti, Cu, or an alloy, or may be ITO.
  • S105 sequentially depositing a multilayer film on the auxiliary electrode layer, wherein the density of the single layer film in the multilayer film gradually increases from the bottom to the top.
  • a multilayer film may be sequentially deposited on the auxiliary electrode layer by chemical vapor deposition.
  • S106 applying a photoresist to the multilayer film, exposing, developing, and forming a predetermined pattern, and forming the predetermined pattern of the multilayer film to have the same width.
  • a cathode separation column is formed by using a plurality of films having different dense densities, and the compactness of the multilayer film is gradually increased from the bottom to the top, and finally dry etching, forming an inverted trapezoidal cathode isolation column due to the characteristics of the film.
  • the cathode isolating column formed in this manner has the characteristics of good process stability, good uniformity of the large plate, and is not easily detached from the substrate in the subsequent process.
  • the process of making the inverted trapezoidal cathode isolation column is simplified, and the efficiency is improved.
  • the density of the single-layer film in the multilayer film is gradually increased from bottom to top, and specifically includes:
  • the multilayer film includes at least three films, and the difference in density of adjacent films in the multilayer film gradually increases from bottom to top.
  • the multilayer film is from bottom to top, and the difference in density of adjacent films is larger and larger.
  • the difference in width of adjacent films is also larger, that is, the bottom edge of the inverted trapezoid
  • the density of the single-layer film in the multilayer film is gradually increased from bottom to top, and specifically includes:
  • the multilayer film comprises at least three layers of films, wherein the difference in density of adjacent films in the multilayer film is gradually reduced from bottom to top
  • the multilayer film is from bottom to top, and the difference in density of adjacent films is getting smaller and smaller.
  • the difference in width of adjacent films is smaller and smaller, that is, the bottom edge of the inverted trapezoid.
  • the smaller the difference between the width of the top and the top the better the stability of the cathode spacer, and the cathode is isolated to achieve separate control of the cathode, thereby reducing IR. Drop issues, improve display issues and improve display.
  • one or several gas combinations of SiNx, N2, NH3, TEOS, N2O, etc. are introduced during the process; the stability during the process can be ensured, and the success rate of the process is improved.
  • the etching process can be ICP (Inductively coupled) Plasma) or ECCP (Enhance Cathode Couple Plasma Mode) or RIE (Reactive Ion Etching) and any etching cavity.
  • ICP Inductively coupled
  • ECCP Enhance Cathode Couple Plasma Mode
  • RIE Reactive Ion Etching
  • the subsequent evaporation process is continued.
  • Subsequent evaporation processes include an organic material and a cathode, and the cathode is interrupted by a cathode isolation column.
  • the step of sequentially depositing a plurality of thin films on the auxiliary electrode layer comprises:
  • the step of sequentially depositing a plurality of thin films on the auxiliary electrode layer comprises:
  • a multilayer film is deposited in multiple steps on the auxiliary electrode layer. Simplify the steps.
  • the cathode isolation column can be placed in the PDL (pixel define) in addition to the auxiliary electrode.
  • the display panel process of the above embodiment can be applied to an ordinary display panel, and can also be applied to an AMOLED. Or IJP (inkjet printing) technology.
  • the cathode isolation pillar fabrication process of this embodiment includes:
  • a substrate 111 is provided, on which a fabricated TFT device (not shown) is disposed, and an auxiliary electrode 121 is disposed on the substrate 111.
  • step 2 a CVD film 140 is deposited on the auxiliary electrode 121, and the CVD film 140 is deposited a plurality of times, and the film is gradually densified from the bottom to the top.
  • step 3 a photoresist 131 is coated on the CVD film 140 and exposed.
  • step 4 development is performed to produce an image.
  • step 5 the CVD film 140 beyond the photoresist is removed by dry etching.
  • step 6 after the dry etching, since the CVD film 140 is gradually loosened from the top to the bottom, the inverted trapezoidal spacers 131, 141 are formed.
  • step 7 after the photoresist is stripped, a cathode spacer 141 formed of a CVD film is formed.
  • an embodiment of the present invention further discloses a display panel including a substrate layer 111, a thin film transistor, a flat layer 171, an auxiliary electrode layer 121, and a cathode isolation pillar 141.
  • the substrate layer 111 can be low temperature polysilicon (LTPS, low temperature) Poly-silicon) substrate.
  • LTPS low temperature polysilicon
  • a glass substrate, a resin substrate, or the like may be used. It can also be any TFT such as Oxide TFT or SPC.
  • a thin film transistor is formed on the substrate layer.
  • a flat layer 171 is formed on the thin film transistor.
  • the planarization layer 171 may be CVD (Chemical Vapor) Deposition, chemical vapor deposition) film deposited or PI material, or a combination of the two.
  • the auxiliary electrode layer 121 is formed on the flat layer.
  • the auxiliary electrode 121 may be a metal such as Mo, AL, Ti, Cu, or an alloy, or may be ITO.
  • a cathode isolation pillar 141 is formed on the auxiliary electrode layer 121, and the cathode isolation pillar 141 includes a multilayer film in which the density of the single-layer film 140 gradually increases from the bottom to the top, the multilayer The width of the single-layer film 140 in the film gradually increases from the bottom to the top, and the cathode separation column 141 has an inverted trapezoidal shape.
  • the cathode isolation pillar 141 is formed by using the film 140 having different layers of compactness.
  • the compactness of the multilayer film is gradually increased from the bottom to the top, and finally dry etching, forming an inverted trapezoidal cathode isolation column due to the characteristics of the film. .
  • the cathode isolating column formed in this manner has the characteristics of good process stability, good uniformity of the large plate, and is not easily detached from the substrate in the subsequent process.
  • the process of making the inverted trapezoidal cathode isolation column is simplified, and the efficiency is improved.
  • the multilayer film comprises at least three layers of films, wherein the difference in density of adjacent films in the multilayer film gradually increases from bottom to top.
  • the multilayer film is from bottom to top, and the difference in compactness of adjacent films is getting larger and larger.
  • the difference in width of adjacent films is also larger, that is, the bottom edge of the inverted trapezoid. The larger the difference between the width of the top and the top, the smaller the space occupied by the cathode spacer and space saving.
  • the multilayer film comprises at least three layers of films, wherein the difference in density of adjacent films in the multilayer film gradually decreases from bottom to top.
  • the multilayer film is from bottom to top, and the difference in density of adjacent films is getting smaller and smaller.
  • the difference in width of adjacent films is smaller and smaller, that is, the bottom edge of the inverted trapezoid.
  • the smaller the difference between the width of the top and the top the better the stability of the cathode spacer, and the cathode is isolated to achieve separate control of the cathode, thereby reducing IR. Drop issues, improve display issues and improve display.
  • the cathode isolation pillar 141 may be disposed on the auxiliary electrode 121, and may be disposed on the PDL (pixel).
  • the define layer, the pixel definition layer, is on the layer 181 or the bank layer.
  • the display panel may further include a first insulating layer 151, a first metal layer, and a second insulating layer 161.
  • the first insulating layer 151 is disposed on the substrate 111.
  • the first metal layer is disposed on the first insulating layer 151 and includes gate lines 191, 194.
  • the second insulating layer 161 is disposed on the first metal layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种OLED显示面板及其制程，制程包括：在辅助电极层(121)上依次沉积多层薄膜(140)，多层薄膜(140)中单层薄膜的致密性从下往上逐渐增大(S105)；将多层薄膜(140)形成多层薄膜(140)的宽度相等的预设图案(S106)；对多层薄膜(140)进行干蚀刻，以使多层薄膜(140)中单层薄膜的宽度从下往上逐渐变大(S107)，形成倒梯形的阴极隔离柱(141)(S108)。阴极隔离柱(141)的制程稳定性好。

Description

[根据细则37.2由ISA制定的发明名称]　一种OLED显示面板及其制程 技术领域
本发明涉及显示技术领域，特别涉及一种显示面板及显示面板栅极信号的控制方法。
 背景技术
现有的显示面板主要包括有液晶(Liquid Crystal Display，LCD)显示面板和OLED(Organic Light Emitting Diode，OLED)显示面板。其中，OLED显示面板具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示面板。随着OLED显示面板的工艺、制程的提升，以及成本的降低，OLED电视逐渐普及，为更多人所认识和接受。
而且，因OLED具有超越LCD的显示特性与品质：例如轻薄化，短的反应时间，低的驱动电压更好的显示色彩以及显示视角等优点，其受到大家广泛的关注，近些年其发展日新月异，不仅可以制作曲面显示，同时也逐渐向大尺寸发展。但是大尺寸又存在IR Drop Issue,甚至目视可见Mura,故在工艺上制作辅助电极以及阴极隔离柱，将阴极隔离开从而达到单独控制阴极，从而减少IR Drop的问题，改善显示问题。
传统的阴极隔离柱制作方式是通过有机光阻涂敷，曝光，显影制作而成，通过控制工艺参数形成倒梯形；稳定性差。
 技术问题
本发明的目的在于提供一种显示面板及其制程，解决现有的阴极隔离柱稳定性不好的问题。
 技术解决方案
为达到上述目的，本发明提供的显示面板的制程采用如下技术方案：
一种显示面板的制程，其包括步骤：
提供一基板层；
在所述基板层上形成薄膜晶体管；
在所述薄膜晶体管上形成一层平坦层；
在所述平坦层上形成辅助电极层；
通过化学气相沉积法在所述辅助电极层上依次沉积多层薄膜，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐增大；
对所述多层薄膜涂敷光阻、曝光、显影形成预设图案，形成预设图案的所述多层薄膜的宽度相等；
对所述多层薄膜进行干蚀刻，以使所述多层薄膜中单层薄膜的宽度从下往上逐渐变大；
去除所述多层薄膜上的涂覆光阻，形成倒梯形的阴极隔离柱。
在本发明优选实施例的显示面板的制程中，在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
多次进入机台，其中每次进入机台在所述辅助电极层上沉积一层薄膜。
在本发明优选实施例的显示面板的制程中，在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
进入一次机台，在所述辅助电极层上多步骤沉积多层薄膜。
在本发明优选实施例的显示面板的制程中，在制程过程中通入SiNx、N2、NH3、TEOS、N2O中一种或多种气体。
在本发明优选实施例的显示面板的制程中，所述辅助电极由ITO、Mo、AL、Ti、Cu及其合金中的一种或多种形成。
在本发明优选实施例的显示面板的制程中，所述平坦化层为化学气相沉积法沉积形成的薄膜。
一种显示面板的制程，其包括步骤：
提供一基板层；
在所述基板层上形成薄膜晶体管；
在所述薄膜晶体管上形成一层平坦层；
在所述平坦层上形成辅助电极层；
在所述辅助电极层上依次沉积多层薄膜，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大；
对所述多层薄膜涂敷光阻、曝光、显影形成预设图案，形成预设图案的所述多层薄膜的宽度相等；
对所述多层薄膜进行干蚀刻，以使所述多层薄膜中单层薄膜的宽度从下往上逐渐变大；
去除所述多层薄膜上的涂覆光阻，形成倒梯形的阴极隔离柱。
在本发明优选实施例的显示面板的制程中，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，包括：
所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐增大。
在本发明优选实施例的显示面板的制程中，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，包括：
所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐减小。
在本发明优选实施例的显示面板的制程中，在所述辅助电极层上依次沉积多层薄膜，包括：
通过化学气相沉积法在所述辅助电极层上依次沉积多层薄膜。
在本发明优选实施例的显示面板的制程中，在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
多次进入机台，其中每次进入机台在所述辅助电极层上沉积一层薄膜。
在本发明优选实施例的显示面板的制程中，在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
进入一次机台，在所述辅助电极层上多步骤沉积多层薄膜。
在本发明优选实施例的显示面板的制程中，在制程过程中通入SiNx、N2、NH3、TEOS、N2O中一种或多种气体。
在本发明优选实施例的显示面板的制程中，所述辅助电极由ITO、Mo、AL、Ti、Cu及其合金中的一种或多种形成。
在本发明优选实施例的显示面板的制程中，所述平坦化层为化学气相沉积法沉积形成的薄膜。
一种显示面板，其包括：
一基板层；
薄膜晶体管，形成在所述基板层上；
一平坦层，形成在所述薄膜晶体管上；
一辅助电极层，形成在所述平坦层上；
一阴极隔离柱，形成在所述辅助电极层上，所述阴极隔离柱包括多层薄膜，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，所述多层薄膜中单层薄膜的宽度从下往上逐渐增大，所述阴极隔离柱呈倒梯形。
在本发明优选实施例的显示面板中，所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐增大。
在本发明优选实施例的显示面板中，所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐减小。
在本发明优选实施例的显示面板中，所述辅助电极由ITO、Mo、AL、Ti、Cu及其合金中的一种或多种形成。
在本发明优选实施例的显示面板中，所述平坦化层为化学气相沉积法沉积形成的薄膜。
 有益效果
相对于现有技术，本发明的有益效果是：采用多层致密性不同的薄膜形成阴极隔离柱，多层薄膜的致密性从下往上逐渐变大，最后干蚀刻，由于薄膜的特性形成倒梯形的阴极隔离柱。如此方式形成的阴极隔离柱具有制程稳定性好，大板均一性好的特点，并在后续制程中不容易从基板上脱落。简化了制作倒梯形的阴极隔离柱的制程，提高了效率。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为传统的阴极隔离柱形成的示意图；
图2为本发明实施例显示面板的制程流程图；
图3为本发明实施例阴极隔离柱形成步骤1-3的示意图；
图4为本发明实施例阴极隔离柱形成步骤4-7的示意图；
图5为本发明实施例显示面板的示意图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在图中，结构相似的单元是以相同标号表示。
下面参考图1至图5描述本发明实施例一种显示面板及其制程。
根据本发明实施例，如图1至图5所示，图1为传统的阴极隔离柱形成的示意图；图2为本发明实施例显示面板的制程流程图；图3为本发明实施例阴极隔离柱形成步骤1-3的示意图；图4为本发明实施例阴极隔离柱形成步骤4-7的示意图；图5为本发明实施例显示面板的示意图。
如图1所示，传统的阴极隔离柱制作过程包括：
在步骤1中，提供基板110，基板110上设有制作好的TFT器件（图中未示出），基板110上设有辅助电极120。
在步骤2中，辅助电极120上涂覆一层光阻130。
在步骤3中，对涂覆光阻130的基板曝光。
在步骤4中，显影，并形成倒梯形的阴极隔离柱141。
如图2所示，本发明实施例公开了一种显示面板的制程，所述显示面板的制程包括步骤S101-S108。
S101：提供一基板层。其中，基板层可以为低温多晶硅（LTPS，low temperature poly-silicon）基板。也可以为玻璃基板、树脂基板等。还可以是Oxide TFT or SPC等任何TFT。
S102：在所述基板层上形成薄膜晶体管。在所述基板层上形成第一金属层，所述第一金属层包括栅极线；在所述第一金属层上形成第一绝缘层；在所述第一绝缘层上形成第二金属层，所述第二金属层与所述栅极线形成薄膜晶体管。
S103：在所述薄膜晶体管上形成一层平坦层。平坦化层可以是CVD（Chemical Vapor Deposition，化学气相沉积法）方式沉积的薄膜或者PI材料，或者两者的结合。
S104：在所述平坦层上形成辅助电极层。辅助电极可以是Mo、AL、Ti、Cu等金属以及合金，还可以是ITO。
S105：在所述辅助电极层上依次沉积多层薄膜，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大。其中，可以通过化学气相沉积法在所述辅助电极层上依次沉积多层薄膜。
S106：对所述多层薄膜涂敷光阻、曝光、显影形成预设图案，形成预设图案的所述多层薄膜的宽度相等。
S107：对所述多层薄膜进行干蚀刻，以使所述多层薄膜中单层薄膜的宽度从下往上逐渐变大。
S108：去除所述多层薄膜上的涂覆光阻，形成倒梯形的阴极隔离柱。
本发明实施例中，采用多层致密性不同的薄膜形成阴极隔离柱，多层薄膜的致密性从下往上逐渐变大，最后干蚀刻，由于薄膜的特性形成倒梯形的阴极隔离柱。如此方式形成的阴极隔离柱具有制程稳定性好，大板均一性好的特点，并在后续制程中不容易从基板上脱落。简化了制作倒梯形的阴极隔离柱的制程，提高了效率。
可选的，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，具体包括：
所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐增大。
如此设计，多层薄膜从下往上，相邻薄膜的致密性的差值越来越大，后期干蚀刻后，相邻薄膜的宽度的差值也越来越大，即倒梯形的底边和顶边的宽度差越大，阴极隔离柱所占的空间越小，节约空间。
可选的，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，具体包括：
所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐减小
如此设计，多层薄膜从下往上，相邻薄膜的致密性的差值越来越小，后期干蚀刻后，相邻薄膜的宽度的差值也越来越小，即倒梯形的底边和顶边的宽度差越小，阴极隔离柱的稳定性越好，将阴极隔离开从而达到单独控制阴极，从而减少IR Drop的问题，改善显示问题，提高显示效果。
进一步的，在制程过程中通入SiNx、N2、NH3、TEOS、N2O等一种或者几种气体组合；能够保证制程过程中的稳定性，提高制程的成功率。
在一些实施例中，蚀刻过程可以是ICP（Inductively coupled plasma）或ECCP（Enhance Cathode Couple Plasma Mode）或RIE（Reactive Ion Etching）等任何蚀刻腔体。
在一些实施例中，形成倒梯形的阴极隔离柱后，继续执行后续的蒸镀制程。后续的蒸镀制程包含有机材料以及阴极，阴极被阴极隔离柱隔断。
可选的，在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
多次进入机台，其中每次进入机台在所述辅助电极层上沉积一层薄膜。沉积效果更好。
可选的，在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
进入一次机台，在所述辅助电极层上多步骤沉积多层薄膜。简化操作步骤。
在一些实施例中，阴极隔离柱除了设置在辅助电极上，还可以设置在PDL(pixel define layer，像素定义层)层或坝(bank)层上。
上述实施方式的显示面板制程可以应用在普通显示面板上，也可以应用于AMOLED 或者IJP(喷墨打印)技术上。
如图3和图4所示，在本实施例的阴极隔离柱制作过程包括：
在步骤1中，提供基板111，基板111上设有制作好的TFT器件（图中未示出），基板111上设有辅助电极121。
在步骤2中，辅助电极121上沉积CVD薄膜140，CVD薄膜140为多次沉积，由下至上薄膜逐渐致密。
在步骤3中，在CVD薄膜140上涂覆光阻131并曝光
在步骤4中，显影，制作图像。
在步骤5中，干蚀刻，将超出光阻的CVD薄膜140去除。
在步骤6中，干蚀刻后，由于CVD薄膜140由上向下逐渐疏松，故形成倒梯形隔离柱131、141。
在步骤7中，剥离光阻后，CVD薄膜形成的阴极隔离柱141形成。
如图5所示，本发明实施例还公开一种显示面板，所述显示面板包括基板层111、薄膜晶体管、平坦层171、辅助电极层121和阴极隔离柱141。
其中，基板层111可以为低温多晶硅（LTPS，low temperature poly-silicon）基板。也可以为玻璃基板、树脂基板等。还可以是Oxide TFT or SPC等任何TFT。薄膜晶体管形成在所述基板层上。
平坦层171形成在所述薄膜晶体管上。平坦化层171可以是CVD（Chemical Vapor Deposition，化学气相沉积法）方式沉积的薄膜或者PI材料，或者两者的结合。
辅助电极层121形成在所述平坦层上。辅助电极121可以是Mo、AL、Ti、Cu等金属以及合金，还可以是ITO。
阴极隔离柱141形成在所述辅助电极层121上，所述阴极隔离柱141包括多层薄膜，所述多层薄膜中单层薄膜140的致密性从下往上逐渐增大，所述多层薄膜中单层薄膜140的宽度从下往上逐渐增大，所述阴极隔离柱141呈倒梯形。
本发明实施例中，采用多层致密性不同的薄膜140形成阴极隔离柱141，多层薄膜的致密性从下往上逐渐变大，最后干蚀刻，由于薄膜的特性形成倒梯形的阴极隔离柱。如此方式形成的阴极隔离柱具有制程稳定性好，大板均一性好的特点，并在后续制程中不容易从基板上脱落。简化了制作倒梯形的阴极隔离柱的制程，提高了效率。
可选的，所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐增大
如此设计，多层薄膜从下往上，相邻薄膜的致密性的差值越来越大，后期干蚀刻后，相邻薄膜的宽度的差值也越来越大，即倒梯形的底边和顶边的宽度差越大，阴极隔离柱所占的空间越小，节约空间。
可选的，所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐减小。
如此设计，多层薄膜从下往上，相邻薄膜的致密性的差值越来越小，后期干蚀刻后，相邻薄膜的宽度的差值也越来越小，即倒梯形的底边和顶边的宽度差越小，阴极隔离柱的稳定性越好，将阴极隔离开从而达到单独控制阴极，从而减少IR Drop的问题，改善显示问题，提高显示效果。
在一些实施例中，阴极隔离柱141除了设置在辅助电极121上，还可以设置在PDL(pixel define layer，像素定义层)层181或坝(bank)层上。
所述显示面板还可以包括第一绝缘层151、第一金属层和第二绝缘层161。
第一绝缘层151设置在基板111上。第一金属层设置在第一绝缘层151上，包括栅极线191、194。第二绝缘层161设置在第一金属层上。
虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板的制程，其包括步骤：
    提供一基板层；
    在所述基板层上形成薄膜晶体管；
    在所述薄膜晶体管上形成一层平坦层；
    在所述平坦层上形成辅助电极层；
    通过化学气相沉积法在所述辅助电极层上依次沉积多层薄膜，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐增大；
    对所述多层薄膜涂敷光阻、曝光、显影形成预设图案，形成预设图案的所述多层薄膜的宽度相等；
    对所述多层薄膜进行干蚀刻，以使所述多层薄膜中单层薄膜的宽度从下往上逐渐变大；
    去除所述多层薄膜上的涂覆光阻，形成倒梯形的阴极隔离柱。
  2. 根据权利要求1所述的显示面板的制程，其中在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
    多次进入机台，其中每次进入机台在所述辅助电极层上沉积一层薄膜。
  3. 根据权利要求1所述的显示面板的制程，其中在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
    进入一次机台，在所述辅助电极层上多步骤沉积多层薄膜。
  4. 根据权利要求1所述的显示面板的制程，其中在制程过程中通入SiNx、N2、NH3、TEOS、N2O中一种或多种气体。
  5. 根据权利要求1所述的显示面板的制程，其中所述辅助电极由ITO、Mo、AL、Ti、Cu及其合金中的一种或多种形成。
  6. 根据权利要求1所述的显示面板的制程，其中所述平坦化层为化学气相沉积法沉积形成的薄膜。
  7. 一种显示面板的制程，其包括步骤：
    提供一基板层；
    在所述基板层上形成薄膜晶体管；
    在所述薄膜晶体管上形成一层平坦层；
    在所述平坦层上形成辅助电极层；
    在所述辅助电极层上依次沉积多层薄膜，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大；
    对所述多层薄膜涂敷光阻、曝光、显影形成预设图案，形成预设图案的所述多层薄膜的宽度相等；
    对所述多层薄膜进行干蚀刻，以使所述多层薄膜中单层薄膜的宽度从下往上逐渐变大；
    去除所述多层薄膜上的涂覆光阻，形成倒梯形的阴极隔离柱。
  8. 根据权利要求7所述的显示面板的制程，其中所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，包括：
    所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐增大。
  9. 根据权利要求7所述的显示面板的制程，其中所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，包括：
    所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐减小。
  10. 根据权利要求7所述的显示面板的制程，其中在所述辅助电极层上依次沉积多层薄膜，包括：
    通过化学气相沉积法在所述辅助电极层上依次沉积多层薄膜。
  11. 根据权利要求7所述的显示面板的制程，其中在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
    多次进入机台，其中每次进入机台在所述辅助电极层上沉积一层薄膜。
  12. 根据权利要求7所述的显示面板的制程，其中在所述辅助电极层上依次沉积多层薄膜的步骤，包括：
    进入一次机台，在所述辅助电极层上多步骤沉积多层薄膜。
  13. 根据权利要求7所述的显示面板的制程，其中在制程过程中通入SiNx、N2、NH3、TEOS、N2O中一种或多种气体。
  14. 根据权利要求7所述的显示面板的制程，其中所述辅助电极由ITO、Mo、AL、Ti、Cu及其合金中的一种或多种形成。
  15. 根据权利要求7所述的显示面板的制程，其中所述平坦化层为化学气相沉积法沉积形成的薄膜。
  16. 一种显示面板，其包括：
    一基板层；
    薄膜晶体管，形成在所述基板层上；
    一平坦层，形成在所述薄膜晶体管上；
    一辅助电极层，形成在所述平坦层上；
    一阴极隔离柱，形成在所述辅助电极层上，所述阴极隔离柱包括多层薄膜，所述多层薄膜中单层薄膜的致密性从下往上逐渐增大，所述多层薄膜中单层薄膜的宽度从下往上逐渐增大，所述阴极隔离柱呈倒梯形。
  17. 根据权利要求16所述的显示面板，其中所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐增大。
  18. 根据权利要求16所述的显示面板，其中所述多层薄膜包括至少三层薄膜，所述多层薄膜中相邻薄膜的致密性的差值从下往上逐渐减小。
  19. 根据权利要求16所述的显示面板，其中所述辅助电极由ITO、Mo、AL、Ti、Cu及其合金中的一种或多种形成。
  20. 根据权利要求16所述的显示面板，其中所述平坦化层为化学气相沉积法沉积形成的薄膜。
PCT/CN2017/109534 2017-09-05 2017-11-06 一种oled显示面板及其制程 WO2019047357A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/574,538 US10388707B2 (en) 2017-09-05 2017-11-06 Display panel and manufacturing process thereof
US16/460,741 US10593740B2 (en) 2017-09-05 2019-07-02 Display panel and manufacturing process thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710788449.2A CN107622975B (zh) 2017-09-05 2017-09-05 一种显示面板及其制程
CN201710788449.2 2017-09-05

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US15/574,538 A-371-Of-International US10388707B2 (en) 2017-09-05 2017-11-06 Display panel and manufacturing process thereof
US16/460,741 Division US10593740B2 (en) 2017-09-05 2019-07-02 Display panel and manufacturing process thereof

Publications (1)

Publication Number Publication Date
WO2019047357A1 true WO2019047357A1 (zh) 2019-03-14

Family

ID=61088527

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/109534 WO2019047357A1 (zh) 2017-09-05 2017-11-06 一种oled显示面板及其制程

Country Status (2)

Country Link
CN (1) CN107622975B (zh)
WO (1) WO2019047357A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109360900B (zh) * 2018-09-14 2020-12-25 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制作方法
CN110767827A (zh) * 2018-10-31 2020-02-07 云谷（固安）科技有限公司 显示面板、复合屏、显示终端和复合屏的制备方法
CN209071332U (zh) * 2018-10-31 2019-07-05 云谷（固安）科技有限公司 显示面板、显示屏和显示终端
CN110767690B (zh) * 2018-10-31 2023-09-22 云谷（固安）科技有限公司 显示面板、显示屏、制备显示面板的方法和显示终端
CN109950418A (zh) * 2019-03-18 2019-06-28 云谷（固安）科技有限公司 显示面板及显示屏

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1416300A (zh) * 2002-11-12 2003-05-07 清华大学 一种有机电致发光器件及其制备方法
CN1866537A (zh) * 2005-05-17 2006-11-22 Lg电子株式会社 有机电致发光器件及其制造方法
KR20090048037A (ko) * 2007-11-09 2009-05-13 엘지마이크론 주식회사 플라즈마 디스플레이 패널의 제조방법 및 플라즈마디스플레이 패널
CN103762288A (zh) * 2014-01-23 2014-04-30 同辉电子科技股份有限公司 一种用于高压led的反射弧型隔离槽
CN206293473U (zh) * 2016-10-31 2017-06-30 昆山国显光电有限公司 一种oled器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593379A (zh) * 2012-02-09 2012-07-18 昆山维信诺显示技术有限公司 制造无源矩阵有机电致发光器件的方法、该器件及其设备
CN103231570B (zh) * 2013-04-11 2016-03-30 合肥京东方光电科技有限公司 一种薄膜层及其制作方法、显示用基板、液晶显示器
CN105633102B (zh) * 2016-04-05 2018-11-09 京东方科技集团股份有限公司 阵列基板、薄膜晶体管、显示器件的制作方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1416300A (zh) * 2002-11-12 2003-05-07 清华大学 一种有机电致发光器件及其制备方法
CN1866537A (zh) * 2005-05-17 2006-11-22 Lg电子株式会社 有机电致发光器件及其制造方法
KR20090048037A (ko) * 2007-11-09 2009-05-13 엘지마이크론 주식회사 플라즈마 디스플레이 패널의 제조방법 및 플라즈마디스플레이 패널
CN103762288A (zh) * 2014-01-23 2014-04-30 同辉电子科技股份有限公司 一种用于高压led的反射弧型隔离槽
CN206293473U (zh) * 2016-10-31 2017-06-30 昆山国显光电有限公司 一种oled器件

Also Published As

Publication number Publication date
CN107622975B (zh) 2020-01-14
CN107622975A (zh) 2018-01-23

Similar Documents

Publication Publication Date Title
WO2019047357A1 (zh) 一种oled显示面板及其制程
WO2013116992A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2019100455A1 (zh) 一种柔性触控显示屏及其制作方法
WO2013116994A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2014169621A1 (zh) 薄膜晶体管及其制作方法
WO2013116995A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2017084110A1 (zh) 薄膜晶体管阵列面板及其制作方法
WO2016201729A1 (zh) 一种阵列基板及其制作方法、液晶显示器
CN105793996A (zh) 自对准金属氧化物tft
WO2017008318A1 (zh) 一种阵列基板及其制作方法
WO2016058172A1 (zh) 一种coa基板及其制作方法
WO2013082755A1 (zh) 液晶基板及其制作方法
WO2016119280A1 (zh) 氧化物薄膜晶体管及其制作方法
WO2013185407A1 (zh) 显示面板及其制造方法
WO2018196144A1 (zh) 一种oled显示面板的像素结构及其制程
CN102427061B (zh) 有源矩阵有机发光显示器的阵列基板制造方法
WO2018032558A1 (zh) 一种阵列基板及其制作方法
WO2017140015A1 (zh) 双栅极tft阵列基板及制作方法
WO2016026176A1 (zh) Tft基板的制作方法及其结构
WO2016090690A1 (zh) 一种ltps像素单元及其制造方法
WO2017152451A1 (zh) Ffs模式的阵列基板及制作方法
WO2017152450A1 (zh) Ffs模式的阵列基板及制作方法
WO2018218712A1 (zh) 低温多晶硅tft基板及其制作方法
WO2013166668A1 (zh) 一种薄膜晶体管阵列基板及其制作方法
WO2019056447A1 (zh) 一种阵列基板及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17924469

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17924469

Country of ref document: EP

Kind code of ref document: A1