WO2018218712A1 - 低温多晶硅tft基板及其制作方法 - Google Patents

低温多晶硅tft基板及其制作方法 Download PDF

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Publication number
WO2018218712A1
WO2018218712A1 PCT/CN2017/089620 CN2017089620W WO2018218712A1 WO 2018218712 A1 WO2018218712 A1 WO 2018218712A1 CN 2017089620 W CN2017089620 W CN 2017089620W WO 2018218712 A1 WO2018218712 A1 WO 2018218712A1
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Prior art keywords
layer
gate
insulating layer
island
portions
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PCT/CN2017/089620
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English (en)
French (fr)
Inventor
王涛
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武汉华星光电技术有限公司
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Priority to US15/735,614 priority Critical patent/US10355138B2/en
Publication of WO2018218712A1 publication Critical patent/WO2018218712A1/zh

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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of liquid crystal display panel fabrication, and in particular to a low temperature polysilicon TFT substrate and a method of fabricating the same.
  • Low Temperature Poly-silicon (LTPS) technology is a new generation of TFT (Thin Film Transistor, thin film transistor) substrate manufacturing technology, and traditional amorphous silicon (a-Si)
  • TFT Thin Film Transistor, thin film transistor
  • a-Si amorphous silicon
  • N-type low temperature polysilicon TFT Thin Film Transistor, a thin film transistor substrate, typically a self-collimating N-TFT structure with a gate covering the polysilicon undoped region (ie, the channel region) underneath it, without overlapping the doped regions.
  • a low-temperature polysilicon TFT substrate since the impedance of the lightly doped region is constant and cannot be adjusted, at a higher drain voltage, there will be severe impact ionization in the drain region, thereby generating Warping effect Effect), which causes adverse effects on the long-term stable operation of the device.
  • the invention provides a method for manufacturing a low temperature polysilicon TFT substrate, comprising:
  • An interlayer insulating layer and a source and a drain electrically connected to each of the N-type heavily doped regions are formed on the gate.
  • the ion lightly doped ions on both sides of each of the island-shaped polycrystalline silicon portions using the photoresist portion as a mask is P ions.
  • ions that are ion heavily doped with each of the doped regions not covered by the gate with the gate as a mask are P ions.
  • the indifference-free full-surface ion doped ions for each of the island-shaped polysilicon portions are B ions.
  • the step of providing a plurality of light shielding portions on the substrate comprises:
  • the second metal layer is etched by a yellow light process and an etching process to form a plurality of light shielding portions spaced apart from each other.
  • the step of forming an interlayer insulating layer on the gate and a source and a drain electrically connected to each of the N-type heavily doped regions comprises:
  • the via is electrically connected to the N-type heavily doped region.
  • a gate insulating layer and a first metal layer are sequentially formed on the substrate, and the first metal layer is patterned to be corresponding to each of the island polysilicon portions.
  • the steps of forming a gate include:
  • the first metal layer is etched by a yellow light process and an etching process to form a plurality of gate electrodes spaced apart from each other.
  • the method further includes:
  • the pixel electrode is made of indium tin oxide.
  • the invention also provides a method for manufacturing a low temperature polysilicon TFT substrate, comprising:
  • An insulating layer is deposited on the entire surface
  • a planar layer, a common electrode, a passivation layer, and a pixel electrode electrically connected to each of the drains are sequentially formed on the interlayer insulating layer, the source, and the drain.
  • the ion lightly doped ions on both sides of each of the island-shaped polysilicon portions are masked by the photoresist portion; the gate is used as a mask pair and the gate is not used.
  • the ion heavily doped ions of each of the doped regions covered by the pole are P ions.
  • the indifference-free full-surface ion doped ions for each of the island-shaped polysilicon portions are B ions.
  • the step of providing a plurality of light shielding portions on the substrate comprises:
  • the second metal layer is etched by a yellow light process and an etching process to form a plurality of light shielding portions spaced apart from each other.
  • a gate insulating layer and a first metal layer are sequentially formed on the substrate, and the first metal layer is patterned to be corresponding to each of the island polysilicon portions.
  • the steps of forming a gate include:
  • the first metal layer is etched by a yellow light process and an etching process to form a plurality of gate electrodes spaced apart from each other.
  • a planar layer, a common electrode, a passivation layer, and an electrical connection with each of the drains are sequentially formed on the interlayer insulating layer, the source, and the drain.
  • the steps of a pixel electrode include:
  • the technique employed to deposit an interlevel insulating layer over the entire surface is a chemical vapor deposition technique.
  • the pixel electrode is made of indium tin oxide.
  • the invention also provides a low temperature polysilicon TFT substrate, which comprises:
  • a buffer layer disposed on the substrate and the light shielding portion
  • each of the polysilicon portions including: a channel region located in the middle of the polysilicon portion, and two N-type heavily doped regions located at opposite ends of each polysilicon portion, And an N-type lightly doped region between the channel region and the adjacent N-type heavily doped region;
  • a gate insulating layer disposed on the polysilicon portion and the buffer layer
  • a width of the gate is smaller than a width of the polysilicon portion, and the gate covers the channel region and the N-type lightly doped region ;
  • An interlayer insulating layer disposed on the plurality of gates and the gate insulating layer;
  • each of the sources being electrically connected to an N-type heavily doped region at one end of the polysilicon portion;
  • a plurality of drains are disposed on the interlayer insulating layer, and each of the drains is electrically connected to an N-type heavily doped region at the other end of the polysilicon portion.
  • the gate insulating layer and the interlayer insulating layer are provided with two first via holes above each of the N-type heavily doped regions, each of the source and each A drain is electrically connected to the N-type heavily doped region via the first via, respectively.
  • the low temperature polysilicon TFT substrate further includes:
  • a passivation layer disposed on the common electrode and the planar layer
  • each of the pixel electrodes is via the first The two vias are electrically connected to the drain.
  • the method for fabricating the low-temperature polysilicon TFT comprises: sequentially forming a light-shielding portion, a buffer layer and an island-shaped polysilicon portion on the substrate, and performing light doping on both sides of the island-shaped polycrystalline silicon portion to form a doped region and a channel region; Forming a gate insulating layer and a gate in sequence, the gate covering the channel region and both ends of the channel region beyond the two ends of the channel region and covering a portion of the doped region; and performing ion weight on the doped region not covered by the gate Doping, forming an N-type heavily doped region and an N-type lightly doped region; forming an interlayer insulating layer on the gate, and a source drain electrically connected to the N-type heavily doped region.
  • the scheme changes the N-TFT structure in the low-temperature polysilicon TFT substrate to an N-TFT structure in which the gate and the lightly doped region overlap, so that the impedance variation of the lightly doped region can be controlled by the gate voltage to effectively suppress the N-type.
  • the TFT produces a warping effect that enhances the operating characteristics of the device.
  • FIG. 1 is a schematic flow chart of a method for fabricating a low temperature polysilicon TFT substrate in a preferred embodiment of the present invention.
  • 2A-2C are schematic views showing processes of a low temperature polysilicon TFT substrate in a preferred embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a low temperature polysilicon TFT substrate in a preferred embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a low temperature polysilicon TFT device in a preferred embodiment of the present invention.
  • FIG. 5 is a schematic view showing another structure of a low temperature polysilicon TFT device in a preferred embodiment of the present invention.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • FIG. 1 is a schematic flow chart of a method for fabricating a low temperature polysilicon TFT substrate according to a preferred embodiment of the present invention.
  • a method for fabricating a low-temperature polysilicon TFT substrate of the preferred embodiment includes:
  • S104 removing the photoresist portion, sequentially forming a gate insulating layer and a first metal layer on the island-shaped polysilicon portion, and patterning the first metal layer to form a gate electrode corresponding to the island-shaped polysilicon portion.
  • the width of the gate is smaller than the width of the island-shaped polysilicon portion, the gate covers the channel region of the island-shaped polysilicon portion, and both ends of the gate extend beyond the two ends of the channel region to cover a portion of the doped region;
  • S105 performing ion heavy doping on the doped region not covered by the gate by using the gate as a mask, forming an N-type heavily doped region located on both sides of the island-shaped polysilicon portion, and being located in the N-type heavily doped region and the trench The doped region between the track regions serves as an N-type lightly doped region;
  • the substrate may be a glass substrate.
  • the preparation material of the light shielding portion may be an opaque metal material to prevent the backlight light from directly impinging on the logic circuit of the TFT on the substrate, and may be set by an opaque metal (such as Al, Ag, Cu, Mo, Au, etc.) or a laminate. It can also be made of an alloy of each metal.
  • PVD Physical
  • Vapor Deposition, physical vapor deposition technology deposits a second metal layer 11 on the substrate 100, and then coats the photoresist, and etches the second metal layer 11 through a yellow light process and an etching process to form a plurality of light shieldings spaced apart from each other. Part 111.
  • the buffer layer 12 is a composite layer of a silicon nitride layer and a silicon oxide layer.
  • the silicon nitride layer has a thickness of 40 to 100 nm
  • the silicon oxide layer has a thickness of 100 to 200 nm.
  • a low temperature polysilicon layer 13 is deposited over the entire surface.
  • the low temperature polysilicon layer 13 may be patterned by a yellow light process and an etching process to form an island polysilicon portion 131 corresponding to the light shielding portion 111.
  • the island-shaped polycrystalline silicon portion 131 is subjected to indiscriminate full-surface ion doping (ion implantation) to adjust the threshold voltage (Vth) of the N-TFT.
  • the ions doped with the entire surface of the island-shaped polycrystalline silicon portion 131 are B ions.
  • the photoresist may be coated on the buffer layer 12 by coating, and then the photoresist is patterned by a full exposure process to form the photoresist portion 14.
  • the photoresist portion 14 is formed above the island-shaped polysilicon portion 131 and located at an intermediate portion of the island-shaped polysilicon portion 131.
  • the width of the photoresist portion 14 is about 1/3 to 1 of the width of the island-shaped polysilicon portion 131. Between 2.
  • the two sides of the island-shaped polycrystalline silicon portion 131 are lightly doped with the photoresist portion 14 as a mask, and doped regions 1311 on both sides of the island-shaped polycrystalline silicon portion 131 and trenches between the doped 1311 regions on both sides are formed.
  • the ions which are lightly doped with ions on both sides of the island-shaped polycrystalline silicon portion 131 by using the photoresist portion 14 as a mask are P ions.
  • the photoresist portion 14 may be removed by a photoresist strip process or photoresist ashing. Then, a gate insulating layer 15 may be deposited on the substrate 100 by a CVD technique, and a first metal layer 16 may be formed on the gate insulating layer 15 by a PVD technique.
  • the material of the gate insulating layer 15 may be silicon nitride or silicon oxide; the material of the first metal layer may be molybdenum.
  • a first uniform thickness of the photoresist is applied to the first metal layer 16, and the first metal layer 16 is etched by a yellow light process and an etching process to form a plurality of spaces spaced apart from each other on the island polysilicon portion 131.
  • the width of the gate 161 is smaller than the width of the island-shaped polysilicon portion 131, the gate 161 covers the channel region 1312 of the island-shaped polysilicon portion, and both ends of the gate 161 are beyond the two ends of the channel region 1312, thereby A portion of the doped region 1311 is covered.
  • the distance between the two ends of the gate electrode 161 beyond the two ends of the channel region 1312 may be about 1 to 2 ⁇ m.
  • step S105 referring to FIG. 2A and FIG. 2B, the doped region 1311 not covered by the gate is heavily doped by the gate 161 as a mask to form an N-type heavily doped on both sides of the island-shaped polysilicon portion 131.
  • the impurity region 1311A, and the doping region 1311 between the N-type heavily doped region 1311A and the channel region 1312 is referred to as an N-type lightly doped region 1311B, and has a width of about 1.5 ⁇ m.
  • the ion heavily doped by the doped region 1311 not covered by the gate 161 with the gate 161 as a mask is P ion.
  • an insulating material may be deposited over the entire surface by a CVD technique to form an interlayer insulating layer 17 on the gate insulating layer 15 and the gate electrode 161.
  • the interlayer insulating layer 17 may be a silicon nitride layer, a silicon oxide layer, or a combination of the two.
  • a first via hole is formed on the interlayer insulating layer 17 and the gate insulating layer 15 correspondingly over the N-type heavily doped region 1311A by a yellow light process to expose the two N-type heavily doped regions 1311A.
  • the first via hole includes a via hole P1 on one side of the gate electrode 161 and a via hole P2 formed on the other side.
  • the N-type heavily doped region 1311A may be entirely exposed or partially exposed.
  • the third metal layer 18 can then be deposited over the entire surface using PVD techniques.
  • the third metal layer 18 is patterned by a yellow light process or an etching process to form a source electrode 181 and a drain electrode 182 on the interlayer insulating layer 17, so that the source electrode 181 passes through the via hole P1 and the island-shaped polysilicon portion.
  • the N-type heavily doped region 1311A on the 131 side is electrically connected, and the drain 182 is electrically connected to the N-type heavily doped region 1311A on the other side of the island-shaped polycrystalline silicon portion 131 via the via P2.
  • the source 181 and the drain 182 may be a molybdenum/aluminum/molybdenum composite layer.
  • a planarization layer 19 may be sequentially formed on the TFT substrate formed above.
  • the pixel electrode 1031 may be sequentially formed on the TFT substrate formed above.
  • the planarization layer 19 may be entirely deposited on the interlayer insulating layer 17, the source 181, and the drain 182 by a CVD technique, and then the common electrode material layer 101 may be deposited on the planarization layer 19. Subsequently, a photoresist may be coated on the common electrode material layer 101, and the common electrode material layer 101 corresponding to the drain electrode 182 is removed by a yellow light process and an etching process to form the common electrode 1011 on the flat layer 19.
  • the flat layer 19 is an insulating material layer, and the common electrode 1011 may be made of a transparent conductive metal oxide or a transparent conductive metal film.
  • a passivation layer 102 can be formed on the flat layer 19 and the common electrode 1011 by a CVD technique.
  • the material of the passivation layer 102 can be silicon nitride, silicon oxide or the like.
  • a second via Q is formed on the flat layer 19 and the passivation layer 102 corresponding to the drain 182 by a yellow light process to expose the drain 182. Wherein, the drain 182 can be partially exposed.
  • the pixel electrode material layer 103 may be deposited on the entire surface by a PVD technique, and then the pixel electrode material layer 103 is patterned by a yellow light process and an etching process to form a pixel electrode 1031 on the passivation layer 102.
  • the pixel electrode 1031 is electrically connected to the drain electrode 182 through the second via hole Q. Thereby, the fabrication of the low temperature polysilicon TFT substrate is completed.
  • the material of the pixel electrode 1031 can be indium tin oxide (ie, ITO) to enhance the conductivity of the pixel electrode.
  • the method for fabricating the low-temperature polysilicon TFT substrate changes the N-TFT structure in the low-temperature polysilicon TFT substrate to an N-TFT structure in which the gate and the lightly doped region overlap, so that the gate can be passed through the gate.
  • the pole voltage controls the impedance variation of the lightly doped region to effectively suppress the warpage effect of the N-type TFT and improve the operating characteristics of the device.
  • the embodiment of the invention further provides a low temperature polysilicon TFT substrate.
  • the low-temperature polysilicon TFT substrate includes a plurality of TFTs, and each TFT corresponds to a light shielding portion, a low temperature polysilicon portion, a gate electrode, a source electrode, and a drain electrode.
  • the low temperature polysilicon TFT substrate includes:
  • a buffer layer 22 disposed on the substrate 200 and the light shielding portion 21;
  • the polysilicon portion 23, which is disposed on the buffer layer 22, includes a channel region 232 located in the middle of the polysilicon portion 23, two N-type heavily doped regions 231A at both ends, and an adjacent N-type heavily doped in the channel region N-type lightly doped region 231B between the impurity regions 231A;
  • a gate insulating layer 24 disposed on the polysilicon portion 23 and the buffer layer 22;
  • the gate 25 is disposed on the gate insulating layer 24, the width of the gate 25 is smaller than the width of the polysilicon portion 23, and the gate 25 covers the channel region 232 of the polysilicon portion 23 and the N-type lightly doped region 231B;
  • An interlayer insulating layer 26 disposed on the gate electrode 25 and the gate insulating layer 24;
  • a source 271 disposed on the interlayer insulating layer 26 and electrically connected to the N-type heavily doped region 231A at one end of the polysilicon portion 23;
  • a drain electrode 272 is disposed on the interlayer insulating layer 26 and is electrically connected to the N-type heavily doped region 231A at the other end of the polysilicon portion 23.
  • the low temperature polysilicon TFT substrate may further include:
  • a passivation layer 201 disposed on the common electrode layer 29 and the flat layer 28;
  • a pixel electrode 202 is disposed on the passivation layer 201.
  • a first via hole (P1 and P2) is disposed above the gate insulating layer 24 and the interlayer insulating layer 26 corresponding to the N-type heavily doped region 231A, and the source electrode 271 and the drain electrode 272 respectively pass through the first via hole (P1 and P2).
  • a via (P1 and P2) is electrically connected to the N-type heavily doped region 231A.
  • a second via Q is disposed above the corresponding drain 272 on the flat layer 28 and the passivation layer 201, and the pixel electrode 202 is electrically connected to the drain 272 via the second via Q.
  • substrate 200 can be a glass substrate.
  • the light shielding portion 21 may be provided by an opaque metal (such as Al, Ag, Cu, Mo, Au, etc.) or a laminate, or may be made of an alloy of each metal to prevent the backlight from directly illuminating the TFT to affect the logic circuit of the substrate. .
  • the buffer layer 22 can be a composite layer of a silicon nitride layer and a silicon oxide layer.
  • the silicon nitride layer has a thickness of 40 to 100 nm
  • the silicon oxide layer has a thickness of 100 to 200 nm.
  • the polysilicon portion 23 may be doped with B ions as a whole to adjust the threshold voltage (Vth) of the N-TFT.
  • the N-type lightly doped region 231B may be doped with a small amount of P ions, and the N-type heavily doped region 231B is doped with more P ions.
  • the width of the N-type lightly doped region 231B can be designed to be about 1.5 ⁇ m.
  • the gate insulating layer 24 can be made of silicon nitride or silicon oxide.
  • the material of the gate 25 can be molybdenum.
  • the interlayer insulating layer 26 can be a silicon nitride layer, a silicon oxide layer, or a combination of both.
  • source 271 and drain 272 can be a molybdenum/aluminum/molybdenum composite layer.
  • the flat layer 28 is an insulating material layer such as a silicon nitride layer, a silicon oxide layer or the like.
  • the common electrode 29 can be made of a transparent conductive metal oxide or a transparent conductive metal film.
  • the material of the passivation layer 201 can be silicon nitride, silicon oxide, or the like.
  • the material of the pixel electrode 202 can be indium tin oxide (ie, ITO) to enhance the conductivity of the pixel electrode.
  • the low temperature polysilicon TFT substrate changes the N-TFT structure in the low temperature polysilicon TFT substrate to an N-TFT structure in which the gate and the lightly doped region overlap, since the gate voltage will be
  • the N-type lightly doped region induces a charge, and the impedance of the N-type lightly doped region changes with the gate voltage, thereby effectively suppressing the kink effect of the N-TFT drain output and improving the operating characteristics of the device.

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Abstract

一种低温多晶硅TFT基板及其制作方法。该方法包括：在基板（100）上依次形成遮光部（111）、缓冲层（12）及岛状多晶硅部（131），对岛状多晶硅部（131）两侧进行离子轻掺杂，形成掺杂区（1311）和沟道区（1312）；依次形成栅极绝缘层（15）和栅极（16）；对未被栅极（16）覆盖的掺杂区进行离子重掺杂，形成N型重掺杂区（1311A）和N型轻掺杂区（1311B）；在栅极（161）上形成层间绝缘层（17），及与N型重掺杂区电连接的源漏极（181，182）。

Description

低温多晶硅TFT基板及其制作方法 技术领域
本发明涉及液晶显示面板制作领域，特别是涉及一种低温多晶硅TFT基板及其制作方法。
 背景技术
在信息社会的当代，作为可视信息传输媒介的显示器的重要性在进一步加强，为了在未来占据主导地位，显示器正朝着更轻、更薄、更低能耗、更低成本以及更好图像质量的趋势发展。
低温多晶硅 (Low Temperature Poly-silicon，LTPS) 技术是新一代 TFT （Thin Film Transistor，薄膜晶体管）基板的制造技术，与传统非晶硅 (a-Si) 技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。
一般地，N型低温多晶硅TFT（Thin Film Transistor，薄膜晶体管）基板，通常为自准直的N-TFT结构，其栅极覆盖位于其下方的多晶硅未掺杂区（即沟道区），而与掺杂区不重叠。然而，这种低温多晶硅TFT基板的设计中，由于其轻掺杂区的阻抗是恒定不变无法调节的，在较高的漏极电压下，将使得漏极区域存在严重的碰撞电离，从而产生翘曲效应（kink effect），导致对器件的长期稳定工作造成不利影响。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种改进的彩膜基板和液晶显示器。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种低温多晶硅TFT基板的制作方法，包括：
提供一基板；
在所述基板上设置多个遮光部、以及形成一缓冲层；
在所述缓冲层上沉积一低温多晶硅层，对所述低温多晶硅层进行图形化处理，以在每一所述遮光部对应上方形成一岛状多晶硅部，并对每一所述岛状多晶硅部进行无差别的整面离子掺杂；
在每一所述多晶硅部上涂布光阻，对光阻进行图形化处理形成多个光阻部，以所述光阻部为掩膜对每一所述岛状多晶硅部两侧进行离子轻掺杂，形成位于每一所述岛状多晶硅部两侧的两个掺杂区以及位于两侧掺杂区之间的一沟道区；
去除多个所述光阻部，在多个所述岛状多晶硅部上依次形成一栅极绝缘层和一第一金属层，并对所述第一金属层进行图形化处理，以在每一所述岛状多晶硅部对应上方形成一栅极，其中，所述栅极的宽度小于所述岛状多晶硅部的宽度，所述栅极覆盖所述沟道区，且所述栅极的两端均超出所述沟道区的两端一段距离并覆盖部分所述掺杂区；
以所述栅极为掩膜对未被所述栅极覆盖的每一所述掺杂区进行离子重掺杂，形成位于每一所述岛状多晶硅部两侧的两个N型重掺杂区，并将位于所述N型重掺杂区与所述沟道区之间的掺杂区作为N型轻掺杂区；
在所述栅极上形成一层间绝缘层、及与每一所述N型重掺杂区电连接的一源极和一漏极。
在一些实施例中，以所述光阻部为掩膜对每一所述岛状多晶硅部两侧进行离子轻掺杂的离子为P离子。
在一些实施例中，以所述栅极为掩膜对未被所述栅极覆盖的每一所述掺杂区进行离子重掺杂的离子为P离子。
在一些实施例中，其中，对每一所述岛状多晶硅部进行无差别的整面离子掺杂的离子为B离子。
在一些实施例中，在所述基板上设置多个遮光部的步骤包括：
利用物理气相沉积技术在所述基板上沉积一第二金属层并涂布光阻；
通过黄光工艺和刻蚀工艺，对所述第二金属层进行刻蚀，形成相互间隔的多个遮光部。
在一些实施例中，在所述栅极上形成一层间绝缘层、及与每一所述N型重掺杂区电连接的一源极和一漏极的步骤包括：
通过化学气相沉积技术整面沉积一层间绝缘层；
通过黄光制程在所述层间绝缘层、所述栅极绝缘层上对应在每一所述N型重掺杂区的上方形成两个第一过孔，以使所述N型重掺杂区露出；
整面沉积一第三金属层，对所述第三金属层进行图案化处理形成多个源极和多个漏极，每一所述源极和每一所述漏极分别经由所述第一过孔与所述N型重掺杂区电连接。
在一些实施例中，在所述基板上依次形成一栅极绝缘层和一第一金属层，并对所述第一金属层进行图形化处理，以在每一所述岛状多晶硅部对应上方形成一栅极的步骤包括：
通过化学气相沉积技术在所述基板上沉积一绝缘层；
通过物理气相沉积技术在所述基板上沉积一第一金属层并涂布光阻；
通过黄光工艺和刻蚀工艺，对所述第一金属层进行刻蚀，形成相互间隔的多个栅极。
在一些实施例中，在所述栅极上形成一层间绝缘层、及与每一所述N型重掺杂区电连接的一源极和一漏极之后，所述方法还包括：
在所述层间绝缘层、所述源极及所述漏极上依次沉积一平坦层和一公共电极材料层；
通过黄光工艺和刻蚀工艺去除位于每一所述漏极上方的公共电极材料层，以在所述平坦层上形成一公共电极；
在所述平坦层和所述公共电极上形成一钝化层；
通过黄光制程在所述平坦层、所述钝化层上对应在每一所述漏极的上方形成一第二过孔，以使所述漏极露出；
整面沉积一像素电极材料层，对所述像素电极材料层图形化处理，以在所述钝化层上形成多个像素电极，每一所述像素电极通过所述第二过孔与所述漏极电连接。
在一些实施例中，所述像素电极的制备材料为氧化铟锡。
本发明还提供一种低温多晶硅TFT基板的制作方法，包括：
提供一基板；
在所述基板上设置多个遮光部、以及形成一缓冲层；
在所述缓冲层上沉积一低温多晶硅层，对所述低温多晶硅层进行图形化处理，以在每一所述遮光部对应上方形成一岛状多晶硅部，并对每一所述岛状多晶硅部进行无差别的整面离子掺杂；
在每一所述多晶硅部上涂布光阻，对光阻进行图形化处理形成多个光阻部，以所述光阻部为掩膜对每一所述岛状多晶硅部两侧进行离子轻掺杂，形成位于每一所述岛状多晶硅部两侧的两个掺杂区以及位于两侧掺杂区之间的一沟道区；
去除多个所述光阻部，在多个所述岛状多晶硅部上依次形成一栅极绝缘层和一第一金属层，并对所述第一金属层进行图形化处理，以在每一所述岛状多晶硅部对应上方形成一栅极，其中，所述栅极的宽度小于所述岛状多晶硅部的宽度，所述栅极覆盖所述沟道区，且所述栅极的两端均超出所述沟道区的两端一段距离并覆盖部分所述掺杂区；
以所述栅极为掩膜对未被所述栅极覆盖的每一所述掺杂区进行离子重掺杂，形成位于每一所述岛状多晶硅部两侧的两个N型重掺杂区，并将位于所述N型重掺杂区与所述沟道区之间的掺杂区作为N型轻掺杂区；
整面沉积一层间绝缘层；
在所述层间绝缘层、所述栅极绝缘层上对应在每一所述N型重掺杂区的上方形成两个第一过孔，以使所述N型重掺杂区露出；
整面沉积一第三金属层，对所述第三金属层进行图案化处理形成多个源极和多个漏极，每一所述源极和每一所述漏极分别经由所述第一过孔与所述N型重掺杂区电连接；
在所述层间绝缘层、所述源极及所述漏极上依次形成一平坦层、一公共电极、一钝化层、及与每一所述漏极电连接的一像素电极。
在一些实施例中，以所述光阻部为掩膜对每一所述岛状多晶硅部两侧进行离子轻掺杂的离子为P离子；以所述栅极为掩膜对未被所述栅极覆盖的每一所述掺杂区进行离子重掺杂的离子为P离子。
在一些实施例中，对每一所述岛状多晶硅部进行无差别的整面离子掺杂的离子为B离子。
在一些实施例中，在所述基板上设置多个遮光部的步骤包括：
利用物理气相沉积技术在所述基板上沉积第二金属层并涂布光阻；
通过黄光工艺和刻蚀工艺，对所述第二金属层进行刻蚀，形成相互间隔的多个遮光部。
在一些实施例中，在所述基板上依次形成一栅极绝缘层和一第一金属层，并对所述第一金属层进行图形化处理，以在每一所述岛状多晶硅部对应上方形成一栅极的步骤包括：
通过化学气相沉积技术在所述基板上沉积一绝缘层；
通过物理气相沉积技术在所述基板上沉积一第一金属层并涂布光阻；
通过黄光工艺和刻蚀工艺，对所述第一金属层进行刻蚀，形成相互间隔的多个栅极。
在一些实施例中，在所述层间绝缘层、所述源极及所述漏极上依次形成一平坦层、一公共电极、一钝化层、及与每一所述漏极电连接的一像素电极的步骤包括：
在所述层间绝缘层、所述源极及所述漏极上依次沉积一平坦层和一公共电极材料层；
通过黄光工艺和刻蚀工艺去除位于每一所述漏极上方的公共电极材料层，以在所述平坦层上形成一公共电极；
在所述平坦层和所述公共电极上形成一钝化层；
通过黄光制程在所述平坦层、所述钝化层上对应在每一所述漏极的上方形成一第二过孔，以使所述漏极露出；
整面沉积一像素电极材料层，对所述像素电极材料层图形化处理，以在所述钝化层上形成多个像素电极，每一所述像素电极通过所述第二过孔与所述漏极电连接。
在一些实施例中，整面沉积一层间绝缘层所采用的技术为化学气相沉积技术。
在一些实施例中，所述像素电极的制备材料为氧化铟锡。
本发明还提供一种低温多晶硅TFT基板，其中，包括：
一基板；
多个遮光部，其设置在所述基板上；
一缓冲层，其设置在所述基板和所述遮光部上；
多个多晶硅部，其设置在所述缓冲层上，每一所述多晶硅部包括：位于所述多晶硅部中间的一沟道区、位于每一多晶硅部两端的两个N型重掺杂区、及位于所述沟道区与相邻的所述N型重掺杂区之间的N型轻掺杂区；
一栅极绝缘层，其设置在所述多晶硅部和所述缓冲层上；
多个栅极，其设置在所述栅极绝缘层上，所述栅极的宽度小于所述多晶硅部的宽度，且所述栅极覆盖所述沟道区及所述N型轻掺杂区；
一层间绝缘层，其设置在所述多个栅极和所述栅极绝缘层上；
多个源极，其设置在所述层间绝缘层上，每一所述源极与所述多晶硅部一端的N型重掺杂区电连接；
多个漏极，其设置在所述层间绝缘层上，每一所述漏极与所述多晶硅部另一端的N型重掺杂区电连接。
在一些实施例中，所述栅极绝缘、及所述层间绝缘层上对应每一所述N型重掺杂区的上方设有两个第一过孔，每一所述源极与每一所述漏极分别经由所述第一过孔与所述N型重掺杂区电连接。
在一些实施例中，所述低温多晶硅TFT基板还包括：
一平坦层，其设置在所述源极、所述漏极和所述层间绝缘层上；
一公共电极，其设置在所述平坦层上；
一钝化层，其设置在所述公共电极和所述平坦层上；
多个像素电极，其设置在所述钝化层上，所述平坦层、所述钝化层上对应每一所述漏极的上方设有一第二过孔，每一像素电极经由所述第二过孔与所述漏极电连接。
 有益效果
本发明提供的低温多晶硅TFT的制作方法包括：在基板上依次形成遮光部、缓冲层及岛状多晶硅部，对岛状多晶硅部两侧进行离子轻掺杂，形成掺杂区和沟道区；依次形成栅极绝缘层和栅极，栅极覆盖沟道区且其两端均超出沟道区的两端一段距离并覆盖部分掺杂区；对未被栅极覆盖的掺杂区进行离子重掺杂，形成N型重掺杂区和N型轻掺杂区；在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源漏极。该方案将低温多晶硅TFT基板中的N-TFT结构更改为栅极和轻掺杂区有重叠的N-TFT结构，从而可通过栅极电压控制轻掺杂区的阻抗变化，以有效抑制N型TFT产生翘曲效应，提升器件的工作特性。
 附图说明
图1为本发明优选实施例中低温多晶硅TFT基板的制作方法的流程示意图。
图2A-图2C为本发明优选实施例中低温多晶硅TFT基板的制程示意图。
图3为本发明优选实施例中低温多晶硅TFT基板的一种结构示意图。
图4为本发明优选实施例中低温多晶硅TFT器件的一种结构示意图。
图5为本发明优选实施例中低温多晶硅TFT器件的另一种结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在附图中，组件相似的模块是以相同标号表示。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
参阅图1，图1为本发明优选实施例中低温多晶硅TFT基板的制作方法的流程示意图。如图1所示，本优选实施例的低温多晶硅TFT基板的制作方法，包括：
S101、提供一基板，在基板上设置遮光部，以及形成缓冲层；
S102、在缓冲层上沉积低温多晶硅层，对低温多晶硅层进行图形化处理，以在遮光部对应上方形成岛状多晶硅部，并对岛状多晶硅部进行无差别的整面离子掺杂；
S103、在岛状多晶硅部上涂布光阻，对该光阻进行图形化处理形成光阻部，以该光阻部为掩膜对岛状多晶硅部两侧进行离子轻掺杂，形成位于岛状多晶硅部两侧的掺杂区以及位于两侧掺杂区之间的沟道区；
S104、去除光阻部，在岛状多晶硅部上依次形成栅极绝缘层和第一金属层，并对第一金属层进行图形化处理，以在岛状多晶硅部对应上方形成栅极，其中，所述栅极的宽度小于岛状多晶硅部的宽度，栅极覆盖岛状多晶硅部的沟道区，且栅极的两端均超出沟道区的两端一段距离并覆盖部分掺杂区；
S105、以栅极为掩膜对未被栅极覆盖的掺杂区进行离子重掺杂，形成位于岛状多晶硅部两侧的N型重掺杂区，并将位于N型重掺杂区与沟道区之间的掺杂区作为N型轻掺杂区；
S106、在栅极上形成层间绝缘层，及与N型重掺杂区电连接的源极和漏极。
以下将结合图2A-图2C对以上低温多晶硅TFT基板的制作方法的步骤进行详细描述。
步骤S101中，该基板可为玻璃基板。遮光部的制备材料可以为不透明的金属材料，以防止背光源光线直接照射到TFT对基板的逻辑电路造成影响，可由不透明的金属（如Al、Ag、Cu、Mo、Au等）或叠层设置，还可由各金属的合金制成。在一些实施方式中，参考图2A，可利用PVD（Physical Vapor Deposition，物理气相沉积）技术在基板100上沉积第二金属层11，然后涂布光阻，通过黄光工艺和刻蚀工艺，对第二金属层11进行刻蚀，形成相互间隔的多个遮光部111。
然后，可采用CVD（Chemical Vapor Deposition，化学气相沉积）技术整面沉积绝缘材料，以在遮光部111和基板100上形成缓冲层12。其中，缓冲层12为氮化硅层与氧化硅层的复合层。在一些实施方式中，氮化硅层的厚度为40～100nm，氧化硅层的厚度可100～200nm。
在步骤S102中，参考图2A，整面沉积低温多晶硅层13。在一些实施方式中，可采用黄光工艺和刻蚀工艺对低温多晶硅层13进行图形化处理，以在遮光部111对应上方形成岛状多晶硅部131。然后对岛状多晶硅部131进行无差别的整面离子掺杂（离子注入），以调整N-TFT的阈值电压（Vth）。其中，对岛状多晶硅部131进行整面离子掺杂的离子为B离子。
在步骤S103中，继续参考图2A，可采用涂布的方式在缓冲层12上涂布光阻，然后通过全曝光工艺对该光阻进行图形化处理形成光阻部14。其中，该光阻部14形成于岛状多晶硅部131的上方，且位于该岛状多晶硅部131的中间部分，该光阻部14宽度约为岛状多晶硅部131宽度的1/3~1/2之间。
以该光阻部14为掩膜对岛状多晶硅部131的两侧进行离子轻掺杂，形成位于岛状多晶硅部131两侧的掺杂区1311以及位于两侧掺杂1311区之间的沟道区（即未掺杂区）1312。其中，以光阻部14为掩膜对岛状多晶硅部131两侧进行离子轻掺杂的离子为P离子。
参考图2A，在步骤S104中，可采用光阻剥离工艺或光阻灰化去除光阻部14。然后，可采用CVD技术在基板100上沉积栅极绝缘层15，再采用PVD技术在栅极绝缘层15上形成第一金属层16。其中，栅极绝缘层15的制备材料可为氮化硅或氧化硅；第一金属层的材料可以为钼。
然后，在第一金属层16涂布一层厚度均匀的光阻，通过黄光工艺和刻蚀工艺对第一金属层16进行刻蚀，以在岛状多晶硅部131对应上方形成相互间隔的多个栅极161。其中，栅极161的宽度小于岛状多晶硅部131的宽度，栅极161覆盖岛状多晶硅部的沟道区1312，且栅极161的两端均超出沟道区1312的两端一段距离，从而覆盖部分掺杂区1311。其中，栅极161的两端均超出沟道区1312的两端的一段距离可约为1~2μm。
在步骤S105中，参考图2A和图2B，以栅极161为掩膜对未被栅极覆盖的掺杂区1311进行离子重掺杂，形成位于岛状多晶硅部131两侧的N型重掺杂区1311A，并将位于N型重掺杂区1311A与沟道区1312之间的掺杂区1311作为N型轻掺杂区1311B，其宽度可为1.5μm左右。其中，以栅极161为掩膜对未被栅极161覆盖的掺杂区1311进行离子重掺杂的离子为P离子。
在步骤S106中，可采用CVD技术整面沉积绝缘材料，以在栅极绝缘层15和栅极161上形成层间绝缘层17。其中，层间绝缘层17可为氮化硅层、氧化硅层、或二者的组合。
随后，通过黄光制程在该层间绝缘层17、栅极绝缘层15上对应在N型重掺杂区1311A的上方形成第一过孔，以使两个N型重掺杂区1311A露出。其中，第一过孔包括位于栅极161一侧的过孔P1和位于另一侧形成的过孔P2，该N型重掺杂区1311A可以全部露出，也可以部分露出。
然后，可采用PVD技术整面沉积第三金属层18。在通过黄光工艺、刻蚀工艺对第三金属层18进行图案化处理，以在层间绝缘层17上形成源极181和漏极182，使得源极181经由过孔P1与岛状多晶硅部131一侧的N型重掺杂区1311A电连接，漏极182经由过孔P2与岛状多晶硅部131另一侧的N型重掺杂区1311A电连接。其中，源极181和漏极182可为钼/铝/钼复合层。
参考图2B和图2C，在一些实施例中，在步骤S106之后，还可以在上述形成的TFT基板上依次形成平坦层19、公共电极101、钝化层102，以及在钝化层102上设置像素电极1031。
具体地，可通过CVD技术先在层间绝缘层17、源极181及漏极182上整面沉积平坦层19，然后在平坦层19上沉积公共电极材料层101。随后，可在公共电极材料层101上涂布光阻，通过黄光工艺和刻蚀工艺去除对应于漏极182上方的公共电极材料层101，以在平坦层19上形成公共电极1011。其中，平坦层19为绝缘材料层，公共电极1011可由透明导电金属氧化物或者透明导电金属薄膜制成。
然后，可通过CVD技术在平坦层19和公共电极1011上形成钝化层102。该钝化层102的制备材料可以为氮化硅、氧化硅等。再采用黄光制程在平坦层19、钝化层102上对应在漏极182的上方形成第二过孔Q，以使漏极182露出。其中，漏极182可部分露出。
在一些实施例中，可采用PVD技术整面沉积像素电极材料层103，然后，通过黄光工艺和刻蚀工艺对像素电极材料层103图形化处理，以在钝化层102上形成像素电极1031，使得该像素电极1031通过第二过孔Q与漏极182电连接。从而完成低温多晶硅TFT基板的制作。
实际应用中，像素电极1031的制备材料可为氧化铟锡（即ITO），以增强像素电极的导电性。
由上可知，本发明实施例提供的低温多晶硅TFT基板的制作方法，将低温多晶硅TFT基板中的N-TFT结构更改为栅极和轻掺杂区有重叠的N-TFT结构，从而可通过栅极电压控制轻掺杂区的阻抗变化，以有效抑制N型TFT产生翘曲效应，提升器件的工作特性。
本发明实施例还提供一种低温多晶硅TFT基板。其中，低温多晶硅TFT基板包括有多个TFT，每个TFT对应一遮光部、一低温多晶硅部、一栅极、一源极、以及一漏极。
参考图3，该低温多晶硅TFT基板包括：
基板200；
遮光部21，其设置在基板200上；
缓冲层22，其设置在基板200和遮光部21上；
多晶硅部23，其设置在缓冲层22上，包括位于多晶硅部23中间的沟道区232、位于两端的两个N型重掺杂区231A、及位于沟道区与相邻的N型重掺杂区231A之间的N型轻掺杂区231B；
栅极绝缘层24，其设置在多晶硅部23和缓冲层22上；
栅极25，其设置在栅极绝缘层24上，栅极25的宽度小于多晶硅部23的宽度，且栅极25覆盖多晶硅部23的沟道区232及N型轻掺杂区231B；
层间绝缘层26，其设置在栅极25和栅极绝缘层24上；
源极271，其设置在层间绝缘层26上，并与多晶硅部23一端的N型重掺杂区231A电连接；
漏极272，其设置在层间绝缘层26上，并与多晶硅部23另一端的N型重掺杂区231A电连接。
继续参考图3，在一些实施例中，该低温多晶硅TFT基板还可以包括：
平坦层28，其设置在源极271、漏极272和层间绝缘层26上；
公共电极29，其设置在平坦层28上；
钝化层201，其设置在公共电极层29和平坦层28上；
像素电极202，其设置在钝化层201上。
其中，参考图4，栅极绝缘24、及层间绝缘层26上对应N型重掺杂区231A的上方设有第一过孔（P1和P2），源极271与漏极272分别经由第一过孔（P1和P2）与N型重掺杂区231A电连接。
在一些实施例中，参考图5，平坦层28、钝化层201上对应漏极272的上方设有第二过孔Q，像素电极202经由第二过孔Q与漏极272电连接。
在一些实施例中，基板200可为玻璃基板。遮光部21可由不透明的金属（如Al、Ag、Cu、Mo、Au等）或叠层设置，还可由各金属的合金制成，以防止背光源光线直接照射到TFT对基板的逻辑电路造成影响。
在一些实施例中，缓冲层22可为氮化硅层与氧化硅层的复合层。在一些实施方式中，氮化硅层的厚度为40～100nm，氧化硅层的厚度可100～200nm。
在本发明实施例中，多晶硅部23整体可掺杂有B离子，以调整N-TFT的阈值电压（Vth）。其N型轻掺杂区231B可掺杂有少量P离子，其N型重掺杂区231B掺杂有较多的P离子。在一些实施方式中，N型轻掺杂区231B的宽度可设计为约为1.5μm左右。
在一些实施例中，栅极绝缘层24的制备材料可为氮化硅或氧化硅。而栅极25的制备材料可为钼。
在一些实施方式中，层间绝缘层26可为氮化硅层、氧化硅层、或二者的组合。
在一些实施例中，源极271和漏极272可为钼/铝/钼复合层。
本发明实施例中，平坦层28为绝缘材料层，如氮化硅层、氧化硅层等。而公共电极29则可由透明导电金属氧化物或者透明导电金属薄膜制成。
在一些实施例中，钝化层201的制备材料可以为氮化硅、氧化硅等。而像素电极202的制备材料可为氧化铟锡（即ITO），以增强像素电极的导电性。
由上可知，本发明实施例提供的低温多晶硅的TFT基板，将低温多晶硅TFT基板中的N-TFT结构更改为栅极和轻掺杂区有重叠的N-TFT结构，由于栅极电压会在N型轻掺杂区感应出电荷，该N型轻掺杂区的阻抗会随栅极电压而变化，从而能有效抑制N-TFT漏极输出的扭结效应，提升器件的工作特性。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种低温多晶硅TFT基板的制作方法，其中，包括：
    提供一基板；
    在所述基板上设置多个遮光部、以及形成一缓冲层；
    在所述缓冲层上沉积一低温多晶硅层，对所述低温多晶硅层进行图形化处理，以在每一所述遮光部对应上方形成一岛状多晶硅部，并对每一所述岛状多晶硅部进行无差别的整面离子掺杂；
    在每一所述多晶硅部上涂布光阻，对光阻进行图形化处理形成多个光阻部，以所述光阻部为掩膜对每一所述岛状多晶硅部两侧进行离子轻掺杂，形成位于每一所述岛状多晶硅部两侧的两个掺杂区以及位于两侧掺杂区之间的一沟道区；
    去除多个所述光阻部，在多个所述岛状多晶硅部上依次形成一栅极绝缘层和一第一金属层，并对所述第一金属层进行图形化处理，以在每一所述岛状多晶硅部对应上方形成一栅极，其中，所述栅极的宽度小于所述岛状多晶硅部的宽度，所述栅极覆盖所述沟道区，且所述栅极的两端均超出所述沟道区的两端一段距离并覆盖部分所述掺杂区；
    以所述栅极为掩膜对未被所述栅极覆盖的每一所述掺杂区进行离子重掺杂，形成位于每一所述岛状多晶硅部两侧的两个N型重掺杂区，并将位于所述N型重掺杂区与所述沟道区之间的掺杂区作为N型轻掺杂区；
    在所述栅极上形成一层间绝缘层、及与每一所述N型重掺杂区电连接的一源极和一漏极。
  2. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，以所述光阻部为掩膜对每一所述岛状多晶硅部两侧进行离子轻掺杂的离子为P离子。
  3. 如权利要求2所述的低温多晶硅TFT基板的制作方法，其中，以所述栅极为掩膜对未被所述栅极覆盖的每一所述掺杂区进行离子重掺杂的离子为P离子。
  4. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，对每一所述岛状多晶硅部进行无差别的整面离子掺杂的离子为B离子。
  5. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，在所述基板上设置多个遮光部的步骤包括：
    利用物理气相沉积技术在所述基板上沉积一第二金属层并涂布光阻；
    通过黄光工艺和刻蚀工艺，对所述第二金属层进行刻蚀，形成相互间隔的多个遮光部。
  6. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，在所述栅极上形成一层间绝缘层、及与每一所述N型重掺杂区电连接的一源极和一漏极的步骤包括：
    通过化学气相沉积技术整面沉积一层间绝缘层；
    通过黄光制程在所述层间绝缘层、所述栅极绝缘层上对应在每一所述N型重掺杂区的上方形成两个第一过孔，以使所述N型重掺杂区露出；
    整面沉积一第三金属层，对所述第三金属层进行图案化处理形成多个源极和多个漏极，每一所述源极和每一所述漏极分别经由所述第一过孔与所述N型重掺杂区电连接。
  7. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，在所述基板上依次形成一栅极绝缘层和一第一金属层，并对所述第一金属层进行图形化处理，以在每一所述岛状多晶硅部对应上方形成一栅极的步骤包括：
    通过化学气相沉积技术在所述基板上沉积一绝缘层；
    通过物理气相沉积技术在所述基板上沉积一第一金属层并涂布光阻；
    通过黄光工艺和刻蚀工艺，对所述第一金属层进行刻蚀，形成相互间隔的多个栅极。
  8. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，在所述栅极上形成一层间绝缘层、及与每一所述N型重掺杂区电连接的一源极和一漏极之后，所述方法还包括：
    在所述层间绝缘层、所述源极及所述漏极上依次沉积一平坦层和一公共电极材料层；
    通过黄光工艺和刻蚀工艺去除位于每一所述漏极上方的公共电极材料层，以在所述平坦层上形成一公共电极；
    在所述平坦层和所述公共电极上形成一钝化层；
    通过黄光制程在所述平坦层、所述钝化层上对应在每一所述漏极的上方形成一第二过孔，以使所述漏极露出；
    整面沉积一像素电极材料层，对所述像素电极材料层图形化处理，以在所述钝化层上形成多个像素电极，每一所述像素电极通过所述第二过孔与所述漏极电连接。
  9. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述像素电极的制备材料为氧化铟锡。
  10. 一种低温多晶硅TFT基板的制作方法，其中，包括：
    提供一基板；
    在所述基板上设置多个遮光部、以及形成一缓冲层；
    在所述缓冲层上沉积一低温多晶硅层，对所述低温多晶硅层进行图形化处理，以在每一所述遮光部对应上方形成一岛状多晶硅部，并对每一所述岛状多晶硅部进行无差别的整面离子掺杂；
    在每一所述多晶硅部上涂布光阻，对光阻进行图形化处理形成多个光阻部，以所述光阻部为掩膜对每一所述岛状多晶硅部两侧进行离子轻掺杂，形成位于每一所述岛状多晶硅部两侧的两个掺杂区以及位于两侧掺杂区之间的一沟道区；
    去除多个所述光阻部，在多个所述岛状多晶硅部上依次形成一栅极绝缘层和一第一金属层，并对所述第一金属层进行图形化处理，以在每一所述岛状多晶硅部对应上方形成一栅极，其中，所述栅极的宽度小于所述岛状多晶硅部的宽度，所述栅极覆盖所述沟道区，且所述栅极的两端均超出所述沟道区的两端一段距离并覆盖部分所述掺杂区；
    以所述栅极为掩膜对未被所述栅极覆盖的每一所述掺杂区进行离子重掺杂，形成位于每一所述岛状多晶硅部两侧的两个N型重掺杂区，并将位于所述N型重掺杂区与所述沟道区之间的掺杂区作为N型轻掺杂区；
    整面沉积一层间绝缘层；
    在所述层间绝缘层、所述栅极绝缘层上对应在每一所述N型重掺杂区的上方形成两个第一过孔，以使所述N型重掺杂区露出；
    整面沉积一第三金属层，对所述第三金属层进行图案化处理形成多个源极和多个漏极，每一所述源极和每一所述漏极分别经由所述第一过孔与所述N型重掺杂区电连接；
    在所述层间绝缘层、所述源极及所述漏极上依次形成一平坦层、一公共电极、一钝化层、及与每一所述漏极电连接的一像素电极。
  11. 如权利要求9所述的低温多晶硅TFT基板的制作方法，其中，以所述光阻部为掩膜对每一所述岛状多晶硅部两侧进行离子轻掺杂的离子为P离子；以所述栅极为掩膜对未被所述栅极覆盖的每一所述掺杂区进行离子重掺杂的离子为P离子。
  12. 如权利要求11所述的低温多晶硅TFT基板的制作方法，其中，对每一所述岛状多晶硅部进行无差别的整面离子掺杂的离子为B离子。
  13. 如权利要求10所述的低温多晶硅TFT基板的制作方法，其中，在所述基板上设置多个遮光部的步骤包括：
    利用物理气相沉积技术在所述基板上沉积第二金属层并涂布光阻；
    通过黄光工艺和刻蚀工艺，对所述第二金属层进行刻蚀，形成相互间隔的多个遮光部。
  14. 如权利要求10所述的低温多晶硅TFT基板的制作方法，其中，在所述基板上依次形成一栅极绝缘层和一第一金属层，并对所述第一金属层进行图形化处理，以在每一所述岛状多晶硅部对应上方形成一栅极的步骤包括：
    通过化学气相沉积技术在所述基板上沉积一绝缘层；
    通过物理气相沉积技术在所述基板上沉积一第一金属层并涂布光阻；
    通过黄光工艺和刻蚀工艺，对所述第一金属层进行刻蚀，形成相互间隔的多个栅极。
  15. 如权利要求10所述的低温多晶硅TFT基板的制作方法，其中，在所述层间绝缘层、所述源极及所述漏极上依次形成一平坦层、一公共电极、一钝化层、及与每一所述漏极电连接的一像素电极的步骤包括：
    在所述层间绝缘层、所述源极及所述漏极上依次沉积一平坦层和一公共电极材料层；
    通过黄光工艺和刻蚀工艺去除位于每一所述漏极上方的公共电极材料层，以在所述平坦层上形成一公共电极；
    在所述平坦层和所述公共电极上形成一钝化层；
    通过黄光制程在所述平坦层、所述钝化层上对应在每一所述漏极的上方形成一第二过孔，以使所述漏极露出；
    整面沉积一像素电极材料层，对所述像素电极材料层图形化处理，以在所述钝化层上形成多个像素电极，每一所述像素电极通过所述第二过孔与所述漏极电连接。
  16. 如权利要求10所述的低温多晶硅TFT基板的制作方法，其中，整面沉积一层间绝缘层所采用的技术为化学气相沉积技术。
  17. 如权利要求10所述的低温多晶硅TFT基板的制作方法，其中，所述像素电极的制备材料为氧化铟锡。
  18. 一种低温多晶硅TFT基板，其中，包括：
    一基板；
    多个遮光部，其设置在所述基板上；
    一缓冲层，其设置在所述基板和所述遮光部上；
    多个多晶硅部，其设置在所述缓冲层上，每一所述多晶硅部包括：位于所述多晶硅部中间的一沟道区、位于每一多晶硅部两端的两个N型重掺杂区、及位于所述沟道区与相邻的所述N型重掺杂区之间的N型轻掺杂区；
    一栅极绝缘层，其设置在所述多晶硅部和所述缓冲层上；
    多个栅极，其设置在所述栅极绝缘层上，所述栅极的宽度小于所述多晶硅部的宽度，且所述栅极覆盖所述沟道区及所述N型轻掺杂区；
    一层间绝缘层，其设置在所述多个栅极和所述栅极绝缘层上；
    多个源极，其设置在所述层间绝缘层上，每一所述源极与所述多晶硅部一端的N型重掺杂区电连接；
    多个漏极，其设置在所述层间绝缘层上，每一所述漏极与所述多晶硅部另一端的N型重掺杂区电连接。
  19. 如权利要求18所述的低温多晶硅TFT基板，其中，所述栅极绝缘、及所述层间绝缘层上对应每一所述N型重掺杂区的上方设有两个第一过孔，每一所述源极与每一所述漏极分别经由所述第一过孔与所述N型重掺杂区电连接。
  20. 如权利要求18所述的低温多晶硅TFT基板，其中，还包括：
    一平坦层，其设置在所述源极、所述漏极和所述层间绝缘层上；
    一公共电极，其设置在所述平坦层上；
    一钝化层，其设置在所述公共电极和所述平坦层上；
    多个像素电极，其设置在所述钝化层上，所述平坦层、所述钝化层上对应每一所述漏极的上方设有一第二过孔，每一像素电极经由所述第二过孔与所述漏极电连接。
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