WO2020134965A1 - 阵列基板的制造方法、装置及阵列基板 - Google Patents

阵列基板的制造方法、装置及阵列基板 Download PDF

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Publication number
WO2020134965A1
WO2020134965A1 PCT/CN2019/123618 CN2019123618W WO2020134965A1 WO 2020134965 A1 WO2020134965 A1 WO 2020134965A1 CN 2019123618 W CN2019123618 W CN 2019123618W WO 2020134965 A1 WO2020134965 A1 WO 2020134965A1
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layer
doped
amorphous silicon
gate insulating
array substrate
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PCT/CN2019/123618
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English (en)
French (fr)
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莫琼花
卓恩宗
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惠科股份有限公司
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Priority to US17/272,939 priority Critical patent/US11557611B2/en
Publication of WO2020134965A1 publication Critical patent/WO2020134965A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present application relates to the field of thin film transistors, and in particular, to an array substrate manufacturing method, an array substrate manufacturing apparatus, and an array substrate.
  • the liquid crystal display has now become the mainstream of the market, and its working principle is that the liquid crystal will deflect under the drive of electric current, so that light easily passes through, thereby displaying an image.
  • the liquid crystal may be polarized after being driven for a long time, or because of the leakage of the thin film transistor array substrate, the liquid crystal molecules cannot be normally deflected under the control of the signal voltage.
  • IS phenomenon ImageSticking
  • the main purpose of the present application is to provide an array substrate manufacturing method, an array substrate manufacturing apparatus, and an array substrate, Improve the stability of the thin film transistor array substrate.
  • the present application provides a method for manufacturing an array substrate.
  • the method for manufacturing an array substrate includes the following steps:
  • An amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer are sequentially deposited on the gate insulating layer, wherein the The doping concentration of each layer of the doped amorphous silicon layer increases layer by layer from bottom to top;
  • a passivation layer covering a pattern including the amorphous silicon layer, the doped amorphous silicon layer and the metal layer is formed to form an array substrate.
  • the gate insulating layer includes a first gate insulating layer and a second gate insulating layer
  • the step of depositing and forming the gate insulating layer on the pre-formed base substrate and the gate includes:
  • the second gate insulating layer is deposited on the first gate insulating layer, and the deposition rate of the first gate insulating layer is greater than the deposition rate of the second gate insulating layer.
  • the interlayer thickness of the first gate insulating layer is greater than the interlayer thickness of the second gate insulating layer.
  • the amorphous silicon layer and the doped amorphous silicon layer including at least three doped layers are sequentially deposited on the gate insulating layer After the steps of the metal layer, it also includes:
  • the remaining thickness in the channel region is etched in the range of 450 ⁇ -550 ⁇ Of the amorphous silicon layer.
  • the doped amorphous silicon layer includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer whose doping concentration increases layer by layer from bottom to top.
  • the ratio of doping concentrations of the first doped layer, the second doped layer, the third doped layer, and the fourth doped layer is 1:1.5:2.5:3.
  • the interlayer thickness of each of the doped layers is equal.
  • the step of etching the pattern of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer includes:
  • the metal layer, the doped amorphous silicon layer and the amorphous silicon layer in the channel region are sequentially etched to form a channel region of the array substrate.
  • the method further includes:
  • the method further includes:
  • the preset voltage range is 14.6V-15.6V .
  • the present application also provides an array substrate manufacturing apparatus, the array substrate manufacturing apparatus It includes a memory, a processor, and an array substrate manufacturing program stored on the memory and capable of running on the processor.
  • the array substrate manufacturing program is executed by the processor, it is implemented as described above The steps of the manufacturing method of the array substrate.
  • the present application further provides an array substrate, the array substrate includes:
  • the doped amorphous silicon layer includes at least three doped layers, and the doping concentration of each layer of the doped amorphous silicon layer increases layer by layer from bottom to top.
  • the doped amorphous silicon layer includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer in which the doping concentration increases layer by layer from bottom to top.
  • the ratio of doping concentrations of the first doped layer, the second doped layer, the third doped layer, and the fourth doped layer is 1:1.5:2.5:3.
  • the interlayer thickness of each of the doped layers is equal.
  • the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, wherein:
  • the first gate insulating layer is provided on the base substrate and covers the gate
  • the second gate insulating layer is provided on the first gate insulating layer
  • the interlayer thickness of the first gate insulating layer is greater than the interlayer thickness of the second gate insulating layer.
  • the array substrate, the manufacturing method and the device of the array substrate provided by the present application Depositing and forming a gate insulating layer on the pre-formed base substrate and the gate, the gate insulating layer covering the gate; depositing an amorphous silicon layer on the gate insulating layer in sequence, including at least three layers A doped amorphous silicon layer and a metal layer of the doped layer, wherein the doping concentration of each layer of the doped amorphous silicon layer increases layer by layer from bottom to top; the amorphous silicon layer A pattern of the doped amorphous silicon layer and the metal layer; on the gate insulating layer, a pattern covering the amorphous silicon layer, the doped amorphous silicon layer and the metal layer is formed Pattern the passivation layer to form the array substrate. In this way, by improving the stability of the thin film transistor array substrate, the problem that the thin film transistor is prone to image sticking is solved.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate of this application.
  • FIG. 2 is a schematic structural diagram of another embodiment of an array substrate of this application.
  • FIG. 3 is a schematic structural diagram of still another embodiment of the array substrate of the present application.
  • FIG. 4 is a schematic structural diagram of another embodiment of an array substrate of the present application.
  • FIG. 5 is a schematic diagram of a hardware operating environment of a terminal according to an embodiment solution
  • FIG. 6 is a schematic flowchart of an embodiment of a method for manufacturing an array substrate of the present application
  • FIG. 7 is a schematic flowchart of another embodiment of a method for manufacturing an array substrate of the present application.
  • amorphous silicon layer depositing an amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer in sequence on the gate insulating layer, wherein each layer of the doped amorphous silicon layer is doped
  • the impurity concentration increases layer by layer from bottom to top;
  • a passivation layer covering a pattern including the amorphous silicon layer, the doped amorphous silicon layer, and the metal layer is formed to form an array substrate.
  • the array substrate provided by the present application , By forming a doped amorphous silicon layer with at least three layers of doping concentration gradually increasing from bottom to top, to increase the barrier energy barrier of the doped amorphous silicon layer, reduce the leakage current, and enhance the array substrate Stability, solved the thin film transistor easily There is a problem of image retention.
  • FIG. 1 is a schematic structural view of an embodiment of the array substrate of the present application
  • FIG. 2 is a schematic structural interlayer structure of three doped amorphous silicon layers of another embodiment of the array substrate of the present application
  • FIG. 3 is A schematic diagram of an interlayer structure of a four-layer doped amorphous silicon layer according to yet another embodiment of the array substrate of the present application.
  • the array substrate includes a base substrate 10, a gate 20 provided on the base substrate 10, a gate insulating layer 30 provided on the base substrate 10 and covering the gate 20, and provided on the gate An amorphous silicon layer 40 on the polar insulating layer 30, a doped amorphous silicon layer 50 provided on the amorphous silicon layer 40, and a metal layer 60 provided on the doped amorphous silicon layer 50, And a passivation layer 70 provided on the gate insulating layer 30 and covering the amorphous silicon layer 40, the doped amorphous silicon layer 50, and the metal layer 60,
  • the crystalline silicon layer 50 includes at least three doped layers, and the doping concentration of each layer of the doped amorphous silicon layer increases layer by layer from bottom to top.
  • the array substrate may also be a pixel electrode (not shown in the figure) including a passivation via through the passivation layer.
  • the metal layer includes a source electrode and a drain electrode (not shown in the figure), and the material of the metal layer may be a stack combination of one or more of manganese, molybdenum, titanium, aluminum, and copper;
  • the amorphous silicon layer may be A-Si amorphous silicon material;
  • the material of the gate insulating layer may be silicon oxide and/or silicon nitride;
  • the gate may be one of molybdenum, titanium, aluminum and copper Or a variety of stack combinations;
  • the base substrate may be a glass substrate.
  • the interlayer thickness of each of the doped layers is equal.
  • the doped amorphous silicon layer may be N-type (Negative )
  • the doped amorphous silicon layer may also be a P-type (positive) doped amorphous silicon layer.
  • the doped amorphous silicon layer is an N-type doped amorphous silicon layer.
  • the doped amorphous silicon layer is provided with three doped layers with a doping concentration increasing layer by layer from bottom to top, referring to FIG. 2
  • the doped amorphous silicon layer includes a first doped layer 51, a second doped layer 52, and a third doped layer 53 whose doping concentration increases layer by layer from bottom to top.
  • the first doped layer 51 is provided on the amorphous silicon layer 40
  • the second doped layer 52 is provided on the first doped layer 51
  • the third doped layer 53 is provided on the second doped layer 52
  • the metal layer 60 is provided on the third doped layer 53.
  • the ratio of the doped layers of each layer may also be in the second doped layer, and the concentration of doped P phosphorus atoms is 2% of that of the first doped layer -6 times; in the third doped layer, the concentration of doped P phosphorus atoms is 1.5-3 times that of the second doped layer.
  • the doped amorphous silicon layer is provided with four layers of doped layers whose doping concentration increases gradually from bottom to top.
  • the doped amorphous silicon layer The layer includes a first doped layer 51, a second doped layer 52, a third doped layer 53, and a fourth doped layer 54 whose doping concentration increases layer by layer from bottom to top.
  • the first doped layer 51 is provided on the amorphous silicon layer 40
  • the second doped layer 52 is provided on the first doped layer 51
  • the third doped layer 53 is provided on the second doped layer 52
  • the fourth doped layer 54 is provided on the third doped layer 53
  • the metal layer 60 is provided on the fourth doped layer 54.
  • the ratio of the doped layers of each layer may also be in the second doped layer, and the concentration of doped P phosphorus atoms is the first 1.5-3 times of the doped layer; in the third doped layer, the concentration of doped P phosphorus atoms is 2-6 times that of the second doped layer; in the fourth doped layer, the doped P phosphorus The concentration of atoms is 1.5-3 times that of the third doped layer.
  • the N-type doped amorphous silicon layer has four doped layers, the first doped layer, the second doped layer, the third doped layer, and the first The doping concentration ratio of the four-doped layer is 1:1.5:2.5:3.
  • the array substrate provided by the present application is provided with at least three layers of concentration gradients from the bottom to the top of the metal layer to increase the doping layer with increasing concentration layer by layer, which increases the barrier energy barrier and makes electron injection more It is easy to reduce leakage current, improve the stability of the thin film transistor, and solve the problem that the thin film transistor is prone to image sticking.
  • a chemical vapor deposition method is used to form a gate insulating layer, and the gate insulating layer covers the gate electrode; an amorphous silicon layer is sequentially deposited on the gate insulating layer , A doped amorphous silicon layer and a metal layer including at least three doped layers, wherein the ion concentration of each layer of the doped amorphous silicon layer increases layer by layer from bottom to top, to The doped amorphous silicon layer of the four-layer doped layer is taken as an example.
  • the doped concentration of the first doped layer is smaller than that of the second doped layer, and the doped concentration of the second doped layer is smaller than that of the third doped layer Layer doping concentration, third The doping concentration of the doped layer is less than that of the fourth doped layer.
  • the PH 3 and SiH 4 of the first doped layer may be 0.8, the gas flow ratio of PH 3 and SiH 4 of the second doped layer may be 1.8, and the gas flow ratio of PH 3 and SiH 4 of the third doped layer may be 4.5.
  • the P phosphorus atom is a pentavalent atom
  • the Si silicon atom is a tetravalent atom
  • a P phosphorus atom will have an extra electron to form N type structure.
  • the gas flow ratio of PH 3 and SiH 4 of the first doped layer may be 0.5.
  • PH 3 gas flow rate and PH 3 SiH and SiH 4 gas flow rate of the doped layer may be 1 .5, PH 3 gas flow ratio of SiH and third doped layer 4 may be 3, 4 of the fourth doped layer Can be 4.5.
  • a 4 Mask process (four-step lithography process) may be used.
  • the amorphous silicon layer, the doped amorphous silicon layer and the metal layer are etched to etch the pattern of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer.
  • apply photoresist on the metal layer Then, it is exposed and developed through a two-tone mask to remove the photoresist located in the exposed area, and then the metal layer, the doped amorphous silicon layer and the amorphous silicon layer in the exposed area are etched.
  • a passivation layer covering the pattern including the amorphous silicon layer, the doped amorphous silicon layer and the metal layer is formed, and a passivation layer through the passivation layer is formed.
  • the array substrate provided by the present application , By forming a doped amorphous silicon layer with at least three layers of doping concentration gradually increasing from bottom to top, to increase the barrier energy barrier of the doped amorphous silicon layer, reduce the leakage current, and enhance the array substrate Stability, solved the thin film transistor easily There is a problem of image retention.
  • FIG. 4 is a schematic structural diagram of another embodiment of the array substrate of the present application, based on the above embodiments of FIGS. 1 to 3,
  • the gate insulating layer 30 of the array substrate provided by the present application includes a first gate insulating layer 31 and a second gate insulating layer 32.
  • the first gate insulating layer 31 is provided on the base substrate 10 and covers the gate 20, and the second gate insulating layer 32 is provided on the first gate insulating layer 31.
  • the interlayer thickness of the first gate insulating layer is greater than the interlayer thickness of the second gate insulating layer, optionally, the first The interlayer thickness of the gate insulating layer is 2500 ⁇ (Amy), and the interlayer thickness of the second gate insulating layer is 1000 ⁇ (Amy).
  • the gate insulating layer when the gate insulating layer is formed by deposition, Depositing and forming the first gate insulating layer covering the gate on the pre-formed base substrate and the gate; depositing and forming the second gate on the first gate insulating layer Electrode insulation layer, the deposition rate of the first gate insulation layer is greater than the deposition rate of the second gate insulation layer, specifically Ground, the first gate insulating layer is prepared according to a conventional deposition rate process parameter, and the second gate insulating layer is prepared at a lower process rate than conventional deposition rate process parameter.
  • the interlayer thickness is 2500 ⁇
  • the gate insulating layer with a thickness of 1000 ⁇ between the second gate insulating layer to reduce the Si-H weak bonds, improve the stability of the array substrate, and effectively improve Thin film transistors are prone to image retention problems.
  • the present application provides a method for manufacturing an array substrate, which improves the stability of the array substrate and solves the problem that the thin film transistor is prone to image retention The problem.
  • FIG. 5 is a schematic diagram of a hardware operating environment of a terminal according to an embodiment of the present application.
  • the terminal in the embodiment of the present application may be an apparatus for manufacturing an array substrate.
  • the terminal may include: a processor 1001, such as a CPU (C entral Processing U nit), memory 1002, communication bus 1003.
  • the communication bus 1003 is configured to implement connection communication between the components in the terminal.
  • the memory 1002 may be a high-speed RAM random Memory (random-access memory), can also be a stable memory (non-volatile memory), such as disk storage.
  • the memory 1002 may optionally be a storage device independent of the foregoing processor 1001.
  • FIG. 5 does not constitute a limitation on the terminal in the embodiments of the present application, and may include more or fewer components than those illustrated, or combine some components, or different components Layout.
  • the memory 1002 which is a computer storage medium, may include an array substrate manufacturing program.
  • the processor 1001 may be set to call the manufacturing program of the array substrate stored in the memory 1002 and perform the following operations:
  • amorphous silicon layer depositing an amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer in sequence on the gate insulating layer, wherein each layer of the doped amorphous silicon layer is doped
  • the impurity concentration increases layer by layer from bottom to top;
  • a passivation layer covering a pattern including the amorphous silicon layer, the doped amorphous silicon layer, and the metal layer is formed to form an array substrate.
  • processor 1001 can call the manufacturing program of the array substrate stored in the memory 1002, and also perform the following operations:
  • the second gate insulating layer is deposited on the first gate insulating layer, and the deposition rate of the first gate insulating layer is greater than the deposition rate of the second gate insulating layer.
  • processor 1001 can call the manufacturing program of the array substrate stored in the memory 1002, and also perform the following operations:
  • the remaining thickness is etched in the channel region from 450 ⁇ to 550 ⁇ Of the amorphous silicon layer.
  • processor 1001 can call the manufacturing program of the array substrate stored in the memory 1002, and also perform the following operations:
  • the patterned doped amorphous silicon layer is heat-treated based on nitride gas.
  • processor 1001 can call the manufacturing program of the array substrate stored in the memory 1002, and also perform the following operations:
  • the preset voltage range is 14.6V-15.6V .
  • the manufacturing method of the array substrate includes:
  • Step S10 Deposit and form a gate insulating layer on the pre-formed base substrate and the gate, and the gate insulating layer covers the gate.
  • Step S20 Depositing an amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer in sequence on the gate insulating layer, wherein each layer of the doped amorphous silicon layer is doped
  • the impurity concentration increases layer by layer from bottom to top.
  • Step S30 Etching the pattern of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer.
  • Step S40 On the gate insulating layer, a passivation layer covering a pattern including the amorphous silicon layer, the doped amorphous silicon layer, and the metal layer is formed to form an array substrate.
  • a chemical vapor deposition method is used to form a gate insulating layer, and the gate insulating layer covers the gate electrode; an amorphous silicon layer is sequentially deposited on the gate insulating layer , A doped amorphous silicon layer and a metal layer including at least three doped layers, wherein the ion concentration of each layer of the doped amorphous silicon layer increases layer by layer from bottom to top, to The doped amorphous silicon layer of the four-layer doped layer is taken as an example.
  • the doped concentration of the first doped layer is smaller than that of the second doped layer, and the doped concentration of the second doped layer is smaller than that of the third doped layer Layer doping concentration, third The doping concentration of the doped layer is less than that of the fourth doped layer.
  • the PH 3 and SiH 4 of the first doped layer may be 0.8, the gas flow ratio of PH 3 and SiH 4 of the second doped layer may be 1.8, and the gas flow ratio of PH 3 and SiH 4 of the third doped layer may be 4.5.
  • the gas flow ratio of PH 3 and SiH 4 of the first doped layer may be 0.5.
  • PH 3 gas flow rate and PH 3 SiH and SiH 4 gas flow rate of the doped layer may be 1 .5, PH 3 gas flow ratio of SiH and third doped layer 4 may be 3, 4 of the fourth doped layer Can be 4.5.
  • a 4 Mask process (four-step lithography process) may be used.
  • the amorphous silicon layer, the doped amorphous silicon layer and the metal layer are etched to etch the pattern of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer.
  • apply photoresist on the metal layer Then, exposure and development are performed through a two-tone mask plate to remove the photoresist located in the exposed area to form a photoresist mask.
  • the metal layer, the doped amorphous silicon layer and the amorphous silicon layer of the exposed area are etched based on the lithography mask (The metal layer, the doped amorphous silicon layer and the amorphous silicon layer that are covered by the etching lithography mask).
  • the plasma ashing process is used to remove the photoresist in the half-exposed area ( Removing the lithography mask in the channel region) to expose the metal layer in the channel region corresponding to the half-exposure region, and then etching the metal layer in the channel region to form the source electrode and the leakage level of the metal layer And etching the doped amorphous silicon layer and the amorphous silicon layer in the channel region to form the channel region of the array substrate.
  • the amorphous silicon layer is etched to make the amorphous silicon layer
  • the thickness of the remaining thickness in the channel region ranges from 450 ⁇ (Amy) to 550 ⁇ (Amy), and optionally, the remaining thickness may be 500 ⁇ . It needs to be explained that The remaining thickness of the amorphous silicon layer formed in the channel region is in the range of 450 ⁇ -550 ⁇ , which can reduce the leakage current and improve the problem that the thin film transistor is prone to image sticking.
  • the patterned doped amorphous silicon layer is subjected to heat treatment based on NH 3 ammonia gas.
  • the substrate structure of the thin film transistor is subjected to a heat treatment at a temperature of 270°C (degrees Celsius) to 300°C (degrees Celsius) for 50 seconds to remove water vapor on the surface of the base structure of the thin film transistor, and then based on the temperature of 270°C-300°C
  • the N-type doped amorphous silicon layer is subjected to NH 3 gas treatment for 1 second to 15 seconds, wherein the gas treatment time can be selected to be 7 seconds or 10 seconds.
  • the thin film transistor prepared based on the thin film transistor substrate has illumination and high brightness stability, which can effectively improve the problem that the thin film transistor is prone to image sticking.
  • the thin film transistor base structure is subjected to a heat treatment at a processing environment temperature of 270°C-300°C for 50 seconds to remove water vapor on the surface of the thin film transistor base structure, and then based on the treatment ambient temperature of 270°C-300°C for N
  • the type-doped amorphous silicon layer is subjected to N 2 gas treatment for 1 second to 20 seconds, and NH 3 gas treatment for 1 second to 15 seconds, wherein the N 2 gas treatment time can be selected to be 10 seconds, and the NH 3 gas treatment The time can be selected as 7 seconds or 10 seconds.
  • forming a cover on the gate insulating layer includes An amorphous silicon layer, a patterned passivation layer of the doped amorphous silicon layer and the metal layer, and a pixel layer forming a passivation via through the passivation layer to form a thin film transistor array substrate.
  • the thin film transistor array substrate is a back-etched channel type array substrate.
  • a display panel is manufactured based on the thin film transistor array substrate.
  • the array substrate is driven based on a voltage within a preset voltage range, and the preset voltage range is 14.6V (volt)-15.6V (volt). such By setting the Gamma voltage to 14.6V-15.6V, the driving ability of the thin film transistor is increased, so that the thin film transistor is less prone to image sticking.
  • the passivation layer of the pattern to form Thin film transistor array substrate. In this way, by improving the stability of the thin film transistor array substrate, the problem that the thin film transistor is prone to image retention is solved.
  • the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, and the step of depositing and forming the gate insulating layer on the pre-formed base substrate and the gate includes:
  • Step S11 Deposit and form the first gate insulating layer covering the gate on the pre-formed base substrate and the gate.
  • Step S12 The second gate insulating layer is deposited on the first gate insulating layer, and the deposition rate of the first gate insulating layer is greater than the deposition rate of the second gate insulating layer.
  • the gate insulating layer of the array substrate includes a first gate insulating layer and a second gate insulating layer, the interlayer thickness of the first gate insulating layer is greater than the interlayer thickness of the second gate insulating layer, optional Ground, the interlayer thickness of the first gate insulating layer is 2500 ⁇ , the thickness of the second gate insulating layer is 1000 ⁇ .
  • the first gate electrode covering the gate electrode is deposited and formed on the pre-formed base substrate and the gate electrode An insulating layer; depositing and forming the second gate insulating layer on the first gate insulating layer, the deposition rate of the first gate insulating layer is greater than the deposition rate of the second gate insulating layer, specifically
  • the first gate insulating layer is prepared according to the conventional deposition rate process parameters, and the second gate insulating layer is prepared at the lower than conventional deposition rate process parameters.
  • the interlayer thickness by forming the first gate insulating layer is 2500 ⁇
  • the thickness of the second gate insulating layer is 1000
  • the gate insulating layer of ⁇ reduces Si-H weak bonds, improves the stability of the thin film transistor array substrate, and effectively improves the problem that the thin film transistor is prone to image sticking.
  • the present application also provides an array substrate manufacturing apparatus, the array substrate manufacturing apparatus includes a memory, a processor, and an array substrate manufacturing program stored on the memory and runable on the processor, the processor executes The manufacturing process of the array substrate realizes the steps of the manufacturing method of the array substrate as described in the above embodiments.
  • the methods in the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware.
  • the technical solution of the present application can be embodied in the form of a software product in essence or part that contributes to the existing technology, and the computer software product is stored in a storage medium (such as ROM/RAM as described above) , Disk, CD), including several instructions to make a terminal device (which can be a TV, mobile phone, computer, server, air conditioner, or network equipment, etc.) to perform the method described in each embodiment of the present application.
  • a terminal device which can be a TV, mobile phone, computer, server, air conditioner, or network equipment, etc.

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Abstract

一种阵列基板及其制造方法与装置，包括：在预先形成的衬底基板（10）和栅极（20）上沉积形成栅极绝缘层（30），所述栅极绝缘层（30）覆盖所述栅极（20）；在所述栅极绝缘层（30）上依次沉积形成非晶硅层（40）、包括至少三层掺杂层的掺杂型非晶硅层（50）和金属层（60），其中，所述掺杂型非晶硅层（50）各层的掺杂浓度自下往上逐层递增；蚀刻出所述非晶硅层（40）、所述掺杂型非晶硅层（50）和所述金属层（60）的图形，形成阵列基板。

Description

阵列基板的制造方法、装置及阵列基板
相关申请
本申请要求 2018 年 12月25日申请的，申请号为 201811598405.4 ，名称为'阵列基板的制造方法、装置及阵列基板'的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及 薄膜晶体管 领域，尤其涉及一种 阵列基板的制造方法、阵列基板的制造装置和阵列基板 。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。液晶显示器现已成为市场主流，其工作原理是液晶在电流的驱动下会发生偏转，使光线容易通过，从而显示图像。但是液晶在受长时间的驱动后可能会被极化，或者是因为薄膜晶体管阵列基板漏电，造成液晶分子不能在信号电压控制下正常偏转，过一段时间后仍可以看到静止画面的痕迹，即IS现象（ImageSticking），屏幕上会长时间保持一幅或者一部分静止的画面。
发明内容
本申请的主要目的在于提供一种 阵列基板的制造方法、阵列基板的制造装置以及阵列基板 ， 提高了薄膜晶体管阵列基板的稳定性 。
为实现上述目的，本申请提供 一种 阵列基板的制造方法，所述阵列基板的制造方法包括以下步骤：
在预先形成的衬底基板和栅极上沉积形成栅极绝 缘层，所述栅极绝缘层覆盖所述栅极；
在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少 三层掺杂层的掺杂型非晶硅层 和金属层，其中，所述 掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增 ；
蚀刻出所述非晶硅层、所述 掺杂型非晶硅层和所述金属层的图形；以及
在 所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板。
可选地，所述栅极绝缘层包括第一栅极绝缘层和第二栅极绝缘层，所述在预先形成的衬底基板和栅极上沉积形成栅极绝缘层的步骤包括：
在预先形成的所述衬底基板和所述栅极上，沉积形成覆盖所述栅极的所述第一栅极绝缘层；以及
在所述第一栅极绝缘层上沉积形成所述第二栅极绝缘层，所述第一栅极绝缘层的沉积速率大于所述第二栅极绝缘层的沉积速率。
可选地 ，所述第一栅极绝缘层的层间厚度大于所述第二栅极绝缘层的层间厚度。
可选地 ，所述 在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少 三层掺杂层的掺杂型非晶硅层 和金属层的步骤之后，还包括：
在对所述非晶硅层进行背沟道蚀刻时，在沟道区域内蚀刻出剩余厚度的范围为450 Å -550 Å 的所述非晶硅层。
可选地，所述掺杂型非晶硅层包括掺杂浓度自下往上逐层递增的第一掺杂层、第二掺杂层、第三掺杂层和第四掺杂层。
可选地，所述第一掺杂层、所述第二掺杂层、所述第三掺杂层和所述第四掺杂层的掺杂浓度占比为1:1.5:2.5:3。
可选地 ， 各个 所述掺杂层的层间厚度相等。
可选地 ， 所述蚀刻出所述非晶硅层、所述 掺杂型非晶硅层和所述金属层的图形的步骤包括；
在所述金属层上形成光刻掩膜；
基于所述光刻掩膜蚀刻所述金属层、所述掺杂型非晶硅层和所述非晶硅层；
去除沟道区域内的所述光刻掩膜，以在 沟道区域内露出 所述 金属层 ；以及
依次蚀刻 沟道区域内 的所述 金属层、所述掺杂型非晶硅层和所述非晶硅层，以形成阵列基板的沟道区。
可选地，所述在 所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板 的步骤之前，还包括：
基于氮化物气体 对 已图形化的 所述 掺杂型非晶硅层进行 热处理 ；以及
其中，所述在 所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板的步骤 之后，还包括：
基于预设 电压范围内的电压驱动所述 阵列基板 ， 所述 预设电压范围为 14.6V- 15.6V 。
为实现上述目的，本申请 还 提供 一种 阵列基板的制造 装置， 所述 阵列基板的制造 装置 包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的 阵列基板的制造 程序，所述 阵列基板的制造 程序被所述处理器执行时实现如 上所述 阵列基板的制造 方法的步骤 。
为实现上述目的，本申请 还 提供 一种 阵列基板 ， 所述 阵列基板 包括：
衬底基板，所述衬底基板上依次设有栅极、栅极绝缘层、非晶硅层、掺杂型非晶硅层、金属层和钝化层；以及
其中， 所述掺杂型非晶硅层至少包括三层掺杂层，所述掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增。
可选地 ， 所述掺杂型非晶硅层包括掺杂浓度自下往上逐层递增的第一掺杂层、第二掺杂层、第三掺杂层和第四掺杂层。
可选地，所述第一掺杂层、所述第二掺杂层、所述第三掺杂层和所述第四掺杂层的掺杂浓度占比为1:1.5:2.5:3。
可选地 ， 各个 所述掺杂层的层间厚度相等。
可选地 ， 所述栅极绝缘层包括第一栅极绝缘层和第二栅极绝缘层，其中：
所述第一栅极绝缘层，设于所述衬底基板上且覆盖所述栅极；
所述第二栅极绝缘层，设于所述第一栅极绝缘层上；以及
所述第一栅极绝缘层的层间厚度大于所述第二栅极绝缘层的层间厚度。
本申请提供的 阵列基板 、 阵列基板的制造方法以及装置 ， 在预先形成的衬底基板和栅极上沉积形成栅极绝缘层，所述栅极绝缘层覆盖所述栅极；在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少三层掺杂层的掺杂型非晶硅层和金属层，其中，所述掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增；蚀刻出所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形；在所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板。 这样， 通过提高薄膜晶体管阵列基板的稳定性，解决 了薄膜晶体管容易出现 图像残留 的问题。
附图说明
图1为本申请 阵列基板的一实施例的结构示意图 ；
图2为本申请 阵列基板 的另一实施例的结构示意图 ；
图3为本申请 阵列基板 的又一实施例的结构示意图 ；
图4为本申请 阵列基板的又一实施例的结构示意图 ；
图5为 实施例方案涉及的实施例终端的硬件运行环境示意图 ；
图6为本申请 阵列基板的制造 方法 的一 实施例的流程示意图；
图7为本申请 阵列基板的制造 方法 的另一 实施例的流程示意图。
附图标号说明：
标号 名称 标号 名称
10 衬底基板 51 第一掺杂层
20 栅极 52 第二掺杂层
30 栅极绝缘层 53 第三掺杂层
31 第一栅极绝缘层 54 第四掺杂层
32 第二栅极绝缘层 60 金属层
40 非晶硅层 70 钝化层
50 掺杂型非晶硅层
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不限定本申请。
本申请的一个或几个实施例的解决方案是：
在预先形成的衬底基板和栅极上沉积形成栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少三层掺杂层的掺杂型非晶硅层和金属层，其中，所述掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增；
蚀刻出所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形；
在所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板。
这样， 本申请提供 的 阵列基板 ，通过形成具有至少三层掺杂浓度自下往上逐渐递增的掺杂型非晶硅层，以增加掺杂型非晶硅层的势垒能障，降低了漏电流，增强了 阵列基板 的稳定性，解决了薄膜晶体管容易 出现 图像残留 的问题 。
如图1、图2和 图 3所示，图1是本申请阵列基板的一实施例的结构示意图，图2是本申请阵列基板的另一实施例的三层掺杂型非晶硅层的层间结构示意图， 图 3 是 本申请阵列基板的又一实施例的四层掺杂型非晶硅层的层间结构示意图。
本申请提供一种 阵列基板 ，如图1所示，所述 阵列基板包括衬底基板10、设于所述衬底基板10上的栅极20、设于所述衬底基板10上且覆盖所述栅极20的栅极绝缘层30、设于所述栅极绝缘层30上的非晶硅层40、设于所述非晶硅层40上的掺杂型非晶硅层50、设于所述掺杂型非晶硅层50上的金属层60，以及设于所述栅极绝缘层30上且覆盖包括所述非晶硅层40、所述掺杂型非晶硅层50、所述金属层60的钝化层70，所述掺杂型非晶硅层50至少包括三层掺杂层，所述掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增。需要说明的是，所述阵列基板还可以是包括通过所述钝化层的钝化过孔的像素电极（图示未指出）。
需要说明的是，所述金属层包括源电极和漏电极（图示未指出），金属层的材质可以是锰、钼、钛、铝和铜中的一种或多种的堆栈组合；所述非晶硅层可以是A-Si无定型硅材质；所述栅极绝缘层的材质可以是氧化硅和/或氮化硅；所述栅极可以是钼、钛、铝和铜中的一种或多种的堆栈组合；所述衬底基板可以是玻璃基板。
可选地， 各个 所述掺杂层的层间厚度相等。需要说明的是，所述掺杂型非晶硅层可以是N型（ Negative ）掺杂非晶硅层，也可以是P型（ Positive ）掺杂非晶硅层，可选地，设置所述掺杂型非晶硅层为N型掺杂非晶硅层。
本申请实施例中，可选地，所述掺杂型非晶硅层设置有三层掺杂浓度自下往上逐层递增的掺杂层，参照图 2 ，所述掺杂型非晶硅层包括掺杂浓度自下往上逐层递增的第一掺杂层51、第二掺杂层52和第三掺杂层53。需要说明的是，第一掺杂层51设于非晶硅层40上，第二掺杂层52设于第一掺杂层51上，第三掺杂层53设于第二掺杂层52上，而则金属层60设于第三掺杂层53上。
在所述 N型掺杂非晶硅层具有三层掺杂层时，各层掺杂层占比也可以是在第二掺杂层中，掺杂的P磷原子的浓度为第一掺杂层的2-6倍；在第三掺杂层中，掺杂的P磷原子的浓度为第二掺杂层的1.5-3倍。
本申请实施例中，可选地，所述掺杂型非晶硅层设置有四层掺杂浓度自下往上逐层递增的掺杂层，参照图3，所述掺杂型非晶硅层包括掺杂浓度自下往上逐层递增的第一掺杂层51、第二掺杂层52、第三掺杂层53和第四掺杂层54。需要说明的是，第一掺杂层51设于非晶硅层40上，第二掺杂层52设于第一掺杂层51上，第三掺杂层53设于第二掺杂层52上，第四掺杂层54设于第三掺杂层53上，而则金属层60设于第四掺杂层54上。
可选地，在N型掺杂非晶硅层具有四层掺杂层时，各层掺杂层占比也可以是在第二掺杂层中，掺杂的P磷原子的浓度为第一掺杂层的1.5-3倍；在第三掺杂层中，掺杂的P磷原子的浓度为第二掺杂层的2-6倍；在第四掺杂层中，掺杂的P磷原子的浓度为第三掺杂层的1.5-3倍。
可选地，在所述N型掺杂非晶硅层具有四层掺杂层时，所述第一掺杂层、所述第二掺杂层、所述第三掺杂层和所述第四掺杂层的掺杂浓度占比为1:1.5:2.5:3。
本申请提供的阵列基板，在非晶硅层与金属层之间设有至少三层浓度梯度自下往上掺杂浓度逐层递增的掺杂层，增加了势垒能障，使电子注入更加容易，实现降低了漏电流，提高了薄膜晶体管的稳定性，解决了薄膜晶体管容易出现图像残留的问题。
可选地，在制造阵列基板时， 在预先形成的衬底基板和栅极上，采用化学气相法沉积形成栅极绝缘层，所述栅极绝缘层覆盖所述栅极；在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少三层掺杂层的掺杂型非晶硅层和金属层，其中，所述掺杂型非晶硅层各层掺杂的离子浓度自下往上逐层递增，以 四层掺杂层的掺杂型非晶硅层 为 例，第 一 掺杂层的掺杂浓度小于第二掺杂层的掺杂浓度，第 二 掺杂层的掺杂浓度小于第 三 掺杂层的掺杂浓度，第 三 掺杂层的掺杂浓度小于第 四 掺杂层的掺杂浓度 。
具体地，基于PH 3 磷化氢和SiH 4 四氢化硅（甲硅烷）沉积形成具有三层掺杂层的N型掺杂非晶硅层时，第一 掺杂层 的PH 3 和SiH 4 的气流 比 率 可以为 0.8，第二 掺杂层的 PH 3 和SiH 4 的 气流比率可以为 1.8，第三 掺杂层的 PH 3 和SiH 4 的 气流比率可以为4.5 。需要说明的是，由于P磷原子是五价原子，Si硅原子是四价原子，在进行化合反应时，当P磷原子替代Si硅原子时，P磷原子就会多出一个电子，以形成N型结构。
具体地，基于PH 3 和SiH 4 沉积形成具有四层掺杂层的N型掺杂非晶硅层时，第一 掺杂层 的PH 3 和SiH 4 的气流 比 率 可以为 0. 5 ，第二 掺杂层的 PH 3 和SiH 4 的 气流比率可以为 1 .5 ，第三 掺杂层的 PH 3 和SiH 4 的 气流比率可以为3 ，第四 掺杂层的 PH 3 和SiH 4 的 气流比率可以为4.5 。
可选 地， 在掺杂 型非晶硅层上沉积形成金属层后，可以是采用 4Mask制程 （ 四 步光刻制程） 图形 化 非晶硅层、掺杂型非晶硅层和金属层，以蚀刻出非晶硅层、掺杂型非晶硅层和金属层的图形。具体 地，在金属层上涂抹光刻胶， 并通过双色调掩膜版进行曝光、显影，去除位于曝光区域的光刻胶， 然后蚀刻曝光区域的金属层、掺杂型非晶硅层 和 非晶硅层。 利用等离子体灰化工艺，去除半曝光 区域 的光刻胶，以 在 半 曝光区域对应的沟道区域内露出金属层， 然后蚀刻沟道 区域内的 金属 层，以形成金属 层的 源电 极 和漏电 级 ，以及蚀刻 沟道 区域内的掺杂型非晶硅层和 非 晶硅层， 其中 ，蚀刻 所述非晶硅层， 以使非晶硅层 在 沟道区域内的剩余厚度为450 Å -550 Å ， 可选地，剩余厚度可以为 500 Å 。需要 说明的是，通过 形成 在 沟道区域内的剩余厚度为450 Å -550 Å 的 非晶硅层 ， 能够减少漏电流，以改善 薄膜晶体管容易 出现 图像残留 的问题 。
具体地 ，在 图 形化金属层 、 掺杂型非晶硅层和 非 晶硅层 后 ， 在所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以及形成 通过钝化层的钝化过孔的像素层， 以形成阵列基板。
这样， 本申请提供 的 阵列基板 ，通过形成具有至少三层掺杂浓度自下往上逐渐递增的掺杂型非晶硅层，以增加掺杂型非晶硅层的势垒能障，降低了漏电流，增强了 阵列基板 的稳定性，解决了薄膜晶体管容易 出现 图像残留 的问题 。
如 图 4所示 ， 图 4 是本申请阵列基板的又一实施例的结构示意图， 在上述图1至图3的实施例基础上 ， 本申请提供的阵列基板的栅极 绝缘层3 0 包括 第一栅极绝缘层 31和 第二栅极绝缘层 32，所述第一栅极绝缘层31设于所述衬底基板10上且覆盖所述栅极20，所述第二栅极绝缘层32设于所述第一栅极绝缘层31上。
所述第一栅极绝缘层的层间厚度大于所述第二栅极绝缘层的层间厚度， 可选地，第一 栅极绝缘层的层间厚度为2500 Å （埃米）， 第二栅极绝缘层的层间厚度为1000 Å （埃米）。
具体 地，在制造阵列基板的过程中，在沉积形成栅极绝缘层时， 在预先形成的所述衬底基板和所述栅极上，沉积形成覆盖所述栅极的所述第一栅极绝缘层；在所述第一栅极绝缘层上沉积形成所述第二栅极绝缘层，所述第一栅极绝缘层的沉积速率大于所述第二栅极绝缘层的沉积速率，具体 地，第 一 栅极绝缘层 按照常规沉积速率工艺 参数制备，第二栅极绝缘层以低于常规沉积速率 工艺参数制备。这样 ，通过形成第一 栅极绝缘层的层间厚度为2500 Å ， 第二栅极绝缘层的层间厚度为1000 Å 的 栅极绝缘层， 以 减少Si-H弱键，提升 阵列基板 的 稳定性， 有效改善了 薄膜晶体管容易出现图像残留的问题。
本申请提供一种阵列基板的制造方法， 通过提高阵列基板的稳定性，解决 了薄膜晶体管容易出现 图像残留 的问题。
如图5所示，图5是本申请实施例方案涉及的实施例终端的硬件运行环境示意图；
本申请实施例终端可以是阵列基板的制造 装置 。
如图5所示，该 终端 可以包括：处理器1001，例如CPU （C entral P rocessing U nit ） ，存储器1002，通信总线1003。其中，通信总线1003设置为实现该 终端 中各组成部件之间的连接通信。存储器1002可以是高速RAM 随机 存储器 （ random-access memory ） ，也可以是稳定的存储器（non-volatile memory），例如磁盘存储器。存储器1002可选的还可以是独立于前述处理器1001的存储装置。
本领域技术人员可以理解，图5中示出的终端的结构并不构成对本申请实施例终端的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
如图5所示，作为一种计算机存储介质的存储器1002中可以包括 阵列基板的制造 程序。
在图5所示的 终端 中，处理器1001可以设置为调用存储器1002中存储的阵列基板的制造程序，并执行以下操作：
在预先形成的衬底基板和栅极上沉积形成栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少三层掺杂层的掺杂型非晶硅层和金属层，其中，所述掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增；
蚀刻出所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形；
在所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板。
进一步地，处理器1001可以调用存储器1002中存储的阵列基板的制造程序，还执行以下操作：
在预先形成的所述衬底基板和所述栅极上，沉积形成覆盖所述栅极的所述第一栅极绝缘层；
在所述第一栅极绝缘层上沉积形成所述第二栅极绝缘层，所述第一栅极绝缘层的沉积速率大于所述第二栅极绝缘层的沉积速率。
进一步地，处理器1001可以调用存储器1002中存储的阵列基板的制造程序，还执行以下操作：
在对所述非晶硅层进行背沟道蚀刻时，在沟道区域内蚀刻出剩余厚度为450 Å -550 Å 的所述非晶硅层。
进一步地，处理器1001可以调用存储器1002中存储的阵列基板的制造程序，还执行以下操作：
基于氮化物气体 对 已图形化的 所述 掺杂型非晶硅层进行 热处理。
进一步地，处理器1001可以调用存储器1002中存储的阵列基板的制造程序，还执行以下操作：
基于预设 电压范围内的电压驱动所述 阵列基板 ， 所述 预设电压范围为 14.6V- 15.6V 。
参照图6， 在一 实施例中，所述阵列基板的制造方法包括：
步骤S10、 在预先形成的衬底基板和栅极上沉积形成栅极绝缘层，所述栅极绝缘层覆盖所述栅极。
步骤S20、 在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少三层掺杂层的掺杂型非晶硅层和金属层，其中，所述掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增。
步骤S30、 蚀刻出所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形。
步骤S40、 在所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板。
本实施例中， 在预先形成的衬底基板和栅极上，采用化学气相法沉积形成栅极绝缘层，所述栅极绝缘层覆盖所述栅极；在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少三层掺杂层的掺杂型非晶硅层和金属层，其中，所述掺杂型非晶硅层各层掺杂的离子浓度自下往上逐层递增，以 四层掺杂层的掺杂型非晶硅层 为 例，第 一 掺杂层的掺杂浓度小于第二掺杂层的掺杂浓度，第 二 掺杂层的掺杂浓度小于第 三 掺杂层的掺杂浓度，第 三 掺杂层的掺杂浓度小于第 四 掺杂层的掺杂浓度 。
具体地，基于PH 3 磷化氢和SiH 4 四氢化硅（甲硅烷）沉积形成具有三层掺杂层的N型掺杂非晶硅层时，第一 掺杂层 的PH 3 和SiH 4 的气流 比 率 可以为 0.8，第二 掺杂层的 PH 3 和SiH 4 的 气流比率可以为 1.8，第三 掺杂层的 PH 3 和SiH 4 的 气流比率可以为4.5 。
具体地，基于PH 3 和SiH 4 沉积形成具有四层掺杂层的N型掺杂非晶硅层时，第一 掺杂层 的PH 3 和SiH 4 的气流 比 率 可以为 0. 5 ，第二 掺杂层的 PH 3 和SiH 4 的 气流比率可以为 1 .5 ，第三 掺杂层的 PH 3 和SiH 4 的 气流比率可以为3 ，第四 掺杂层的 PH 3 和SiH 4 的 气流比率可以为4.5 。
可选 地， 在掺杂 型非晶硅层上沉积形成金属层后，可以是采用 4Mask制程 （ 四 步光刻制程） 图形 化 非晶硅层、掺杂型非晶硅层和金属层，以蚀刻出非晶硅层、掺杂型非晶硅层和金属层的图形。具体 地，在金属层上涂抹光刻胶， 并通过双色调掩膜版进行曝光、显影，去除位于曝光区域的光刻胶， 形成光刻掩膜。 然后 基于光刻掩膜 蚀刻曝光区域的金属层、掺杂型非晶硅层 和 非晶硅层 （蚀刻光刻掩膜覆盖范围外的 金属层、掺杂型非晶硅层 和 非晶硅层 ） 。 然后，利用等离子体灰化工艺，去除半曝光 区域 的光刻胶（ 去除沟道区域内的所述光刻掩膜 ），以 在 半 曝光区域对应的沟道区域内露出金属层， 然后蚀刻沟道 区域内的 金属 层，以形成金属 层的 源电 极 和漏电 级 ，以及蚀刻 沟道 区域内的掺杂型非晶硅层和 非 晶硅层， 以形成阵列基板的沟道区。其中 ，蚀刻 所述非晶硅层， 以使非晶硅层 在沟道区域内的剩余厚度的厚度范围为450 Å （埃米）-550 Å （埃米）， 可选地，剩余厚度可以为 500 Å 。需要 说明的是，通过 形成在沟道区域内的剩余厚度的范围为450 Å -550 Å 的 非晶硅层 ， 能够减少漏电流，以改善 薄膜晶体管容易 出现 图像残留 的问题 。
可选地 ，在 图 形化金属层 、 掺杂型非晶硅层和 非 晶硅层 后 ， 基于NH 3 氨气 对 已图形化的 所述 掺杂型非晶硅层进行 热处理。 具体 地，对 薄膜晶体管基体结构进行为时50秒的处理环境温度为270℃（摄氏度）-300℃（摄氏度） 的热处理 ，以除去薄膜晶体管基体结构表面的水汽，然后基于270℃-300℃的处理环境温度对N型掺杂非晶硅层 进行 为1秒至15秒 的 NH 3 气体 处理 ，其中，气体处理时间可选为7秒，也可选为10秒 。 这样 ， 在 能 减少Si-H弱键的 同时， 基于 该 薄膜晶体管基体 制备的 薄膜晶体管具有照光及高光亮稳定性，能 有效改善 薄膜晶体管容易 出现 图像残留 的问题 。
可选地 ，在 图 形化金属层 、 掺杂型非晶硅层和 非 晶硅层 后 ， 基于N 2 氮气和NH 3 氨气 对 已图形化的 所述 掺杂型非晶硅层进行 热处理。 具体 地， 在 对 薄膜晶体管基体结构进行为时50秒的处理环境温度为270℃-300℃ 的热处理 ，以除去薄膜晶体管基体结构表面的水汽，然后基于270℃-300℃的处理环境温度对N型掺杂非晶硅层进行1秒至20秒的N 2 气体处理，以及 进行 为1秒至15秒 的 NH 3 气体 处理 ，其中，N 2 气体处理时间可选为10秒，NH 3 气体处理时间可选为7秒，也可选为10秒 。 这样 ， 在 能 减少Si-H弱键的 同时， 基于 该 薄膜晶体管基体 制备的 薄膜晶体管具有照光及高光亮稳定性，能 有效改善 薄膜晶体管容易 出现 图像残留 的问题 。
在 图 形化金属层 、 掺杂型非晶硅层和 非 晶硅层， 以及基于NH 3 气体 对 掺杂型非晶硅层进行 热处理 之后 ， 在所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以及形成 通过钝化层的钝化过孔的像素层， 以形成薄膜晶体管阵列基板。
可选地，所述薄膜晶体管阵列基板为背刻沟道型阵列基板。
可选地，基于所述薄膜晶体管阵列基板制造显示面板。
基于预设电压范围内的电压驱动所述阵列基板，所述预设电压范围为14.6V（伏特）-15.6V（伏特）。这样 ，通过将 Gamma（伽马）电压设为 14.6V-15.6V ，增加了薄膜 晶体管的 驱动能力，以使薄膜晶体管不容易出现图像残留的 现象。
在本申请的一个或几个实施例中 ， 在预先形成的衬底基板和栅极上沉积形成栅极绝缘层，所述栅极绝缘层覆盖所述栅极；在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少三层掺杂层的掺杂型非晶硅层和金属层，其中，所述掺杂层非晶硅层各层掺杂的离子浓度自下往上逐层递增；蚀刻出所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形；在所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成 薄膜晶体管 阵列基板。这样 ， 通过提高 薄膜晶体管 阵列基板的稳定性，解决了薄膜晶体管容易出现图像残留的问题。
在 又一实施例 中，如图7所示，在上述图6所示的实施例基础上， 所述栅极绝缘层包括第一栅极绝缘层和第二栅极绝缘层，所述在预先形成的衬底基板和栅极上沉积形成栅极绝缘层的步骤包括：
步骤S11、 在预先形成的所述衬底基板和所述栅极上，沉积形成覆盖所述栅极的所述第一栅极绝缘层。
步骤S12、 在所述第一栅极绝缘层上沉积形成所述第二栅极绝缘层，所述第一栅极绝缘层的沉积速率大于所述第二栅极绝缘层的沉积速率。
本实施例中， 阵列基板的栅极绝缘层包括第一栅极绝缘层和第二栅极绝缘层，所述第一栅极绝缘层的层间厚度大于所述第二栅极绝缘层的层间厚度，可选地，第一栅极绝缘层的层间厚度为2500 Å，第二栅极绝缘层的层间厚度为1000 Å。
具体地，在制造阵列基板的过程中，在沉积形成栅极绝缘层时，在预先形成的所述衬底基板和所述栅极上，沉积形成覆盖所述栅极的所述第一栅极绝缘层；在所述第一栅极绝缘层上沉积形成所述第二栅极绝缘层，所述第一栅极绝缘层的沉积速率大于所述第二栅极绝缘层的沉积速率，具体地，第一栅极绝缘层按照常规沉积速率工艺参数制备，第二栅极绝缘层以低于常规沉积速率工艺参数制备。这样，通过形成第一栅极绝缘层的层间厚度为2500 Å，第二栅极绝缘层的层间厚度为1000 Å的栅极绝缘层，以减少Si-H弱键，提升薄膜晶体管阵列基板的稳定性，有效改善了薄膜晶体管容易出现图像残留的问题。
此外，本申请还提出一种阵列基板的制造装置，所述阵列基板的制造装置包括存储器、处理器及存储在存储器上并可在处理器上运行的阵列基板的制造程序，所述处理器执行所述阵列基板的制造程序时实现如以上实施例所述的阵列基板的制造方法的步骤。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是电视机，手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (18)

  1. 一种阵列基板的制造方法，其中，所述阵列基板的制造方法包括以下步骤：
    在预先形成的衬底基板和栅极上沉积形成栅极绝 缘层，所述栅极绝缘层覆盖所述栅极；
    在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少 三层掺杂层的掺杂型非晶硅层 和金属层，其中，所述 掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增 ；
    蚀刻出所述非晶硅层、所述 掺杂型非晶硅层和所述金属层的图形；以及
    在 所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板。
  2. 如权利要求1所述的阵列基板的制造方法，其中，所述栅极绝缘层包括第一栅极绝缘层和第二栅极绝缘层，所述在预先形成的衬底基板和栅极上沉积形成栅极绝缘层的步骤包括：
    在预先形成的所述衬底基板和所述栅极上，沉积形成覆盖所述栅极的所述第一栅极绝缘层；以及
    在所述第一栅极绝缘层上沉积形成所述第二栅极绝缘层，所述第一栅极绝缘层的沉积速率大于所述第二栅极绝缘层的沉积速率。
  3. 如权利要求2所述的阵列基板的制造方法，其中，所述第一栅极绝缘层的层间厚度大于所述第二栅极绝缘层的层间厚度。
  4. 如权利要求1所述的 阵列基板的制造方法，其中，所述 在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少 三层掺杂层的掺杂型非晶硅层 和金属层的步骤之后，还包括：
    在对所述非晶硅层进行背沟道蚀刻时，在沟道区域内蚀刻出剩余厚度的范围为450 Å -550 Å 的所述非晶硅层。
  5. 如权利要求1所述的阵列基板的制造方法，其中，所述掺杂型非晶硅层包括掺杂浓度自下往上逐层递增的第一掺杂层、第二掺杂层、第三掺杂层和第四掺杂层。
  6. 如权利要求5所述的阵列基板 ， 其中 ，所述第一掺杂层、所述第二掺杂层、所述第三掺杂层和所述第四掺杂层的掺杂浓度占比为1:1.5:2.5:3。
  7. 如权利要求1所述的阵列基板 ， 其中 ， 各个 所述掺杂层的层间厚度相等。
  8. 如权利要求1所述的 阵列基板 ， 其中 ， 所述蚀刻出所述非晶硅层、所述 掺杂型非晶硅层和所述金属层的图形的步骤包括；
    在所述金属层上形成光刻掩膜；
    基于所述光刻掩膜蚀刻所述金属层、所述掺杂型非晶硅层和所述非晶硅层；
    去除沟道区域内的所述光刻掩膜，以在 沟道区域内露出 所述 金属层 ；以及
    依次蚀刻 沟道区域内 的所述 金属层、所述掺杂型非晶硅层和所述非晶硅层，以形成阵列基板的沟道区。
  9. 如权利要求1所述的阵列基板的制造方法，其中，所述在 所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板 的步骤之前，还包括：
    基于氮化物气体 对 已图形化的 所述 掺杂型非晶硅层进行 热处理 。
  10. 如权利要求1所述的阵列基板的制造方法，其中，所述在 所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板的步骤 之后，还包括：
    基于预设 电压范围内的电压驱动所述 阵列基板 ， 所述 预设电压范围为 14.6V- 15.6V 。
  11. 一种 阵列基板的制造 装置 ，其中，所述 阵列基板的制造 装置 包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的 阵列基板的制造 程序，所述 阵列基板的制造 程序被所述处理器执行时实现如 下 阵列基板的制造 方法的步骤 ：
    在预先形成的衬底基板和栅极上沉积形成栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
    在所述栅极绝缘层上依次沉积形成非晶硅层、包括至少三层掺杂层的掺杂型非晶硅层和金属层，其中，所述掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增；
    蚀刻出所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形；以及
    在所述栅极绝缘层上，形成覆盖包括所述非晶硅层、所述掺杂型非晶硅层和所述金属层的图形的钝化层，以形成阵列基板。
  12. 如权利要求11所述的阵列基板的制造装置 ，其中， 所述掺杂型非晶硅层包括掺杂浓度自下往上逐层递增的第一掺杂层、第二掺杂层、第三掺杂层和第四掺杂层，所述第一掺杂层、所述第二掺杂层、所述第三掺杂层和所述第四掺杂层的掺杂浓度占比为1:1.5:2.5:3。
  13. 如权利要求11所述的阵列基板的制造装置 ，其中， 所述栅极绝缘层包括第一栅极绝缘层和第二栅极绝缘层，其中：
    所述第一栅极绝缘层，设于所述衬底基板上且覆盖所述栅极；
    所述第二栅极绝缘层，设于所述第一栅极绝缘层上；以及
    所述第一栅极绝缘层的层间厚度大于所述第二栅极绝缘层的层间厚度。
  14. 一种 阵列基板 ，其中， 所述阵列基板包括：
    衬底基板，所述衬底基板上依次设有栅极、栅极绝缘层、非 晶硅层、掺杂型非晶硅层、金属层和钝化层；以及
    其中， 所述掺杂型非晶硅层至少包括三层掺杂层，所述掺杂型非晶硅层各层的掺杂浓度自下往上逐层递增。
  15. 如权利要求14所述的阵列基板 ， 其中 ， 所述掺杂型非晶硅层包括掺杂浓度自下往上逐层递增的第一掺杂层、第二掺杂层、第三掺杂层和第四掺杂层。
  16. 如权利要求15所述的阵列基板 ， 其中 ，所述第一掺杂层、所述第二掺杂层、所述第三掺杂层和所述第四掺杂层的掺杂浓度占比为1:1.5:2.5:3。
  17. 如权利要求14所述的阵列基板 ， 其中 ， 各个 所述掺杂层的层间厚度相等。
  18. 如权利要求14所述的阵列基板 ， 其中 ， 所述栅极绝缘层包括第一栅极绝缘层和第二栅极绝缘层，其中：
    所述第一栅极绝缘层，设于所述衬底基板上且覆盖所述栅极；
    所述第二栅极绝缘层，设于所述第一栅极绝缘层上；以及
    所述第一栅极绝缘层的层间厚度大于所述第二栅极绝缘层的层间厚度。
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Publication number Priority date Publication date Assignee Title
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CN111430446A (zh) * 2019-01-09 2020-07-17 惠科股份有限公司 一种薄膜晶体管器件、驱动电路及显示装置
CN110444602A (zh) * 2019-08-05 2019-11-12 深圳市华星光电半导体显示技术有限公司 一种氧化物薄膜晶体管的制备方法及阵列基板
US11817460B2 (en) * 2020-03-27 2023-11-14 Boe Technology Group Co., Ltd. Thin film transistor and method for manufacturing the same, array substrate, and display device
US11935935B2 (en) * 2021-05-03 2024-03-19 Taiwan Semiconductor Manufacturing Company Limited Transistor including a hydrogen-diffusion barrier and methods for forming the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010049163A1 (en) * 1997-09-24 2001-12-06 Shunpei Yamazaki Semiconductor device and method for producing it
CN101893799A (zh) * 2009-05-22 2010-11-24 上海天马微电子有限公司 液晶显示面板及其制造方法
CN109065632A (zh) * 2018-07-26 2018-12-21 惠科股份有限公司 薄膜晶体管及其制造方法、显示装置
CN109786440A (zh) * 2018-12-25 2019-05-21 惠科股份有限公司 阵列基板的制造方法、装置及阵列基板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000012863A (ja) * 1998-06-19 2000-01-14 Sanyo Electric Co Ltd 薄膜トランジスタ及びそれを用いた表示装置
CN103489920B (zh) * 2013-09-26 2016-08-17 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN106571399A (zh) * 2016-11-08 2017-04-19 深圳市华星光电技术有限公司 一种薄膜晶体管及薄膜晶体管的制作方法
CN108598093B (zh) * 2018-05-24 2021-01-15 京东方科技集团股份有限公司 阵列基板的制造方法、阵列基板和显示面板
CN108987279B (zh) * 2018-07-16 2021-06-18 惠科股份有限公司 薄膜晶体管的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010049163A1 (en) * 1997-09-24 2001-12-06 Shunpei Yamazaki Semiconductor device and method for producing it
CN101893799A (zh) * 2009-05-22 2010-11-24 上海天马微电子有限公司 液晶显示面板及其制造方法
CN109065632A (zh) * 2018-07-26 2018-12-21 惠科股份有限公司 薄膜晶体管及其制造方法、显示装置
CN109786440A (zh) * 2018-12-25 2019-05-21 惠科股份有限公司 阵列基板的制造方法、装置及阵列基板

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