WO2020135052A1 - 阵列基板结构的制备方法、阵列基板及显示面板 - Google Patents

阵列基板结构的制备方法、阵列基板及显示面板 Download PDF

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WO2020135052A1
WO2020135052A1 PCT/CN2019/124560 CN2019124560W WO2020135052A1 WO 2020135052 A1 WO2020135052 A1 WO 2020135052A1 CN 2019124560 W CN2019124560 W CN 2019124560W WO 2020135052 A1 WO2020135052 A1 WO 2020135052A1
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array substrate
amorphous silicon
silicon layer
metal layer
substrate structure
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PCT/CN2019/124560
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English (en)
French (fr)
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卓恩宗
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惠科股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the field of thin film transistors, and in particular, to a method for preparing an array substrate structure, an array substrate, and a display panel.
  • the liquid crystal display has now become the mainstream of the market, and its working principle is that the liquid crystal will deflect under the drive of electric current, so that light easily passes through, thereby displaying an image.
  • the thin film transistor array substrate includes a metal layer and an amorphous silicon layer. During the preparation of the substrate structure of the array substrate, the portion of the amorphous silicon layer that cannot be covered by the metal layer is called amorphous silicon redundancy (A -Si tail), the redundancy of amorphous silicon may cause the light leakage current of the thin film transistor array substrate, resulting in the instability of the array substrate.
  • the main purpose of the present application is to provide a method for preparing an array substrate structure, an array substrate, and a display panel.
  • the metal layer completely covers the amorphous silicon layer.
  • the present application provides a method for preparing an array substrate structure.
  • the method for preparing an array substrate structure includes the following steps:
  • a lithography mask is formed on the metal layer, and the thickness of the lithography mask in the channel region is Set thickness
  • the metal layer and the amorphous silicon layer are sequentially etched, and a bias power supply is added when the amorphous silicon layer is etched, so that the metal layer covers the channel region
  • the outer amorphous silicon layer forms an array substrate structure.
  • the present application also provides an array substrate including an array substrate structure and a passivation layer, and a pixel electrode through a passivation via in the passivation layer, the passivation layer is provided On the array substrate structure, the array substrate structure is formed by the following preparation method of the array substrate structure:
  • a lithography mask is formed on the metal layer, and the thickness of the lithography mask in the channel region is Set thickness
  • the metal layer and the amorphous silicon layer are sequentially etched, and a bias power supply is added when the amorphous silicon layer is etched, so that the metal layer covers the channel region
  • the outer amorphous silicon layer forms an array substrate structure.
  • the present application also provides a display panel including an array substrate, the array substrate including an array substrate structure and a passivation layer, and pixels passing through passivation vias in the passivation layer Electrodes, the passivation layer is provided on the array substrate structure, and the array substrate structure is formed by the following preparation method of the array substrate structure:
  • a lithography mask is formed on the metal layer, and the thickness of the lithography mask in the channel region is Set thickness
  • the metal layer and the amorphous silicon layer are sequentially etched, and a bias power supply is added when the amorphous silicon layer is etched, so that the metal layer covers the channel region
  • the outer amorphous silicon layer forms an array substrate structure.
  • a method for preparing an array substrate structure, an array substrate, and a display panel provided by the present application after sequentially forming a gate, a gate insulating layer, an amorphous silicon layer, and a metal layer on a base substrate, forming photolithography on the metal layer A mask, the thickness of the lithography mask in the channel region is a preset thickness; etching the metal layer and the amorphous silicon layer outside the coverage of the lithography mask; a mixed gas based on a preset ratio Performing ashing treatment on the lithography mask to remove the lithography mask in the channel region; based on the lithography mask after the ashing treatment, etching the metal layer and the amorphous silicon layer in sequence And add a bias power supply when etching the amorphous silicon layer, so that the metal layer covers the amorphous silicon layer outside the channel region to form an array substrate structure.
  • the metal layer is completely covered with the amorphous silicon layer, which solves the problem that the array substrate is prone to leakage, thereby improving the array The stability of the substrate.
  • FIG. 1 is a schematic flowchart of an embodiment of a method for manufacturing an array substrate structure of the present application
  • FIG. 2 is a schematic flowchart of another embodiment of a method for manufacturing an array substrate structure of the present application
  • FIG. 3 is a schematic flowchart of still another embodiment of a method for manufacturing an array substrate structure of the present application
  • FIG. 4 is an example diagram of the lateral width difference between the metal layer and the amorphous silicon layer according to an embodiment of the method for manufacturing an array substrate structure of the present application;
  • FIG. 5 is an example diagram of a photolithography mask formed on a metal layer according to another embodiment of a method for manufacturing an array substrate structure of the present application
  • FIG. 6 is an example diagram of a photolithographic mask after ashing treatment according to still another embodiment of a method for preparing an array substrate structure of the present application
  • FIG. 7 is an example diagram of etching a metal layer and an amorphous silicon layer based on a photolithography mask after ashing treatment according to another embodiment of the method for manufacturing an array substrate structure of the present application;
  • FIG. 8 is a diagram of an example of a lithography mask according to still another embodiment of a method for manufacturing an array substrate structure of the present application.
  • the present application provides a method for preparing an array substrate structure. By removing the lateral width difference between the amorphous silicon layer and the metal layer formed during the preparation of the array substrate structure, the metal layer is completely covered with the amorphous silicon layer, which solves the array substrate The problem of current leakage is easy to occur, thereby improving the stability of the array substrate.
  • the method for manufacturing the array substrate structure includes:
  • Step S10 After sequentially forming a gate, a gate insulating layer, an amorphous silicon layer, and a metal layer on the base substrate, a lithography mask is formed on the metal layer, and the lithography mask is formed on the channel region.
  • the thickness is the preset thickness.
  • the thin film transistor array substrate may include an array substrate structure, a passivation film or passivation layer, and a pixel electrode through a passivation via in the passivation layer, wherein the array substrate structure further includes a base substrate and a gate Electrode, gate insulating layer, amorphous silicon layer (or active layer) and metal layer.
  • the amorphous silicon layer may further include a doped amorphous silicon layer, and the doped amorphous silicon layer is provided between the amorphous silicon layer and the metal layer, that is, the metal layer is provided in the doped Above the heterogeneous amorphous silicon layer.
  • the doped amorphous silicon layer may be an N-type doped amorphous silicon layer or a P-type doped amorphous silicon layer.
  • the lateral width of the finally formed amorphous silicon layer 22 is greater than the lateral width of the metal layer 12, that is, the metal layer cannot
  • the portion covering the amorphous silicon layer has a certain lateral width difference ⁇ hc.
  • it can also be the part of the amorphous silicon layer that cannot be covered by the metal layer, which is called amorphous silicon redundancy (A-Si tail).
  • Amorphous silicon redundancy may cause light leakage current in the thin film transistor array substrate, thereby causing instability of the array substrate.
  • a pre-formed base substrate and a gate are formed on the base substrate by chemical vapor deposition to form a gate insulating layer covering the gate, and then sequentially deposited on the gate insulating layer to form a non-conductive Crystal silicon layer and metal layer.
  • the material of the metal layer may be a stack combination of one or more of manganese, molybdenum, titanium, aluminum and copper; the amorphous silicon layer may be A-Si material; the gate The material of the insulating layer may be silicon oxide and/or silicon nitride; the gate may be a stack combination of one or more of molybdenum, titanium, aluminum, and copper; and the base substrate may be a glass substrate.
  • a metal layer on the amorphous silicon layer or the doped amorphous silicon layer After depositing a metal layer on the amorphous silicon layer or the doped amorphous silicon layer, apply photoresist on the metal layer.
  • the photoresist is exposed through the mask plate, specifically, the photoresist corresponding to the exposure area of the mask plate is completely exposed, and the photoresist corresponding to the half exposure area of the mask plate is partially exposed, and then Based on O 2, the exposed photoresist is dry-etched to etch away the photoresist that has been affected by light. Referring to FIG. 5, a photoresist mask 30 provided on the metal layer 20 is formed.
  • the thickness ⁇ hd of the photolithography mask 30 in the channel region is a preset thickness, and the thickness of the preset thickness ranges from 2000 ⁇ to 8000 ⁇ . Choose from 3000 ⁇ , 3700 ⁇ , 4200 ⁇ , 4500 ⁇ , 4700 ⁇ , 5000 ⁇ , 5500 ⁇ or 7000 ⁇ .
  • the photo dose energy (Photo Dose Energy) to achieve the control of the thickness value in the channel region after the lithography mask is formed.
  • setting the light dose energy of 41.5mj can correspondingly adjust the preset thickness of the lithography mask in the channel region to 5000 ⁇ .
  • the mask plate may be a single slit mask plate or a double slit mask plate.
  • the formed photoresist layer may have poor uniformity, and when etching the exposed photoresist layer to form a photoresist mask, due to factors such as etching rate , It will also cause the unevenness of the thickness of the lithography mask.
  • the metal layer and the amorphous silicon layer are not affected by the unevenness of the thickness of the lithography mask
  • the loss of the lithography mask outside the track area is excessive.
  • Step S20 etching the metal layer and the amorphous silicon layer outside the coverage of the lithography mask.
  • the metal layer and the amorphous silicon layer outside the coverage area of the lithography mask are sequentially etched. Specifically, based on the lithography mask, the metal layer outside the coverage area of the lithography mask is etched by wet etching, and then the amorphous silicon layer exposed by the etching of the metal layer is dry-etched.
  • the metal layer may be wet-etched based on a mixed compound, the mixed compound including H 3 PO 4 phosphoric acid, CH 3 COOH acetic acid, and HNO 3 nitric acid; the first drying of the amorphous silicon layer During the etching, the amorphous silicon layer may be dry-etched based on a first mixed gas including SF 6 sulfur hexafluoride gas and Cl 2 chlorine gas.
  • a mixed compound including H 3 PO 4 phosphoric acid, CH 3 COOH acetic acid, and HNO 3 nitric acid
  • a bias power supply can be added to achieve lateral etching of the amorphous silicon layer to reduce the amorphous silicon layer and the The difference in lateral width of the metal layer. It should be noted that by adding a bias power source, the lateral movement of the chemical reaction plasma can be caused to achieve the purpose of laterally etching the amorphous silicon layer.
  • Step S30 Perform ashing treatment on the lithography mask based on a mixed gas at a preset ratio to remove the lithography mask in the channel region.
  • the mixed gas includes sulfur hexafluoride SF 6 and oxygen O 2 , and the preset ratio is a ratio range of sulfur hexafluoride and oxygen of 0.02-0.1, wherein the volume flow rate of SF 6 in the mixed gas may be It is 200-800 sccm, and the volume flow rate of O 2 in the mixed gas may be 8000-10000 sccm.
  • the lithography mask is ashed based on a mixed gas including SF 6 at 800 sccm and O 2 at 8000 sccm, that is, based on a mixed gas pair with a ratio of SF 6 and O 2 at a preset ratio of 0.1
  • the lithography mask performs ashing treatment.
  • the lithography mask is ashed based on a mixed gas at a preset ratio to avoid excessive etching of the remaining lithography mask when removing the lithography mask in the channel region
  • the remaining photolithography mask 31 can cover enough metal layer 11 and amorphous silicon layer 21 after the first etching.
  • a bias power supply may be added to achieve lateral etching of the amorphous silicon layer 21 to reduce the amorphous silicon layer 21 and the lateral width difference ⁇ hc of the metal layer 11. It should be noted that by adding a bias power source, the lateral movement of the chemical reaction plasma can be caused to achieve the purpose of laterally etching the amorphous silicon layer.
  • Step S40 Based on the lithography mask after the ashing process, sequentially etch the metal layer and the amorphous silicon layer, and add a bias power source when etching the amorphous silicon layer to cover the metal layer
  • the amorphous silicon layer outside the channel region forms an array substrate structure.
  • the metal layer and the amorphous silicon layer are etched a second time. Specifically, the metal layer outside the coverage area of the lithography mask is wet-etched, wherein the metal layer in the channel region is etched to form the source electrode and the leakage level of the metal layer, and the bare exposure corresponds to the channel region Amorphous silicon layer.
  • the amorphous silicon layer outside the coverage of the metal layer is dry-etched, and at the same time, the amorphous silicon layer is dry-etched
  • the metal layer 13 can cover the amorphous layer outside the channel region. The silicon layer 23 and the lateral cut planes of the amorphous silicon layer and the metal layer outside the channel region are flush.
  • the metal layer may be wet-etched based on a mixed compound, the mixed compound including H 3 PO 4 , CH 3 COOH, and HNO 3 ; when the second dry etching is performed on the amorphous silicon layer,
  • the amorphous silicon layer may be dry-etched based on a second mixed gas including SF 6 , Cl 2 and He gas.
  • the amorphous silicon layer in the channel region is partially etched so that the amorphous silicon layer 23 is in the channel region
  • the remaining thickness ⁇ hd0 within the thickness range is 450 ⁇ -550 ⁇ , optionally, the remaining thickness may be 500 ⁇ . It should be noted that the remaining thickness formed in the channel region is 450 ⁇ -550
  • the amorphous silicon layer of ⁇ can reduce the leakage current to improve the problem that the thin film transistor is prone to image sticking.
  • the lateral cut planes of the amorphous silicon layer and the metal layer in the channel region can also be leveled.
  • the remaining photolithography mask is removed to form the base substrate, gate, gate insulating layer, and patterned amorphous Thin film transistor array substrate structure of silicon layer and metal layer.
  • a passivation layer covering the pattern including the amorphous silicon layer and the metal layer is formed on the gate insulating layer of the array substrate structure (that is, a passivation is formed on the array substrate structure Layer), and the pixel electrode forming the passivation via through the passivation layer, the thin film transistor array substrate can be formed.
  • the thin film transistor array substrate formed based on the array substrate structure may be configured to prepare a display panel.
  • a lithography mask is formed on the metal layer, and the lithography mask is in the trench
  • the thickness of the track area is a preset thickness; the metal layer and the amorphous silicon layer outside the coverage of the lithography mask are etched; and the lithography mask is ashed based on a preset ratio of mixed gas To remove the lithography mask in the channel region; based on the lithography mask after the ashing process, the metal layer and the amorphous silicon layer are etched in sequence, and when the amorphous silicon layer is etched A bias power supply is added so that the metal layer covers the amorphous silicon layer outside the channel region to form an array substrate structure.
  • the metal layer outside the back channel region is completely covered with the amorphous silicon layer, which solves the problem that the array substrate is prone to leakage , Thereby improving the stability of the array substrate.
  • the step of forming a lithography mask on the metal layer includes:
  • Step S50 After applying photoresist on the metal layer, expose the photoresist based on a mask.
  • Step S51 etching the exposed photoresist to form the photolithography mask with a thickness of the preset thickness in the channel region.
  • a photoresist is applied on the metal layer.
  • the photoresist is exposed through the mask plate, specifically, the photoresist corresponding to the exposure area of the mask plate is completely exposed, and the photoresist corresponding to the half exposure area of the mask plate is partially exposed, and then The exposed photoresist is dry-etched based on O 2 to etch away the photoresist that has been affected by light.
  • the thickness ⁇ hd of the formed photolithography mask 30 in the channel region is a preset thickness, and the thickness range of the preset thickness is 2000 ⁇ -8000 ⁇ , the preset thickness can be selected from 3000 ⁇ , 3700 ⁇ , 4200 ⁇ , 4500 ⁇ , 4700 ⁇ , 5000 ⁇ , 5500 ⁇ or 7000 ⁇ ; and the thickness of the interlayer thickness ⁇ hd1 of the island-like structure portion forming the lithographic mask corresponding to the non-exposed area of the mask plate is 18000 ⁇ -22000 ⁇ , optionally, the interlayer thickness ⁇ hd1 is 22000 ⁇ .
  • the thickness of the lithography mask in the channel region is in the range of 2000 ⁇ -8000 ⁇
  • the thickness of the interlayer thickness of the island structure outside the channel region in the formation of the lithography mask is 18000 ⁇ -22000 ⁇ can improve the uniformity of the lithography mask, so that the uniformity of the lithography mask reaches 25%-55%.
  • the photo dose energy (Photo Dose Energy) to achieve the control of the thickness value in the channel region after the lithography mask is formed.
  • setting the light dose energy of 41.5mj can correspondingly adjust the preset thickness of the lithography mask in the channel region to 5000 ⁇ .
  • the mask plate may be a single slit mask plate or a double slit mask plate.
  • the formed photoresist layer may have poor uniformity, and when etching the exposed photoresist layer to form a photoresist mask, due to factors such as etching rate , It will also cause the unevenness of the thickness of the lithography mask.
  • the thickness of the channel region by forming a lithography mask is 2000 ⁇ -8000 ⁇
  • the thickness of the interlayer layer forming the island-like structure portion of the lithography mask outside the channel region is 18000 ⁇ -22000 ⁇
  • the thickness of the interlayer layer forming the island-like structure portion of the lithography mask outside the channel region is 18000 ⁇ -22000 ⁇
  • the method for preparing the array substrate structure further includes:
  • Step S60 When etching the photoresist after exposure, the photoresist is over-etched at a preset intensity within a preset time, so that the critical size deviation of the formed photoresist mask is less than default value.
  • a photoresist is applied on the metal layer.
  • the photoresist is exposed through the mask plate, specifically, the photoresist corresponding to the exposure area of the mask plate is completely exposed, and the photoresist corresponding to the half exposure area of the mask plate is partially exposed, and then The exposed photoresist is dry-etched based on O 2 to etch away the photoresist that has been affected by light.
  • the photoresist when etching the exposed photoresist, the photoresist is over-etched at a preset intensity within a preset time, so that the formed photoresist mask The critical dimension deviation is less than the preset value. In this way, by reducing the deviation of the critical dimension generated during the formation of the lithography mask, accurate formation of the lithography mask can be achieved.
  • the present application also proposes an array substrate including an array substrate structure, a passivation layer, a passivation via, and a pixel electrode.
  • the array substrate structure is formed by the above method for preparing an array substrate structure.
  • the present application also provides a display panel, which is prepared and formed based on the above array substrate.
  • the methods in the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware, but in many cases the former is better Implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or part that contributes to the existing technology, and the computer software product is stored in a storage medium (such as ROM/RAM as described above) , Disk, CD), including several instructions to make a terminal device (which can be a TV, mobile phone, computer, server, air conditioner, or network equipment, etc.) to perform the method described in each embodiment of the present application.

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Abstract

一种阵列基板结构的制备方法，包括：在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜(S10)；蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层(S20)；基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜(S30)；依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源(S40)。由上述阵列基板结构制备方法形成的阵列基板以及显示面板。

Description

阵列基板结构的制备方法、阵列基板及显示面板
相关申请
本申请要求2018年12月25日申请的，申请号为201811595969.2，名称为“阵列基板结构的制备方法、阵列基板及显示面板”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及薄膜晶体管领域，尤其涉及一种阵列基板结构的制备方法、阵列基板以及显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。液晶显示器现已成为市场主流，其工作原理是液晶在电流的驱动下会发生偏转，使光线容易通过，从而显示图像。薄膜晶体管阵列基板包括金属层和非晶硅层，在阵列基板的基板结构在制备的过程中，可以将金属层所不能覆盖住的非晶硅层的部分，称为非晶硅冗余(A-Si tail)，非晶硅冗余可能会导致薄膜晶体管阵列基板产生光漏电流，造成阵列基板的不稳定。
发明内容
本申请的主要目的在于提供一种阵列基板结构的制备方法、阵列基板以及显示面板，通过在制备阵列基板结构时，实现金属层完全覆盖非晶硅层。
为实现上述目的，本申请提供一种阵列基板结构的制备方法，所述阵列基板结构的制备方法包括以下步骤：
在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度；
蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层；
基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜；以及
基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。
为实现上述目的，本申请还提供一种阵列基板，所述阵列基板包括阵列基板结构和钝化层，以及通过所述钝化层中的钝化过孔的像素电极，所述钝化层设置在所述阵列基板结构上，所述阵列基板结构由如下阵列基板结构的制备方法形成：
在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度；
蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层；
基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜；以及
基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。
为实现上述目的，本申请还提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括阵列基板结构和钝化层，以及通过所述钝化层中的钝化过孔的像素电极，所述钝化层设置在所述阵列基板结构上，所述阵列基板结构由如下阵列基板结构的制备方法形成：
在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度；
蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层；
基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜；以及
基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。
本申请提供的阵列基板结构的制备方法、阵列基板以及显示面板，在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度；蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层；基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜；基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。这样，通过去除在阵列基板结构制备过程中形成的，非晶硅层和金属层的横向宽度差，实现金属层完全覆盖非晶硅层，解决了阵列基板容易产生漏电的问题，从而提高了阵列基板的稳定性。
附图说明
图1为本申请阵列基板结构的制备方法的一实施例的流程示意图；
图2为本申请阵列基板结构的制备方法的另一实施例的流程示意图；
图3为本申请阵列基板结构的制备方法的又一实施例的流程示意图；
图4为本申请阵列基板结构的制备方法的一实施例的金属层和非晶硅层的横向宽度差值示例图；
图5为本申请阵列基板结构的制备方法的另一实施例的在金属层上形成的光刻掩膜示例图；
图6为本申请阵列基板结构的制备方法的又一实施例的灰化处理后的光刻掩膜示例图；
图7为本申请阵列基板结构的制备方法的又一实施例的基于灰化处理后的光刻掩膜蚀刻金属层和非晶硅层示例图；
图8为本申请阵列基板结构的制备方法的又一实施例的光刻掩膜示例图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不限定本申请。
本申请提供一种阵列基板结构的制备方法，通过去除在阵列基板结构制备过程中形成的，非晶硅层和金属层的横向宽度差，实现金属层完全覆盖非晶硅层，解决了阵列基板容易产生漏电的问题，从而提高了阵列基板的稳定性。
参照图1，在一实施例中，所述阵列基板结构的制备方法包括：
步骤S10、在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度。
本实施例中，薄膜晶体管阵列基板可以包括阵列基板结构、钝化膜或钝化层，以及通过钝化层中的钝化过孔的像素电极，其中，阵列基板结构又包括衬底基板、栅极、栅极绝缘层、非晶硅层（或者有源层）和金属层。当然，所述非晶硅层还可以包括掺杂型非晶硅层，所述掺杂型非晶硅层设于非晶硅层和金属层之间，即所述金属层设置在所述掺杂型非晶硅层之上。需要说明的是，所述掺杂型非晶硅层可以是N型掺杂非晶硅层，也可以是P型掺杂非晶硅层。
参照图4，在阵列基板结构通过4-Mask制程（四步光刻制程）制备的过程中，所最终形成的非晶硅层22的横向宽度大于金属层12的横向宽度，即金属层所不能覆盖住非晶硅层的部分具有一定的横向宽度差值Δhc。当然，也可以是将金属层所不能覆盖住的非晶硅层的部分，称为非晶硅冗余(A-Si tail)。而非晶硅冗余可能会导致薄膜晶体管阵列基板产生光漏电流，从而造成阵列基板的不稳定。
在制造薄膜晶体管基板结构时，预先形成的衬底基板和栅极，并采用化学气相法在衬底基板上沉积形成覆盖栅极的栅极绝缘层，然后在栅极绝缘层上依次沉积形成非晶硅层和金属层。
需要说明的是，所述金属层的材质可以是锰、钼、钛、铝和铜中的一种或多种的堆栈组合；所述非晶硅层可以是A-Si材质；所述栅极绝缘层的材质可以是氧化硅和/或氮化硅；所述栅极可以是钼、钛、铝和铜中的一种或多种的堆栈组合；所述衬底基板可以是玻璃基板。
在非晶硅层或者掺杂型非晶硅层上沉积形成金属层后，在金属层上涂抹光刻胶。通过掩膜板对所述光刻胶进行曝光，具体地，对与掩膜板曝光区域对应的光刻胶进行完全曝光，对与掩膜板半曝光区域对应的光刻胶进行部分曝光，然后基于O 2对曝光后的光刻胶进行干蚀刻，以蚀刻掉已受光照影响的光刻胶，参照图5，形成设于金属层20上的光刻掩膜30，其中，在蚀刻与掩膜板半曝光区域对应的光刻胶后，形成光刻掩膜30在沟道区域的厚度Δhd为预设厚度，所述预设厚度的厚度范围为2000Å-8000 Å，所述预设厚度可选为3000 Å、3700 Å、4200 Å、4500 Å、4700 Å、5000 Å、5500 Å或者7000 Å。
具体地，在设置光刻曝光参数时，可以通过调配掩膜板半曝光区域的光剂量能量（Photo Dose Energy）的热值，实现对光刻掩膜形成后的在沟道区域的厚度值的调控。比如，设置41.5mj的光剂量能量，可对应调控出光刻掩膜在沟道区域的预设厚度为5000 Å。
需要说明的是，所述掩膜板可以是单缝隙掩膜板，也可以是双缝隙掩膜板。
需要说的是，在涂抹光刻胶时，所形成的光刻胶层可能均匀性较差，以及在蚀刻曝光后的光刻胶层以形成光刻掩膜时，因蚀刻速率等因素的影响，也会造成光刻掩膜的膜厚的不均匀性。这样，通过形成在沟道区域的厚度达到预设厚度的光刻掩膜，避免在后续4-Mask制程中，因光刻掩膜的膜厚的不均匀性而对金属层和非晶硅层蚀刻时造成的影响，同时又能避免在后续对光刻掩膜进行灰化处理时，因光刻掩膜在沟道区域的厚度值过大而造成的灰化时间过长，而导致的沟道区域外的光刻掩膜损耗过大。
步骤S20、蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层。
在金属层上形成光刻掩膜后，基于所述光刻掩膜，依次蚀刻所述光刻掩膜覆盖范围外的金属层和非晶硅层。具体地，基于所述光刻掩膜，通过湿蚀刻，蚀刻光刻掩膜覆盖范围外的金属层，然后对因金属层蚀刻后裸露出来的非晶硅层进行干蚀刻。
具体地，可以是基于混合化合物对所述金属层进行湿蚀刻，所述混合化合物包括H 3PO 4磷酸、CH 3COOH乙酸和HNO 3硝酸；在对所述非晶硅层进行第一次干蚀刻时，可以是基于第一混合气体对非晶硅层进行干蚀刻，所述第一混合气体包括SF 6六氟化硫气体和Cl 2氯气。
当然，在对因金属层蚀刻后裸露出来的非晶硅层进行干蚀刻时，可以通过加入偏压电源，实现对所述非晶硅层进行侧向蚀刻，以减少所述非晶硅层和所述金属层的横向宽度差值。需要说明的是，通过加入偏压电源，能够引起化合反应电浆的横向移动，以达到对非晶硅层进行侧向蚀刻的目的。
步骤S30、基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜。
所述混合气体包括六氟化硫SF 6和氧气O 2，所述预设比率为六氟化硫和氧气的比值范围为0.02-0.1，其中，所述混合气体中SF 6的体积流量范围可以是200-800sccm，所述混合气体中O 2 的体积流量范围可以是8000-10000sccm。
比如，基于包括800sccm的SF 6和8000 sccm的O 2的混合气体对所述光刻掩膜进行灰化处理，即是基于预设比率为SF 6和O 2的比值为0.1的混合气体对所述光刻掩膜进行灰化处理。
参照图6，基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以在去除沟道区域的光刻掩膜时，避免对其余光刻掩膜进行过多的蚀刻，实现在保证裸露出沟道区域的金属层11的前提下，剩余的光刻掩膜31能覆盖足够多的经过第一次蚀刻后的金属层11和非晶硅层21。
在基于预设比率的混合气体对所述光刻掩膜进行灰化处理时，可以通过加入偏压电源，实现对所述非晶硅层21进行侧向蚀刻，以减少所述非晶硅层21和所述金属层11的横向宽度差值Δhc。需要说明的是，通过加入偏压电源，能够引起化合反应电浆的横向移动，以达到对非晶硅层进行侧向蚀刻的目的。
步骤S40、基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。
基于灰化处理后的光刻掩膜，对金属层和非晶硅层进行第二次蚀刻。具体地，对所述光刻掩膜覆盖范围外的金属层进行湿蚀刻，其中，蚀刻沟道区域内的金属层，以形成金属层的源电极和漏电级，以及裸露出与沟道区域对应的非晶硅层。然后基于灰化处理后的光刻掩膜，以及湿蚀刻后的金属层，对所述金属层覆盖范围外的非晶硅层进行干蚀刻，同时，在对所述非晶硅层进行干蚀刻时加入偏压电源，对所述非晶硅层进行侧向蚀刻，以去除非晶硅层和金属层的横向宽度差值，参照图7，使金属层13能覆盖沟道区域外的非晶硅层23，及使沟道区域外的非晶硅层和金属层的侧向切面平齐。
具体地，可以是 基于混合化合物对所述金属层进行湿蚀刻，所述混合化合物包括H 3PO 4、CH 3COOH和HNO 3；在对所述非晶硅层进行第二次干蚀刻时，可以是基于第二混合气体对非晶硅层进行干蚀刻，所述第二混合气体包括SF 6、Cl 2和He气。
需要说明的是，在对沟道区域内的非晶硅层进行干蚀刻时，参照图7，对沟道区域内的非晶硅层进行部分蚀刻，以使非晶硅层23在沟道区域内的剩余厚度Δhd0的厚度范围为450Å-550 Å，可选地，剩余厚度可以为500 Å。需要说明的是，通过形成在沟道区域内的剩余厚度为450Å-550 Å的非晶硅层，能够减少漏电流，以改善薄膜晶体管容易出现图像残留的问题。
当然，通过加入偏压电源以对所述非晶硅层进行侧向蚀刻时，也能使沟道区域内的非晶硅层和金属层的侧向切面平齐。
在使所述金属层覆盖沟道区域外的所述非晶硅层后，去除剩余的光刻掩膜，即可形成包括衬底基板、栅极、栅极绝缘层，以及图形化的非晶硅层和金属层的薄膜晶体管阵列基板结构。
需要说明的是，在所述阵列基板结构的栅极绝缘层上，形成覆盖包括所述非晶硅层和所述金属层的图形的钝化层（即在所述阵列基板结构上形成钝化层），以及形成通过钝化层的钝化过孔的像素电极，即可形成薄膜晶体管阵列基板。
进一步地，基于所述阵列基板结构形成的薄膜晶体管阵列基板，可设置为制备显示面板。
在一实施例中，在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度；蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层；基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜；基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。这样，通过去除在阵列基板结构制备过程中形成的非晶硅层和金属层的横向宽度差，实现背沟道区域外的金属层完全覆盖非晶硅层，解决了阵列基板容易产生漏电的问题，从而提高了阵列基板的稳定性。
在另一实施例中，如图2所示，在上述图1所示的实施例基础上，所述在所述金属层上形成光刻掩膜的步骤包括：
步骤S50、在所述金属层上涂抹光刻胶后，基于掩膜板对所述光刻胶进行曝光。
步骤S51、蚀刻曝光后的所述光刻胶，以形成在沟道区域的厚度为所述预设厚度的所述光刻掩膜。
本实施例中，在非晶硅层或者掺杂型非晶硅层上沉积形成金属层后，在金属层上涂抹光刻胶。通过掩膜板对所述光刻胶进行曝光，具体地，对与掩膜板曝光区域对应的光刻胶进行完全曝光，对与掩膜板半曝光区域对应的光刻胶进行部分曝光，然后基于O 2对曝光后的光刻胶进行干蚀刻，以蚀刻掉已受光照影响的光刻胶。
参照图8，在蚀刻与掩膜板半曝光区域对应的光刻胶后，形成光刻掩膜30在沟道区域的厚度Δhd为预设厚度，所述预设厚度的厚度范围为2000Å-8000 Å，所述预设厚度可选为3000 Å、3700 Å、4200 Å、4500 Å、4700 Å、5000 Å、5500 Å或者7000 Å；以及形成与掩膜板非曝光区域对应的光刻掩膜的岛状结构部分的层间厚度Δhd1的范围为18000 Å-22000 Å，可选地，所述层间厚度Δhd1为22000 Å。这样，通过形成光刻掩膜在沟道区域的厚度范围为2000 Å-8000 Å，以及形成光刻掩膜在沟道区域外的岛状结构部分的层间厚度范围为18000 Å-22000 Å，可以实现改善光刻掩膜的均匀度，以使光刻掩膜的均匀度达到25%-55%。
具体地，在设置光刻曝光参数时，可以通过调配掩膜板半曝光区域的光剂量能量（Photo Dose Energy）的热值，实现对光刻掩膜形成后的在沟道区域的厚度值的调控。比如，设置41.5mj的光剂量能量，可对应调控出光刻掩膜在沟道区域的预设厚度为5000 Å。
需要说明的是，所述掩膜板可以是单缝隙掩膜板，也可以是双缝隙掩膜板。
需要说的是，在涂抹光刻胶时，所形成的光刻胶层可能均匀性较差，以及在蚀刻曝光后的光刻胶层以形成光刻掩膜时，因蚀刻速率等因素的影响，也会造成光刻掩膜的膜厚的不均匀性。
在其中一实施例中，通过形成光刻掩膜在沟道区域的厚度范围为2000 Å-8000 Å，以及形成光刻掩膜在沟道区域外的岛状结构部分的层间厚度范围为18000 Å-22000 Å，可以实现改善光刻掩膜的均匀度，降低光刻掩膜的不均匀性，从而避免在后续4-Mask制程中，因光刻掩膜的膜厚的不均匀性而对金属层和非晶硅层蚀刻时造成的影响，同时又能避免在后续对光刻掩膜进行灰化处理时，因光刻掩膜在沟道区域的厚度值过大而造成的灰化时间过长，而导致的沟道区域外的光刻掩膜损耗过大。
在又一实施例中，如图3所示，在上述图1至图2的实施例基础上，所述阵列基板结构的制备方法还包括：
步骤S60、在蚀刻曝光后的所述光刻胶时，通过在预设时间内对所述光刻胶进行预设强度的过蚀刻，以使形成的所述光刻掩膜的临界尺寸偏差小于预设值。
本实施例中，在非晶硅层或者掺杂型非晶硅层上沉积形成金属层后，在金属层上涂抹光刻胶。通过掩膜板对所述光刻胶进行曝光，具体地，对与掩膜板曝光区域对应的光刻胶进行完全曝光，对与掩膜板半曝光区域对应的光刻胶进行部分曝光，然后基于 O 2对曝光后的光刻胶进行干蚀刻，以蚀刻掉已受光照影响的光刻胶。
在蚀刻曝光后的所述光刻胶的同时，通过在预设时间为76sec的时间内，对所述光刻胶进行预设强度为10%的过蚀刻（Over Etch），以使形成的所述光刻掩膜的临界尺寸偏差（Critical Dimension Bias）小于预设值，所述预设值为0.94μm。
在其中一实施例中，在蚀刻曝光后的所述光刻胶时，通过在预设时间内对所述光刻胶进行预设强度的过蚀刻，以使形成的所述光刻掩膜的临界尺寸偏差小于预设值。这样，通过减少光刻掩膜形成时产生的临界尺寸偏差，能实现精准形成光刻掩膜。
此外，本申请还提出一种阵列基板，所述阵列基板包括阵列基板结构、钝化层、钝化过孔和像素电极，所述阵列基板结构由上述阵列基板结构的制备方法形成。
此外，本申请还提供一种显示面板，所述显示面板基于上述阵列基板制备形成。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是电视机，手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (17)

  1. 一种阵列基板结构的制备方法，其中，所述阵列基板结构的制备方法包括以下步骤：
    在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度；
    蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层；
    基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜；以及
    基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。
  2. 如权利要求1所述的阵列基板结构的制备方法，其中，所述在所述金属层上形成光刻掩膜的步骤包括：
    在所述金属层上涂抹光刻胶后，基于掩膜板对所述光刻胶进行曝光；以及
    蚀刻曝光后的所述光刻胶，以形成在沟道区域的厚度为所述预设厚度的所述光刻掩膜。
  3. 如权利要求2所述的阵列基板结构的制备方法，其中，所述阵列基板结构的制备方法还包括：
    在蚀刻曝光后的所述光刻胶时，通过在预设时间内对所述光刻胶进行预设强度的过蚀刻，以使形成的所述光刻掩膜的临界尺寸偏差小于预设值。
  4. 如权利要求3所述的阵列基板结构的制备方法，其中，所述预设值为0.94μm。
  5. 如权利要求1所述的阵列基板结构的制备方法，其中，所述预设厚度的厚度范围为2000Å-8000 Å。
  6. 如权利要求1所述的阵列基板结构的制备方法，其中，所述阵列基板结构的制备方法还包括：
    在基于预设比率的混合气体对所述光刻掩膜进行灰化处理时，通过加入偏压电源，对所述非晶硅层进行侧向蚀刻，以减少所述非晶硅层和所述金属层的横向宽度差值。
  7. 如权利要求1所述的阵列基板结构的制备方法，其中，所述混合气体包括六氟化硫和氧气，所述预设比率为六氟化硫和氧气的比值范围为0.02-0.1。
  8. 如权利要求7所述的阵列基板结构的制备方法，其中，所述混合气体中六氟化硫的体积流量范围为200-800sccm。
  9. 如权利要求7所述的阵列基板结构的制备方法，其中，所述混合气体中氧气的体积流量范围为8000-10000sccm。
  10. 如权利要求1所述的阵列基板结构的制备方法，其中，所述基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构的步骤包括：
    基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层；以及
    去除所述光刻掩膜，形成阵列基板结构。
  11. 如权利要求10所述的阵列基板结构的制备方法，其中，所述基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层的步骤包括：
    基于灰化处理后的光刻掩膜，对所述光刻掩膜覆盖范围外的所述金属层进行湿蚀刻，其中，蚀刻沟道区域内的所述金属层，以形成所述金属层的源电极和漏电级，以及裸露出与沟道区域对应的所述非晶硅层；以及
    对所述金属层覆盖范围外的所述非晶硅层进行干蚀刻，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层。
  12. 如权利要求11所述的阵列基板结构的制备方法，其中，所述对所述金属层覆盖范围外的所述非晶硅层进行干蚀刻的步骤包括：
    对所述金属层覆盖范围外的所述非晶硅层进行干蚀刻，使所述非晶硅层在沟道区域内的剩余厚度的厚度范围为450Å-550 Å。
  13. 如权利要求1所述的阵列基板结构的制备方法，其中，所述非晶硅层包括掺杂型非晶硅层，所述金属层设置在所述掺杂型非晶硅层之上。
  14. 如权利要求1所述的阵列基板结构的制备方法，其中，所述光刻掩膜的均匀度取值范围为25%-55%。
  15. 如权利要求1所述的阵列基板结构的制备方法，其中，所述光刻掩膜在沟道区域外的岛状结构部分的层间厚度范围为18000 Å-22000 Å。
  16. 一种阵列基板，其中，所述阵列基板包括阵列基板结构和钝化层，以及通过所述钝化层中的钝化过孔的像素电极，所述钝化层设置在所述阵列基板结构上，所述阵列基板结构由如下阵列基板结构的制备方法形成：
    在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度；
    蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层；
    基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜；以及
    基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。
  17. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括阵列基板结构和钝化层，以及通过所述钝化层中的钝化过孔的像素电极，所述钝化层设置在所述阵列基板结构上，所述阵列基板结构由如下阵列基板结构的制备方法形成：
    在衬底基板上依次形成栅极、栅极绝缘层、非晶硅层和金属层后，在所述金属层上形成光刻掩膜，所述光刻掩膜在沟道区域的厚度为预设厚度；
    蚀刻所述光刻掩膜覆盖范围外的所述金属层和所述非晶硅层；
    基于预设比率的混合气体对所述光刻掩膜进行灰化处理，以去除沟道区域内的所述光刻掩膜；以及
    基于灰化处理后的光刻掩膜，依次蚀刻所述金属层和所述非晶硅层，并在蚀刻所述非晶硅层时加入偏压电源，以使所述金属层覆盖沟道区域外的所述非晶硅层，形成阵列基板结构。
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