WO2017054259A1 - 液晶显示面板、阵列基板及其制造方法 - Google Patents

液晶显示面板、阵列基板及其制造方法 Download PDF

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Publication number
WO2017054259A1
WO2017054259A1 PCT/CN2015/092353 CN2015092353W WO2017054259A1 WO 2017054259 A1 WO2017054259 A1 WO 2017054259A1 CN 2015092353 W CN2015092353 W CN 2015092353W WO 2017054259 A1 WO2017054259 A1 WO 2017054259A1
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Prior art keywords
layer
drain
source
doped region
ions
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PCT/CN2015/092353
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English (en)
French (fr)
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肖军城
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/890,677 priority Critical patent/US10042211B2/en
Publication of WO2017054259A1 publication Critical patent/WO2017054259A1/zh
Priority to US16/055,237 priority patent/US10409115B2/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/0102—Constructional details, not otherwise provided for in this subclass
    • G02F1/0107—Gaskets, spacers or sealing of cells; Filling and closing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H01L21/0425—Making electrodes
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13396—Spacers having different sizes
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13398—Spacer materials; Spacer properties
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F2201/50—Protective arrangements
    • G02F2201/501—Blocking layers, e.g. against migration of ions

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel, an array substrate, and a method of fabricating the same.
  • Low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) technology is another new technology in the field of flat panel displays, following the next generation of amorphous silicon (a-Si).
  • LTPS Low Temperature Poly-Silicon
  • a-Si amorphous silicon
  • the low-temperature polysilicon type display panel has the advantages of faster electron mobility, smaller film circuit area, higher resolution, lower power consumption, and higher stability.
  • the low temperature polysilicon type display panel refers to a display panel made of low temperature polysilicon as an active layer of the thin film transistor TFT.
  • Low-temperature polysilicon thin film transistor preparation process temperature is usually lower than 600 ° C, can be applied to ordinary glass substrates, usually by means of excimer laser annealing laser crystallization, using a certain energy of excimer laser laser irradiation of amorphous silicon Amorphous silicon is crystallized into polycrystalline silicon.
  • leakage is an important factor affecting the performance of the thin film transistor and the display effect of the display panel. If the thin film transistor leaks, it is prone to problems such as reduced contrast, flicker and crosstalk. Therefore, how to effectively reduce the leakage of the low-temperature polysilicon thin film transistor becomes an urgent technical problem to be solved.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display panel, an array substrate, and a manufacturing method thereof, which can effectively reduce leakage of a thin film transistor.
  • a technical solution adopted by the present invention is to provide a method for manufacturing an array substrate, comprising: forming a buffer layer on a substrate; forming a low-temperature polysilicon active layer on the buffer layer by using a first mask Forming a gate insulating layer on the low temperature polysilicon active layer; forming a gate layer on the gate insulating layer by using a second mask; forming an interlayer layer on the gate layer by using a third mask And forming, by the electrical layer, two via holes formed on the interlayer dielectric layer; removing portions of the gate insulating layer corresponding to the two via holes of the interlayer dielectric layer to expose a two-part low-temperature polysilicon active layer; performing ion doping treatment on the exposed two-part low-temperature polysilicon active layer to respectively form a source doped region and a drain doped region of the low-temperature polysilicon active layer; Forming a controllable resistive spacer layer on the source doped region and the drain
  • controllable resistive spacer layer is an amorphous silicon layer
  • step of performing ion doping treatment on the exposed two-part low-temperature polysilicon active layer comprises: exposing the exposed two-part low-temperature polysilicon active layer Ion implantation is performed, the concentration of the implanted ions is greater than or equal to a first predetermined value, and the implanted ions are boron ions, phosphorus ions or arsenic ions.
  • controllable resistive spacer layer is an amorphous silicon layer
  • step of performing ion doping treatment on the exposed two-part low-temperature polysilicon active layer comprises: exposing the exposed two-part low-temperature polysilicon active layer Performing ion implantation, the concentration of the implanted ions is less than a first predetermined value, and the implanted ions are boron ions, phosphorus ions or arsenic ions; the forming of the source doped region and the drain doped region respectively
  • the method comprises: performing ion implantation on the controllable resistor spacer layer on the source doping region and the drain doping region, and the concentration of the implanted ions is greater than or equal to a second predetermined value .
  • an array substrate including a low temperature polysilicon active layer, a gate layer, an interlayer dielectric layer, a source layer, and a drain formed on the substrate.
  • the interlayer dielectric layer is on the low temperature polysilicon active layer
  • the source layer and the drain layer are on the interlayer dielectric layer
  • the gate layer is located on the low temperature polysilicon Under the active layer or between the low temperature polysilicon active layer and the interlayer dielectric layer
  • the interlayer dielectric layer is provided with two via holes
  • the low temperature polysilicon active layer includes a source a doped region and a drain doped region, the source layer and the drain layer respectively passing through two via holes on the interlayer dielectric layer and the source doped region and the drain doped region Connected, and at least between the source layer and the source doped region or between the drain layer and the drain doped region, a controllable resist spacer layer, the controllable resistor spacer layer Forming a
  • the controllable resistor spacer layer is disposed between the drain layer and the interlayer dielectric layer, respectively.
  • controllable resistive spacer layer is an amorphous silicon layer, and the concentration of ions doped by the source doped region and the drain doped region is greater than or equal to a first predetermined value, and the ion is boron Ion, phosphorus or arsenic ions.
  • controllable resistive spacer layer is an amorphous silicon layer, and the concentration of ions doped by the source doped region and the drain doped region is less than a first predetermined value, and the doped ions are a boron ion, a phosphorus ion or an arsenic ion; a side of the controllable resistive spacer layer between the source layer and the source doped region adjacent to the source layer is doped with a concentration greater than or equal to a second a predetermined value of ions, a side of the controllable resistive spacer layer between the drain layer and the drain doped region adjacent to the drain layer is doped with ions having a concentration greater than or equal to a second predetermined value,
  • the ions having a concentration greater than or equal to a second predetermined value are boron ions, phosphorus ions or arsenic ions.
  • a liquid crystal display panel including an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate
  • the array substrate includes a low temperature polysilicon active layer, a gate layer, an interlayer dielectric layer, a source layer and a drain layer on the substrate, the interlayer dielectric layer being on the low temperature polysilicon active layer, the source layer And the drain layer is located on the interlayer dielectric layer
  • the gate layer is located under the low temperature polysilicon active layer or between the low temperature polysilicon active layer and the interlayer dielectric layer
  • the low temperature polysilicon active layer includes a source doped region and a drain doped region, and the source layer and the drain layer respectively pass through Two via holes on the interlayer dielectric layer are connected to the source doped region and the drain doped region, and at least between the source layer and the source doped region or the drain
  • the controllable resistor spacer layer is disposed between the drain layer and the interlayer dielectric layer, respectively.
  • controllable resistive spacer layer is an amorphous silicon layer, and the concentration of ions doped by the source doped region and the drain doped region is greater than or equal to a first predetermined value, and the ion is boron Ion, phosphorus or arsenic ions.
  • controllable resistive spacer layer is an amorphous silicon layer, and the concentration of ions doped by the source doped region and the drain doped region is less than a first predetermined value, and the doped ions are a boron ion, a phosphorus ion or an arsenic ion; a side of the controllable resistive spacer layer between the source layer and the source doped region adjacent to the source layer is doped with a concentration greater than or equal to a second a predetermined value of ions, a side of the controllable resistive spacer layer between the drain layer and the drain doped region adjacent to the drain layer is doped with ions having a concentration greater than or equal to a second predetermined value,
  • the ions having a concentration greater than or equal to a second predetermined value are boron ions, phosphorus ions or arsenic ions.
  • the invention has the beneficial effects that, in the manufacturing method of the array substrate of the present invention, the controllable resistance interval is formed on at least the source doped region or the drain doped region of the low temperature polysilicon layer. a layer, the doped region formed with the controllable resistor spacer layer is connected to the corresponding source layer or the drain layer through the controllable resistor spacer layer, and the controllable resistor spacer layer flows through when the gate layer is not applied with the turn-on signal
  • the current acts as a partition, whereby the carriers of the low-temperature polysilicon active layer can be effectively blocked, thereby reducing leakage of the thin film device.
  • FIG. 1 is a flow chart showing an embodiment of a method of manufacturing an array substrate of the present invention
  • FIG. 2 is a schematic structural view of an embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 3 is a schematic structural view of another embodiment of a method for fabricating an array substrate of the present invention.
  • FIG. 4 is a schematic diagram of a method for fabricating an array substrate of the present invention, in which a source layer and a drain layer are respectively formed on two controllable resistor spacer layers on an interlayer dielectric layer by using a third mask; Flowchart after the step of connecting the pole and drain layers to the source doped region and the drain doped region, respectively;
  • FIG. 5 is a schematic diagram of a method for fabricating an array substrate of the present invention, in which a source layer and a drain layer are respectively formed on two controllable resistor spacer layers on an interlayer dielectric layer by using a third mask;
  • FIG. 6 is a schematic structural view of another embodiment of a method for manufacturing an array substrate of the present invention.
  • FIG. 7 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 8 is a schematic structural view of another embodiment of an array substrate of the present invention.
  • FIG. 9 is a schematic structural view of still another embodiment of the array substrate of the present invention.
  • FIG. 10 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • FIG. 1 is a flow chart of a specific embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 2 is a schematic structural view of a method for fabricating an array substrate according to the present invention.
  • the manufacturing method specifically includes the following steps:
  • Step S101 forming a low temperature polysilicon active layer on the substrate by using the first mask, wherein the gate layer is formed by using the second mask before or after forming the low temperature polysilicon active layer.
  • the substrate may be a glass substrate.
  • a buffer layer 22 is formed on the substrate 21, and the buffer layer 22 serves as a buffer to prevent damage to the substrate 21 by the subsequent etching process. .
  • a low temperature polysilicon active layer 23 is formed on the buffer layer 22.
  • the specific process for forming the low temperature polysilicon active layer may be as follows: depositing an amorphous silicon layer on the buffer layer 22, then forming a photoresist layer on the amorphous silicon layer, and then using a low temperature polysilicon active layer The first mask of the pattern illuminates the photoresist layer, and then the exposed photoresist layer is treated with a developer to form a low temperature polysilicon active layer on the photoresist layer.
  • the amorphous silicon layer is laser irradiated by laser annealing to form a low temperature polysilicon active layer 23.
  • the thin film transistor formed in the present embodiment is a top gate thin film transistor.
  • the gate insulating layer 24 is formed on the low temperature polysilicon active layer 23.
  • the gate layer 25 is formed on the gate insulating layer 24 by the second photomask.
  • Step S102 forming an interlayer dielectric layer on the low temperature polysilicon active layer by using a third mask, and forming two via holes on the interlayer dielectric layer to expose two portions of the low temperature polysilicon active layer.
  • an interlayer dielectric layer (inter layer) is formed on the gate layer 25 by using the third photomask.
  • the dielectric, ILD 26, is formed with two via holes 261 and 262 formed in the interlayer dielectric layer 26. Then, portions of the two via holes 261, 262 of the corresponding interlayer dielectric layer 26 in the gate insulating layer 24 are removed by etching or the like, so that two via holes are also formed on the gate insulating layer 24, respectively. Two portions of the low temperature polysilicon active layer 23 are exposed.
  • Step S103 performing ion doping treatment on the exposed two-part low-temperature polysilicon active layer to form a source doped region and a drain doped region of the low-temperature polysilicon active layer, respectively.
  • the exposed two-part low temperature polysilicon active layer 23 is ion doped to form a source doped region 231 and a drain doped region 232 of the low temperature polysilicon active layer 23, respectively.
  • Step S104 forming a controllable resistive spacer layer on at least the source doped region or the drain doped region, wherein the controllable resistive spacer layer forms a blocking effect on the current flowing when the gate layer is not applied with the turn-on signal, and When the gate layer applies an on signal, it conducts a conduction effect on the current flowing.
  • a controllable resistor spacer layer may be formed on the source doped region or the drain doped region, or a layer of controllable resistor spacer may be respectively formed on the source doped region and the drain doped region.
  • a controllable resistor spacer layer 271 is formed on the source doping region 231.
  • the controllable resistor spacer layer 271 forms a blocking effect on the current flowing when the gate layer 25 is not applied with the turn-on signal, and forms a conducting effect on the current flowing when the gate layer 25 applies the turn-on signal.
  • Step S105 forming a source layer and a drain layer on the interlayer dielectric layer by using the fourth mask, and passing the source layer and the drain layer respectively through the two via holes and the source on the interlayer dielectric layer
  • the doped region is connected to the drain doped region, and the doped region in which the controllable resistive spacer layer is formed is connected to the corresponding source or drain layer through the controllable resistive spacer layer.
  • a source layer 281 and a drain layer 282 are formed on the interlayer dielectric layer 26 by using a fourth mask, and the source layer 281 is sequentially turned on through the interlayer dielectric layer 26.
  • the via holes 261 and the via holes on the gate insulating layer 24 are connected to the source doping region 231 of the low temperature polysilicon layer 23, and the drain layer 282 sequentially passes through the via holes 262 and the gate insulating layer 24 on the interlayer insulating layer 26.
  • the upper via is connected to the drain doping region 232 of the low temperature polysilicon layer 23.
  • the source layer 281 is connected to the source doping region 231 through the controllable resistor spacer layer 271 due to the formation of the controllable resistor spacer layer 271 on the source doping region 231.
  • the gate layer 25, the source layer 281, and the drain layer 282 are formed as the gate, the source, and the drain of the thin film transistor on the array substrate, respectively.
  • a controllable resistive spacer layer 271 is disposed between the source layer 281 and the source doped region 231 of the low temperature polysilicon active layer 23, and the controllable resistive spacer layer 271 is not applied to the gate layer 25.
  • a blocking effect is formed on the current flowing through, thereby achieving a blocking effect on carriers of the low-temperature polysilicon active layer 271, thereby effectively reducing leakage of the formed thin film transistor.
  • the controllable resistive spacer layer 271 forms a conducting effect on the current flowing when the turn-on signal is applied to the gate layer 25, thereby enabling the source layer 281 and the drain layer 282 to be turned on.
  • FIG. 3 is a schematic structural view of another embodiment of a method for manufacturing an array substrate according to the present invention, wherein elements of the same reference numerals have the same functions.
  • the low temperature polysilicon active layer 23 is formed in step S301; the gate layer 25, the gate layer 25 and the low temperature polysilicon active layer 23 are formed in step S302.
  • the gate insulating layer 24 is spaced apart; the interlayer dielectric layer 26 is formed in step S303, and the two portions of the low temperature polysilicon active layer 23 are exposed; in step S304, the exposed low temperature polysilicon active layer 23 is ion doped to A source doping region 231 and a drain doping region 232 of a low temperature polysilicon active layer are formed.
  • the specific step of performing ion doping treatment on the exposed low-temperature polysilicon active layer 23 is: performing ion implantation on the exposed low-temperature polysilicon active layer 23 . That is, the exposed low-temperature polysilicon active layer 23 is doped by ion implantation, and the interlayer dielectric layer 26 can be used as a mask for ion implantation during the implantation process, thereby eliminating the need for an additional mask. Ion doping is completed.
  • the concentration of the implanted ions is greater than or equal to a first predetermined value, that is, doping with a high concentration of ions, so that the source doped region and the drain doped region are heavily doped regions (P+).
  • the first predetermined value is a boundary value of the ion concentration that enables the source doping region and the drain doping region to be the heavily doped region, and can be selected according to actual needs.
  • the ion to be implanted in the present embodiment is boron ion, and of course, phosphorus ion or arsenic ion may be used. Further, the amount of ions implanted and the implantation power used can be controlled to adjust the penetration depth of the implanted ions in the low temperature polysilicon active layer 23.
  • the step of forming a controllable resistive spacer layer on at least the source doped region or the drain doped region includes: forming a controllable resistor spacer layer on both the source doped region and the drain doped region, And using the fourth photomask to form two controllable resistor spacer layers respectively corresponding to the source layer and the drain layer on the interlayer dielectric layer.
  • step S305 in addition to forming the controllable resistor spacer layer 271 on the source doping region 231, a controllable resistor spacer layer is formed on the drain doping region 232 and the interlayer dielectric layer 26, respectively. 272, 273, 274. Among them, the controllable resistance spacer layers 273 and 274 correspond to the source layer 281 and the drain layer 282, respectively. In addition, the controllable resistive spacer layers 273, 274 on the interlayer dielectric layer 26 are formed using a fourth mask, the same as the mask forming the source layers 281, 282.
  • the step of forming the source layer and the drain layer on the interlayer dielectric layer by using the fourth mask specifically includes: using the fourth mask on the interlayer dielectric layer 26
  • a source layer 281 and a drain layer 282 are formed on the controllable resistor spacer layers 273 and 274, respectively.
  • the source layer 281 and the drain layer 282 pass through the controllable resistor spacer layers 271 and 273 and the source doping region 231 and the drain, respectively. Doped regions 232 are connected.
  • controllable resistor spacer layer is formed between each of the interlayer dielectric layers 26, so that leakage of the formed thin film transistor can be further reduced.
  • controllable resistive spacer layers 273, 274 and the source layers 281, 282 on the interlayer dielectric layer 26 are all formed using the same mask, which can reduce the number of masks and facilitate the process.
  • controllable resistor spacer layer is an amorphous silicon layer (a-si), and the ohmic contact of the source layer 281 and the drain layer 282 is corrected by the amorphous silicon layer, thereby effectively reducing leakage.
  • a-si amorphous silicon layer
  • the method further includes the following step:
  • Step S401 forming a first insulating layer on the source layer and the drain layer by using the fifth photomask, and exposing a part of the drain layer.
  • the first insulating layer 29 is formed on the source layer 281 and the drain layer 282 by the fifth photomask, and a portion of the drain layer 282 is exposed.
  • the first insulating layer 29 is formed on the source layer 281 and the exposed interlayer dielectric layer 26, and the first insulating layer 29 is not formed on the drain layer 282 to make the drain. Layer 282 is exposed.
  • the first insulating layer 29 may also be formed on the drain layer 282 as long as at least a portion of the drain layer 282 is exposed to facilitate subsequent drain layer 282 to be connected to the pixel electrodes on the array substrate.
  • Step S402 forming a first transparent electrode layer on the first insulating layer by using the sixth photomask.
  • the first transparent electrode layer does not cover the exposed drain layer, and is not connected to the exposed drain layer.
  • the first transparent electrode layer 31 is formed on the first insulating layer 29 by the sixth photomask, and the first transparent electrode layer 31 may be formed using an ITO material.
  • the first transparent electrode layer 31 is not covered with the exposed drain layer 282 and is not connected to the drain layer 282.
  • the first transparent electrode layer 31 is a common electrode layer of the array substrate.
  • Step S403 forming a second insulating layer on the first transparent electrode layer by using the seventh photomask, the second insulating layer not covering the exposed drain layer, and is not connected to the exposed drain layer.
  • the second insulating layer 32 is formed on the first transparent electrode layer 31 by the seventh photomask, and the second insulating layer 32 is not covered with the exposed source layer 282 so as to at least partially leak.
  • the pole layer 282 is exposed.
  • Step S404 forming a second transparent electrode layer on the second insulating layer by using the eighth photomask, and connecting the second transparent electrode layer to the exposed drain layer.
  • the second transparent electrode layer 33 is formed on the second insulating layer 32 by the eighth photomask, and the second transparent electrode layer 33 is connected to the exposed drain layer 282.
  • the second transparent electrode layer 33 is a pixel electrode layer of the array substrate, thereby implementing connection between the pixel electrode layer and the drain layer 282 to realize driving of the pixel electrode layer by the thin film transistor.
  • the formation of the thin film transistor to the pixel electrode layer can be completed by only eight masks, and the 3-4 masks are reduced compared with the existing CMOS process, which is advantageous for reducing the number of masks and Simplify process flow and improve device performance.
  • the gate layer may also be formed before the low temperature polysilicon active layer is formed, that is, the gate layer is formed on the substrate, then the gate insulating layer is formed on the gate layer, and then the gate insulating layer is formed.
  • a low temperature polysilicon active layer is formed thereon, and an interlayer dielectric layer is formed on the low temperature polysilicon active layer.
  • the formed thin film transistor may also be a bottom gate type thin film transistor.
  • controllable resistor spacer layer may be another semiconductor layer, such as a semiconductor layer which may be a germanium element, or may be a compound semiconductor layer such as a semiconductor layer such as gallium arsenide or gallium phosphide.
  • FIG. 6 is a schematic structural view of still another embodiment of the method for fabricating the array substrate of the present invention, wherein the same reference numerals are used in the drawings.
  • the controllable resistor spacer layer on the source doping region 231 and the drain doping region 232 is subjected to ion doping treatment.
  • step S601 the buffer layer 22 is formed on the substrate 21, and then the low temperature polysilicon active layer 23 is formed on the buffer layer 22 by the first mask.
  • step S602 a gate insulating layer 24 is formed on the low temperature polysilicon active layer 23, and then a gate layer 25 is formed on the gate insulating layer 24 by using a second mask.
  • step S603 an interlayer dielectric layer 26 is formed on the gate layer 25, and two via holes 261 and 262 are formed on the interlayer dielectric layer 26, and two corresponding gate insulating layers 24 are removed. Portions of the vias 261, 262 are exposed to expose the two portions of the low temperature polysilicon active layer 23.
  • step S604 the exposed two-part low-temperature polysilicon active layer 23 is subjected to ion doping treatment to form a source doping region 231' and a drain doping region 232' of the low-temperature polysilicon active layer 23, respectively.
  • the exposed low-temperature polysilicon active layer 23 is ion-doped by ion implantation.
  • the concentration of ions implanted into the low temperature polysilicon active layer 23 is less than a first predetermined value, that is, doping with low concentration ions, so that the source doping region 231' and the drain doping region 232'
  • a lightly doped region (P-) that is, LDD is formed on the low temperature polysilicon active layer 23 (Lightly Doped Drain, lightly doped drain) structure.
  • the implanted ions are boron ions, and of course, may be phosphorus ions or arsenic ions.
  • controllable resistor spacer layers 271, 272 are respectively formed on the source doping region 231' and the drain doping region 232', and are respectively formed on the interlayer dielectric layer 26 by using the fourth photomask.
  • the pole layer 281 and the drain layer 282 correspond to controllable resistive spacer layers 273, 274.
  • the controllable resistor spacer layers 271 to 274 are amorphous silicon layers.
  • controllable resistive spacer layers 271, 272 are formed on the source doping region 231' and the drain doping region 232', respectively, the source doping region 231' and the drain doping are formed.
  • the controllable resistive spacer layers 271, 272 on the impurity region 232' are ion implanted to ion doping the controllable resistive spacer layers 271, 272 to form doped regions 611 on the controllable resistive spacer layers 271, 272, respectively. 612.
  • the concentration of the implanted ions is greater than or equal to a second predetermined value, that is, the doped regions 611 and 612 on the controlled resistance spacer layers 271 and 272 are heavily doped.
  • the implanted ions are boron ions, and of course, may be phosphorus ions or arsenic ions.
  • the second predetermined value is a boundary value of the ion concentration that enables the doped regions 611, 612 to be heavily doped regions.
  • controllable resistive spacer layers 271, 272 are partially doped, that is, the depth of the implanted ions in the controllable resistive spacer layers 271, 272 is less than the thickness of the controllable resistive spacer layers 271, 272, and the doped regions 611, 612 The controllable resist spacer layers 271, 272 are not completely penetrated.
  • step S606 the source layer 281 and the drain layer 282 are respectively formed on the two amorphous silicon layers 273 and 274 on the interlayer dielectric layer 26 by using the fourth mask, and the source layer 281 and the drain layer are formed.
  • 282 is connected to the source doping region 231' and the drain doping region 232', respectively.
  • the source layer 281 is connected to the doped region 611 on the controllable resistive spacer layer 271 to be connected to the source doped region 231' through the controllable resistive spacer layer 271, and the drain layer 282 and the controllable resistor spacer layer Doped regions 612 on 272 are connected to connect to drain doped region 232' through controllable resist spacer layer 272.
  • controllable resistive spacer layers 271, 272 are heavily doped, whereby in the finally formed thin film transistor structure, for example, at the ohmic contact of the drain layer 282, lightly doped is formed. a drain doped region 232', a portion of the controllable resistive spacer layer 272 that is not ion doped, and a sandwich structure of the heavily doped doped region 612 in the controllable resistive spacer layer 272, thereby further improving formation Leakage of the thin film transistor.
  • FIG. 7 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • the array substrate of the present embodiment is obtained by using the method for manufacturing an array substrate of the embodiment shown in FIG.
  • the array substrate includes a low temperature polysilicon active layer 23, a gate layer 25, an interlayer dielectric layer 26, a source layer 281, and a drain layer 282 formed on the substrate 21, and further includes a buffer layer 22 and a gate insulating layer 24. .
  • the low temperature polysilicon active layer 23 is formed on the buffer layer 22, and the gate insulating layer 24 is formed on the low temperature polysilicon active layer 23.
  • the gate layer 25 is formed on the gate insulating layer 24, the interlayer dielectric layer 26 is formed on the gate layer 25, and the source layer 281 and the drain layer 282 are formed on the interlayer dielectric layer 26.
  • Two via holes 261 and 262 are disposed on the interlayer dielectric layer 26, and via holes are formed in the gate insulating layer 24 corresponding to the positions of the two via holes 261 and 262.
  • the low temperature polysilicon active layer 23 includes a source doped region 231 and a drain doped region 232.
  • the source layer 281 is sequentially connected to the source doping region 231 through the via hole 261 on the interlayer dielectric layer 26 and the via hole on the gate insulating layer 24, and the drain layer 282 sequentially passes through the interlayer dielectric layer 26.
  • the upper via 262 and the via on the gate insulating layer 24 are connected to the drain doping region 232.
  • the gate layer 25, the source layer 281, and the drain layer 282 are respectively formed as a gate, a source, and a drain of the thin film transistor.
  • a controllable resistor spacer layer 271 is disposed between the source layer 281 and the source doping region 231.
  • the controllable resistance spacer layer 271 forms a blocking effect on the current flowing when the gate layer 25 is not applied with the turn-on signal, and forms a conduction effect on the current flowing when the turn-on signal is applied to the gate layer 25.
  • the controllable resistor spacer layer 271 when the turn-on signal is not applied to the gate layer 25, the circuit that flows through can be blocked, whereby the leakage of the formed thin film transistor can be effectively reduced.
  • the drain layer 282 and Controllable resist spacer layers 272, 273, 274 are also disposed between the drain doped regions 232, between the source layer 281 and the interlayer dielectric layer 26, between the drain layer 282 and the interlayer dielectric layer 26, respectively. Thereby, leakage of the formed thin film transistor can be further reduced.
  • controllable resistor spacer layers 271-274 are all amorphous silicon layers, and the concentration of ions doped by the source doping region 231 and the drain doping region 232 is greater than or equal to a first predetermined value. That is, the source doping region 231 and the drain doping region 232 are heavily doped regions, and the doped ions are boron ions, and of course, may be phosphorus ions or arsenic ions.
  • a first insulating layer 29, a first transparent electrode layer 31, a second insulating layer 32, and a second transparent electrode layer 33 are sequentially formed on the source layer 281 and the drain layer 282.
  • the second transparent electrode layer 33 is connected to the drain layer 282.
  • the first reticle, the second reticle, the third reticle, the fourth reticle, the fifth reticle, the sixth reticle, the seventh reticle, and the eighth The photomask respectively forms a low temperature polysilicon active layer 23, a gate layer 25, an interlayer dielectric layer 26, a source layer 281/drain layer 282, a first insulating layer 29, a first transparent electrode layer 31, and a second insulating layer. 32 and a second transparent electrode layer 33.
  • the interlayer dielectric layer 26 can be used as a mask for ion implantation, thereby eliminating the need for additional Photomask.
  • the array substrate of the present embodiment can complete the fabrication of the thin film device by only eight masks, which is advantageous for reducing the number of the masks, and the formed thin film transistor can reduce leakage by providing a controllable resistor spacer layer. Improve device performance.
  • the source doping region 231 ′ and the drain doping region 232 ′ are lightly doped regions.
  • LDD structure that is, the concentration of ions doped in the source doping region 231' and the drain doping region 232' is less, lower than the first predetermined value, and the doped ions may be boron ions.
  • the doping concentration of the side of the controllable resistive spacer layer 271 located between the source layer 281 and the source doped region 231' near the source layer 281 is greater than or equal to a second predetermined value.
  • the ions, i.e., the controllable resistive spacer layer 271 between the source layer 281 and the source doped region 231' have doped regions 611.
  • the one of the controllable resistive spacer layer 272 located between the drain layer 282 and the drain doping region 232' adjacent to the drain layer 281 is doped with a concentration greater than or equal to a second predetermined value, that is, located in the drain layer 282.
  • the controllable resistive spacer layer 272 between the drain doped region 232' has a doped region 612.
  • the source layer 281 is connected to the doped region 611 on the controllable resistive spacer layer 271 to be connected to the source doped region 231' through the controllable resistive spacer layer 271, and the drain layer 282 and the controllable resistive spacer layer 272.
  • Doped regions 612 are connected to connect to drain doped region 232' through a controllable resist spacer layer 272.
  • the second predetermined value is a boundary value of the ion concentration that enables the doped regions 611 and 612 to be heavily doped regions, and the doped regions 611 and 612 on the control resistive spacer layers 271 and 272 are heavily doped regions.
  • controllable resistive spacer layers 271, 272 are partially doped, that is, the depth of the doped ions in the controllable resistive spacer layers 271, 272 is smaller than the thickness of the controllable resistive spacer layers 271, 272, the doped region 611, 612 does not completely penetrate the controllable resist spacer layers 271, 272.
  • a first insulating layer, a first transparent electrode layer, a second insulating layer, and a second transparent electrode layer are sequentially formed.
  • a first insulating layer, a first transparent electrode layer, a second insulating layer, and a second transparent electrode layer are sequentially formed.
  • the leakage of the thin film transistor device can be further reduced by the controllable resistor spacer layer of the present embodiment.
  • the array substrate of the present invention is suitable for liquid crystal display panels, OLED display panels, and other substrates having thin film transistor devices.
  • the liquid crystal display panel includes an array substrate 1001, a color filter substrate 1002, and a liquid crystal layer 1003 between the array substrate 1001 and the color filter substrate 1002.
  • the array substrate 1001 is the array substrate described in any of the above embodiments, or the array substrate manufactured by using the method for manufacturing an array substrate according to any of the above embodiments.

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Abstract

一种液晶显示面板、阵列基板（1001）及其制造方法，制造方法包括：在低温多晶硅有源层（23）的源极掺杂区（231）和漏极掺杂区（232）中的至少其中一个掺杂区（231，232）上形成可控电阻间隔层（271），可控电阻间隔层（271）在栅极层（25）未施加开启信号时对流经的电流形成隔断作用，而在栅极层（25）施加开启信号时对流经的电流形成导通作用，使形成有可控电阻间隔层（271）的接触区通过可控电阻间隔层（271）与对应的源极层（281）或漏极层（282）相连。因此，能够减少薄膜晶体管器件的漏电。

Description

液晶显示面板、阵列基板及其制造方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种液晶显示面板、阵列基板及其制造方法。
【背景技术】
低温多晶硅（Low Temperature Poly-Silicon，LTPS）技术是平板显示器领域中的又一新技术，继非晶硅（a-Si）之后的下一代技术。低温多晶硅型的显示面板具有电子迁移率更快、薄膜电路面积更小、分辨率更高、功耗更低、稳定性更高等优点。
低温多晶硅型显示面板即是指薄膜晶体管TFT的有源层采用低温多晶硅制成的显示面板。低温多晶硅薄膜晶体管的制备工艺温度通常低于600℃，可适用于普通的玻璃衬底，通常采用准分子激光退火方式激光晶化的方式，利用一定能量的准分子激光对非晶硅进行激光辐射使非晶硅晶化成为多晶硅。
对于低温多晶硅薄膜晶体管而言，漏电是影响薄膜晶体管性能以及显示面板的显示效果的重要因素，若薄膜晶体管发生漏电，容易产生对比度降低、产生闪烁和串扰等问题。因此，如何有效减小低温多晶硅薄膜晶体管的漏电成为亟需解决的技术问题。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示面板、阵列基板及其制造方法，能够有效减少薄膜晶体管的漏电。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制造方法，包括：在基板上形成缓冲层；利用第一光罩在所述缓冲层上形成低温多晶硅有源层；在所述低温多晶硅有源层上形成栅极绝缘层；利用第二光罩在所述栅极绝缘层上形成栅极层；利用第三光罩在所述栅极层上形成层间介电层，所形成的所述层间介电层上形成有两个导通孔；除去所述栅极绝缘层中分别对应所述层间介电层的两个导通孔的部分，以暴露两部分低温多晶硅有源层；对暴露的所述两部分低温多晶硅有源层进行离子掺杂处理，以分别形成所述低温多晶硅有源层的源极掺杂区和漏极掺杂区；在所述源极掺杂区和所述漏极掺杂区上分别形成可控电阻间隔层，并且利用第四光罩在所述层间介电层上形成分别与源极层和漏极层对应的两个可控电阻间隔层；利用所述第四光罩在所述层间介电层上的两个可控电阻间隔层上分别形成源极层和漏极层，并使所述源极层和漏极层分别通过所述层间介电层上的两个导通孔与所述源极掺杂区和所述漏极掺杂区相连，其中所述源极层和所述漏极层分别通过源极掺杂区和漏极掺杂区上的可控电阻间隔层与所述源极掺杂区和漏极掺杂区相连；利用第五光罩在所述源极层和漏极层上形成第一绝缘层，并暴露部分所述漏极层；利用第六光罩在所述第一绝缘层上形成第一透明电极层，所述第一透明电极层不覆盖暴露的所述漏极层，且与暴露的所述漏极层也不相连；利用第七光罩在所述第一透明电极层上形成第二绝缘层，所述第二绝缘层不覆盖暴露的所述漏极层，且与暴露的所述漏极层也不相连；利用第八光罩在所述第二绝缘层上形成第二透明电极层，并使所述第二透明电极层与暴露的所述漏极层相连；其中，所述可控电阻间隔层在所述栅极层未施加开启信号时对流经的电流形成隔断作用，而在所述栅极层施加开启信号时对流经的电流形成导通作用。
其中，所述可控电阻间隔层为非晶硅层；所述对暴露的所述两部分低温多晶硅有源层进行离子掺杂处理的步骤包括：对暴露的所述两部分低温多晶硅有源层进行离子注入，注入的离子的浓度大于或等于第一预定值，注入的离子为硼离子、磷离子或砷离子。
其中，所述可控电阻间隔层为非晶硅层；所述对暴露的所述两部分低温多晶硅有源层进行离子掺杂处理的步骤包括：对暴露的所述两部分低温多晶硅有源层进行离子注入，注入的离子的浓度小于第一预定值，注入的离子为硼离子、磷离子或砷离子；所述在所述源极掺杂区和所述漏极掺杂区上分别形成可控电阻间隔层的步骤之后，包括：对在所述源极掺杂区和所述漏极掺杂区上的可控电阻间隔层进行离子注入，注入的离子的浓度大于或等于第二预定值。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括形成于基板上的低温多晶硅有源层、栅极层、层间介电层、源极层以及漏极层，所述层间介电层位于所述低温多晶硅有源层上，所述源极层和所述漏极层位于所述层间介电层上，所述栅极层位于所述低温多晶硅有源层之下或位于所述低温多晶硅有源层和所述层间介电层之间；所述层间介质层上设置有两个导通孔，所述低温多晶硅有源层包括源极掺杂区和漏极掺杂区，所述源极层和所述漏极层分别通过所述层间介质层上的两个导通孔与所述源极掺杂区和漏极掺杂区相连，且至少在所述源极层和所述源极掺杂区之间或所述漏极层和所述漏极掺杂区之间设置有可控电阻间隔层，所述可控电阻间隔层在所述栅极层未施加开启信号时对流经的电流形成隔断作用，而在所述栅极层施加开启信号时对流经的电流形成导通作用。
其中，所述源极层和所述源极掺杂区之间、所述漏极层和所述漏极掺杂区之间、所述源极层和所述层间介电层之间、所述漏极层和所述层间介电层之间分别设置有所述可控电阻间隔层。
其中，所述可控电阻间隔层为非晶硅层，所述源极掺杂区和所述漏极掺杂区所掺杂的离子的浓度大于或等于第一预定值，所述离子为硼离子、磷离子或砷离子。
其中，所述可控电阻间隔层为非晶硅层，所述源极掺杂区和所述漏极掺杂区所掺杂的离子的浓度小于第一预定值，所掺杂的所述离子为硼离子、磷离子或砷离子；所述源极层和所述源极掺杂区之间的可控电阻间隔层中靠近所述源极层的一侧掺杂有浓度大于或等于第二预定值的离子，所述漏极层和所述漏极掺杂区之间的可控电阻间隔层中靠近所述漏极层的一侧掺杂有浓度大于或等于第二预定值的离子，所述浓度大于或等于第二预定值的离子为硼离子、磷离子或砷离子。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括阵列基板、彩膜基板以及位于阵列基板和彩膜基板之间的液晶层，所述阵列基板包括形成于基板上的低温多晶硅有源层、栅极层、层间介电层、源极层以及漏极层，所述层间介电层位于所述低温多晶硅有源层上，所述源极层和所述漏极层位于所述层间介电层上，所述栅极层位于所述低温多晶硅有源层之下或位于所述低温多晶硅有源层和所述层间介电层之间；所述层间介质层上设置有两个导通孔，所述低温多晶硅有源层包括源极掺杂区和漏极掺杂区，所述源极层和所述漏极层分别通过所述层间介质层上的两个导通孔与所述源极掺杂区和漏极掺杂区相连，且至少在所述源极层和所述源极掺杂区之间或所述漏极层和所述漏极掺杂区之间设置有可控电阻间隔层，所述可控电阻间隔层在所述栅极层未施加开启信号时对流经的电流形成隔断作用，而在所述栅极层施加开启信号时对流经的电流形成导通作用。
其中，所述源极层和所述源极掺杂区之间、所述漏极层和所述漏极掺杂区之间、所述源极层和所述层间介电层之间、所述漏极层和所述层间介电层之间分别设置有所述可控电阻间隔层。
其中，所述可控电阻间隔层为非晶硅层，所述源极掺杂区和所述漏极掺杂区所掺杂的离子的浓度大于或等于第一预定值，所述离子为硼离子、磷离子或砷离子。
其中，所述可控电阻间隔层为非晶硅层，所述源极掺杂区和所述漏极掺杂区所掺杂的离子的浓度小于第一预定值，所掺杂的所述离子为硼离子、磷离子或砷离子；所述源极层和所述源极掺杂区之间的可控电阻间隔层中靠近所述源极层的一侧掺杂有浓度大于或等于第二预定值的离子，所述漏极层和所述漏极掺杂区之间的可控电阻间隔层中靠近所述漏极层的一侧掺杂有浓度大于或等于第二预定值的离子，所述浓度大于或等于第二预定值的离子为硼离子、磷离子或砷离子。
本发明的有益效果是：区别于现有技术的情况，本发明阵列基板的制造方法中，通过至少在低温多晶硅层的源极掺杂区或所述漏极掺杂区上形成可控电阻间隔层，使形成有可控电阻间隔层的掺杂区通过可控电阻间隔层与对应的源极层或漏极层相连，而可控电阻间隔层在栅极层未施加开启信号时对流经的电流起隔断作用，由此可以有效的阻挡低温多晶硅有源层的载流子，从而能够减少薄膜器件的漏电。
【附图说明】
图1是本发明阵列基板的制造方法一实施方式的流程图；
图2是本发明阵列基板的制造方法一实施方式的结构示意图；
图3是本发明阵列基板的制造方法另一实施方式的结构示意图；
图4是本发明阵列基板的制造方法一实施方式中，在利用第三光罩在层间介电层上的两个可控电阻间隔层上分别形成源极层和漏极层，并使源极层和漏极层分别与源极掺杂区和漏极掺杂区相连的步骤之后的流程图；
图5是本发明阵列基板的制造方法一实施方式中，在利用第三光罩在层间介电层上的两个可控电阻间隔层上分别形成源极层和漏极层，并使源极层和漏极层分别与源极掺杂区和漏极掺杂区相连步骤之后的结构示意图；
图6是本发明阵列基板的制造方法另一实施方式的结构示意图；
图7是本发明阵列基板一实施方式的结构示意图；
图8是本发明阵列基板另一实施方式的结构示意图；
图9是本发明阵列基板又一实施方式的结构示意图；
图10是本发明液晶显示面板一实施方式的结构示意图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细说明。
参阅图1和图2，图1是本发明阵列基板的制造方法一具体实施方式的流程图，图2是本发明阵列基板的制造方法的结构示意图，所述制造方法具体包括如下步骤：
步骤S101：利用第一光罩在基板上形成低温多晶硅有源层，其中，在形成低温多晶硅有源层之前或之后再利用第二光罩形成栅极层。
结合图2所示的步骤S201，基板可以是玻璃基板。在本实施方式中，进一步地，在形成低温多晶硅有源层23之前，先在基板21上形成一层缓冲层22，缓冲层22起到缓冲作用，以避免后续的蚀刻过程对基板21造成损伤。形成缓冲层22后，在缓冲层22上形成低温多晶硅有源层23。
其中，形成低温多晶硅有源层的具体过程可以如下：在缓冲层22上沉积一层非晶硅层，然后在非晶硅层上形成光致抗蚀剂层，再利用具有低温多晶硅有源层的图案的第一光罩对光致抗蚀剂层进行光照，然后利用显影液对光照后的光致抗蚀剂层进行处理，以在光致抗蚀剂层上形成低温多晶硅有源层的图案，然后对没有被光致抗蚀剂层覆盖的非晶硅层进行蚀刻，以在非晶硅层上形成低温多晶硅有源层的图案，并去除非晶硅层上的光致抗蚀剂层，从而得到具有低温多晶硅有源层图案的非晶硅层。最后采用激光退火方式对非晶硅层进行激光辐射，从而形成低温多晶硅有源层23。
本实施方式所形成的薄膜晶体管为顶栅型薄膜晶体管。如图2的步骤S202所示，在形成低温多晶硅有源层23之后，在低温多晶硅有源层23上形成栅极绝缘层24。形成栅极绝缘层24后，利用第二光罩在栅极绝缘层24上形成栅极层25。
步骤S102：利用第三光罩在低温多晶硅有源层上形成层间介电层，所形成的层间介电层上形成有两个导通孔，以暴露两部分低温多晶硅有源层。
具体地，如图2所示的步骤S203，利用第三光罩在栅极层25上形成层间介电层（inter layer dielectric，ILD）26，所形成的层间介电层26上形成有两个导通孔261和262。然后，通过蚀刻等方式除去栅极绝缘层24中对应层间介电层26的两个导通孔261、262的部分，从而在栅极绝缘层24上也相应形成两个导通孔，以暴露两部分低温多晶硅有源层23。
步骤S103：对暴露的两部分低温多晶硅有源层进行离子掺杂处理，以分别形成低温多晶硅有源层的源极掺杂区和漏极掺杂区。
如图2所示的步骤S204，对暴露的两部分低温多晶硅有源层23进行离子掺杂处理，以分别形成低温多晶硅有源层23的源极掺杂区231和漏极掺杂区232。
步骤S104：至少在源极掺杂区或漏极掺杂区上形成可控电阻间隔层，其中，可控电阻间隔层在栅极层未施加开启信号时对流经的电流形成隔断作用，而在栅极层施加开启信号时对流经的电流形成导通作用。
其中，可以在源极掺杂区或漏极掺杂区上形成一层可控电阻间隔层，或者也可以在源极掺杂区和漏极掺杂区上均分别形成一层可控电阻间隔层。
如图2所示的步骤S205，本实施方式中，在源极掺杂区231上形成一层可控电阻间隔层271。其中，可控电阻间隔层271在栅极层25未施加开启信号时对流经的电流形成隔断作用，而在栅极层25施加开启信号时对流经的电流形成导通作用。
步骤S105：利用第四光罩在层间介电层上形成源极层和漏极层，并使源极层和漏极层分别通过层间介电层上的两个导通孔与源极掺杂区和漏极掺杂区相连，其中形成有可控电阻间隔层的掺杂区通过可控电阻间隔层与对应的源极层或漏极层相连。
如图2所示的步骤S206，利用第四光罩在层间介电层26上形成源极层281和漏极层282，并且源极层281依次通过层间介电层26上的导通孔261和栅极绝缘层24上的导通孔与低温多晶硅层23的源极掺杂区231相连，漏极层282依次通过层间绝缘层26上的导通孔262和栅极绝缘层24上的导通孔与低温多晶硅层23的漏极掺杂区232相连。其中，在源极掺杂区231上由于形成有可控电阻间隔层271，因此源极层281通过可控电阻间隔层271与源极掺杂区231相连。
其中，所形成的栅极层25、源极层281以及漏极层282分别作为阵列基板上的薄膜晶体管的栅极、源极和漏极。
本实施方式中，通过在源极层281和低温多晶硅有源层23的源极掺杂区231之间设置可控电阻间隔层271，该可控电阻间隔层271在栅极层25未施加开启信号时对流经的电流形成隔断作用，由此可达到对低温多晶硅有源层271载流子的阻隔效应，从而可有效减少所形成的薄膜晶体管的漏电。而该可控电阻间隔层271在栅极层25施加开启信号时对流经的电流形成导通作用，由此可使得源极层281和漏极层282导通。
参阅图3，图3是本发明阵列基板的制造方法另一实施方式的结构示意图，其中，图中相同标号的元件作用相同。如图3所示，在本发明阵列基板的制造方法的实施方式中，步骤S301中形成低温多晶硅有源层23；步骤S302中形成栅极层25，栅极层25和低温多晶硅有源层23之间间隔栅极绝缘层24；步骤S303中形成层间介电层26，并暴露两部分低温多晶硅有源层23；步骤S304中对暴露的低温多晶硅有源层23进行离子掺杂处理，以形成低温多晶硅有源层的源极掺杂区231和漏极掺杂区232。
其中，本实施方式中，对暴露的低温多晶硅有源层23进行离子掺杂处理的具体步骤为：对暴露的低温多晶硅有源层23进行离子注入。即以离子注入的方式对暴露的低温多晶硅有源层23进行掺杂，并且在注入过程中可以使用层间介电层26作为掩膜进行离子注入，由此不需要增加额外的光罩即可完成离子掺杂。其中，注入的离子的浓度大于或等于第一预定值，即采用高浓度离子进行掺杂，以使得源极掺杂区和漏极掺杂区为重掺杂区（P+）。可以理解的是，第一预定值是能够使得源极掺杂区和漏极掺杂区为重掺杂区的离子浓度的边界值，可以根据实际需要进行选择。
其中，本实施方式注入的离子为硼离子，当然还可以磷离子或砷离子等。此外，可以控制所注入的离子的用量以及所使用的注入功率来调整注入的离子在低温多晶硅有源层23中的穿透深度。
本实施方式中，至少在源极掺杂区或漏极掺杂区上形成可控电阻间隔层的步骤包括：在源极掺杂区和漏极掺杂区上均形成可控电阻间隔层，并且利用第四光罩在层间介电层上形成分别与源极层和漏极层对应的两个可控电阻间隔层。
如图3所示的步骤S305，除了在源极掺杂区231上形成可控电阻间隔层271外，还在漏极掺杂区232、层间介电层26上分别形成可控电阻间隔层272、273、274。其中，可控电阻间隔层273和274分别与源极层281和漏极层282相对应。此外，利用第四光罩来形成层间介电层26上的可控电阻间隔层273、274，与形成源极层281、282的光罩相同。
如图3所示的步骤S306，利用第四光罩在层间介电层上形成源极层和漏极层的步骤具体包括：利用第四光罩在层间介电层26上的两个可控电阻间隔层273、274上分别形成源极层281和漏极层282，源极层281和漏极层282分别通过可控电阻间隔层271、273与源极掺杂区231和漏极掺杂区232相连。
由此，在源极层281和源极掺杂区231之间、源极层281和层间介电层26之间、漏极层282和漏极掺杂区232之间以及漏极层282和层间介电层26之间均分别形成有可控电阻间隔层，从而可以进一步减少所形成的薄膜晶体管的漏电。并且，本实施方式中，层间介电层26上的可控电阻间隔层273、274和源极层281、282均使用同一光罩形成，可减少光罩的数量，且有利于简化工艺。
其中，在实施方式中，可控电阻间隔层为非晶硅层（a-si），通过非晶硅层对源极层281和漏极层282的欧姆接触进行修正，能够有效减少漏电。
进一步地，参阅图4和图5，并结合图3，在本实施方式中，在图3所示的步骤S306之后，即在利用第四光罩在层间介电层上的两个可控电阻间隔层上分别形成源极层和漏极层，并使源极层和漏极层分别与源极掺杂区和漏极掺杂区相连的步骤之后，如图4所示，还包括如下步骤：
步骤S401：利用第五光罩在源极层和漏极层上形成第一绝缘层，并暴露部分漏极层。
如图5所示的步骤S501，利用第五光罩在源极层281和漏极层282上形成第一绝缘层29，并暴露部分漏极层282。其中，图5所示的实施例中，第一绝缘层29形成于源极层281以及暴露的层间介电层26上，漏极层282上没有形成第一绝缘层29，以使得漏极层282暴露。在其他实施例中，也可以在漏极层282上形成第一绝缘层29，只要保证至少部分漏极层282暴露即可，以便于后续漏极层282与阵列基板上的像素电极连接。
步骤S402：利用第六光罩在第一绝缘层上形成第一透明电极层，第一透明电极层不覆盖暴露的漏极层，且与暴露的漏极层也不相连。
如图5所示的步骤S502，利用第六光罩在第一绝缘层29上形成第一透明电极层31，第一透明电极层31可以使用ITO材料形成。其中，在形成第一透明电极层31时，使第一透明电极层31不覆盖暴露的漏极层282，也不与漏极层282相连。
第一透明电极层31为阵列基板的公共电极层。
步骤S403：利用第七光罩在第一透明电极层上形成第二绝缘层，第二绝缘层不覆盖暴露的漏极层，且与暴露的漏极层也不相连。
如图5所示的步骤S503，利用第七光罩在第一透明电极层31上形成第二绝缘层32，并使第二绝缘层32不覆盖暴露的源极层282，以使得至少部分漏极层282暴露。
步骤S404：利用第八光罩在第二绝缘层上形成第二透明电极层，并使第二透明电极层与暴露的漏极层相连。
如图5所示的步骤S504，利用第八光罩在第二绝缘层32上形成第二透明电极层33，并使第二透明电极层33与暴露的漏极层282相连。其中，第二透明电极层33为阵列基板的像素电极层，由此实现像素电极层和漏极层282的连接，以实现薄膜晶体管对像素电极层的驱动。
本实施方式中，从薄膜晶体管到像素电极层的形成，仅需要八道光罩即可完成，与现有的CMOS工艺相比，少了3-4道光罩，有利于减少光罩数量，同时能够简化工艺流程和提高器件的性能。
在其他实施方式中，栅极层也可以是在低温多晶硅有源层形成之前形成，即先在基板上形成栅极层，然后在栅极层上形成栅极绝缘层，之后在栅极绝缘层上形成低温多晶硅有源层，再在低温多晶硅有源层上形成层间介电层，即在其他实施方式中，所形成的薄膜晶体管也可以是底栅型薄膜晶体管。
此外，本发明实施方式中，可控电阻间隔层还可以是其他的半导体层，例如可以是锗元素的半导体层，或者还可以是化合物半导体层，例如砷化镓、磷化镓等半导体层。
参阅图6，图6是本发明阵列基板的制造方法的又一实施方式的结构示意图，其中，图中相同标号的元件作用相同。与上述实施方式主要不同的是，本实施方式中，对位于源极掺杂区231和漏极掺杂区232上的可控电阻间隔层进行离子掺杂处理。
具体地，本实施方式中，如图6所示，在步骤S601中，在基板21上形成缓冲层22，然后利用第一光罩在缓冲层22上形成低温多晶硅有源层23。
步骤S602中，在低温多晶硅有源层23上形成栅极绝缘层24，然后利用第二光罩在栅极绝缘层24上形成栅极层25。
步骤S603中，在栅极层25上形成层间介电层26，所形成的层间介电层26上形成有两个导通孔261和262，并除去栅极绝缘层24中对应两个导通孔261、262的部分，以暴露两部分低温多晶硅有源层23。
步骤S604中，对暴露的两部分低温多晶硅有源层23进行离子掺杂处理，以分别形成低温多晶硅有源层23的源极掺杂区231’和漏极掺杂区232’。
其中，通过离子注入的方式对暴露的低温多晶硅有源层23进行离子掺杂。本实施方式中，对低温多晶硅有源层23所注入的离子的浓度小于第一预定值，即采用低浓度离子进行掺杂，以使得源极掺杂区231’和漏极掺杂区232’为轻掺杂区（P-），即在低温多晶硅有源层23上形成LDD（Lightly Doped Drain，轻掺杂漏区）结构。所注入的离子为硼离子，当然也可以是磷离子或砷离子。
步骤S605中，在源极掺杂区231’和漏极掺杂区232’上分别形成可控电阻间隔层271、272，并且利用第四光罩在层间介电层26上分别形成与源极层281和漏极层282对应的可控电阻间隔层273、274。其中，可控电阻间隔层271~274为非晶硅层。
进一步地，在本实施方式中，在源极掺杂区231’和漏极掺杂区232’上分别形成可控电阻间隔层271、272之后，对源极掺杂区231’和漏极掺杂区232’上的可控电阻间隔层271、272进行离子注入，以对可控电阻间隔层271、272进行离子掺杂，从而在可控电阻间隔层271、272上分别形成掺杂区611、612。
其中，对可控电阻间隔层271和272进行离子注入时，注入的离子的浓度大于或等于第二预定值，即可控电阻间隔层271、272上的掺杂区611、612为重掺杂区，所注入的离子为硼离子，当然还可以是磷离子或砷离子等。第二预定值是能够使得掺杂区611、612为重掺杂区的离子浓度的边界值。
此外，可控电阻间隔层271、272为部分掺杂，即所注入的离子在可控电阻间隔层271、272中的深度小于可控电阻间隔层271、272的厚度，掺杂区611、612并没有完全穿透可控电阻间隔层271、272。
步骤S606中，利用第四光罩在层间介电层26上的两个非晶硅层273、274上分别形成源极层281和漏极层282，并使源极层281和漏极层282分别与源极掺杂区231’和漏极掺杂区232’相连。具体地，源极层281与可控电阻间隔层271上的掺杂区611相连，以通过可控电阻间隔层271与源极掺杂区231’相连，漏极层282与可控电阻间隔层272上的掺杂区612相连，以通过可控电阻间隔层272与漏极掺杂区232’相连。
本实施方式中，通过对可控电阻间隔层271、272进行重掺杂处理，由此在最终形成的薄膜晶体管结构中，例如在漏极层282的欧姆接触处，形成的是轻掺杂的漏极掺杂区232’、可控电阻间隔层272中未被离子掺杂的部分、可控电阻间隔层272中重掺杂的掺杂区612的三明治结构，由此，可以进一步改善所形成的薄膜晶体管的漏电。
参阅图7，图7是本发明阵列基板的一实施方式的结构示意图，本实施方式的阵列基板为采用图1所示实施例的阵列基板的制造方法而得到。阵列基板包括形成于基板21上的低温多晶硅有源层23、栅极层25、层间介电层26、源极层281和漏极层282，此外还包括缓冲层22和栅极绝缘层24。
其中，低温多晶硅有源层23形成于缓冲层22上，栅极绝缘层24形成于低温多晶硅有源层23上。栅极层25形成于栅极绝缘层24上，层间介电层26形成于栅极层25上，源极层281和漏极层282形成于层间介电层26上。层间介电层26上设置有两个导通孔261和262，栅极绝缘层24中对应于两个导通孔261、262的位置也形成有导通孔。
其中，低温多晶硅有源层23包括源极掺杂区231和漏极掺杂区232。源极层281依次通过层间介电层26上的导通孔261以及栅极绝缘层24上的导通孔与源极掺杂区231相连，漏极层282依次通过层间介电层26上的导通孔262以及栅极绝缘层24上的导通孔与漏极掺杂区232相连。其中，所形成的栅极层25、源极层281和漏极层282分别为薄膜晶体管的栅极、源极和漏极。
在本实施方式中，源极层281和源极掺杂区231之间设置有可控电阻间隔层271。可控电阻间隔层271在栅极层25未施加开启信号时对流经的电流形成隔断作用，而在栅极层25施加开启信号时对流经的电流形成导通作用。由此，通过设置可控电阻间隔层271，在栅极层25未施加开启信号时，可以隔断流经的电路，由此可以有效减少所形成的薄膜晶体管的漏电。
参阅图8，在本发明阵列基板的另一实施方式中，进一步地，除了在源极层281和源极掺杂区231之间设置有可控电阻间隔层271外，在漏极层282和漏极掺杂区232之间、源极层281和层间介电层26之间、漏极层282和层间介电层26之间也分别设置有可控电阻间隔层272、273、274，由此可进一步减少所形成的薄膜晶体管的漏电。
其中，在本实施方式中，可控电阻间隔层271~274均为非晶硅层，源极掺杂区231和漏极掺杂区232所掺杂的离子的浓度大于或等于第一预定值，即源极掺杂区231和漏极掺杂区232为重掺杂区，所掺杂的离子为硼离子，当然还可以是磷离子或砷离子。
此外，在源极层281和漏极层282上还依次形成有第一绝缘层29、第一透明电极层31、第二绝缘层32以及第二透明电极层33。其中，第二透明电极层33与漏极层282相连。
其中，根据本实施方式的阵列基板，可以分别使用第一光罩、第二光罩、第三光罩、第四光罩、第五光罩、第六光罩、第七光罩以及第八光罩分别形成低温多晶硅有源层23、栅极层25、层间介电层26、源极层281/漏极层282、第一绝缘层29、第一透明电极层31、第二绝缘层32以及第二透明电极层33。在对低温多晶硅有源层23进行离子掺杂以形成源极掺杂区231和漏极掺杂区232时，可以利用层间介电层26作为掩膜进行离子注入，由此不需要增加额外的光罩。
因此，本实施方式的阵列基板，仅需八道光罩即可完成薄膜器件的制造，有利于减少光罩的数量，同时所形成的薄膜晶体管由于设置有可控电阻间隔层，因此能够减少漏电，提高器件性能。
参阅图9，在本发明阵列基板的又一实施方式中，与上述实施方式的主要不同在于，本实施方式中，源极掺杂区231’和漏极掺杂区232’为轻掺杂区（LDD结构），即源极掺杂区231’和漏极掺杂区232’中所掺杂的离子浓度较少，低于第一预定值，所掺杂的离子可以是硼离子。
此外，如图9所示，位于源极层281和源极掺杂区231’之间的可控电阻间隔层271中靠近源极层281的一侧掺杂浓度大于或等于第二预定值的离子，即位于源极层281和源极掺杂区231’之间的可控电阻间隔层271具有掺杂区611。位于漏极层282和漏极掺杂区232’之间的可控电阻间隔层272中靠近漏极层281的一侧掺杂浓度大于或等于第二预定值的离子，即位于漏极层282和漏极掺杂区232’之间的可控电阻间隔层272具有掺杂区612。源极层281与可控电阻间隔层271上的掺杂区611相连，以通过可控电阻间隔层271与源极掺杂区231’相连，漏极层282与可控电阻间隔层272上的掺杂区612相连，以通过可控电阻间隔层272与漏极掺杂区232’相连。
其中，第二预定值是能够使得掺杂区611、612为重掺杂区的离子浓度的边界值，即可控电阻间隔层271、272上的掺杂区611、612为重掺杂区。
其中，可控电阻间隔层271、272为部分掺杂，即所掺杂的离子在可控电阻间隔层271、272中的深度小于可控电阻间隔层271、272的厚度，掺杂区611、612并没有完全穿透可控电阻间隔层271、272。
在形成源极层281和漏极层282后，还依次形成有第一绝缘层、第一透明电极层、第二绝缘层以及第二透明电极层，具体的形成过程可参考图5所示的步骤进行，在此不进行一一赘述。
通过本实施方式的可控电阻间隔层，能够进一步减少薄膜晶体管器件的漏电。
需要说明的是，本发明的阵列基板适用于液晶显示面板、OLED显示面板以及其他具有薄膜晶体管器件的基板。
参阅图10，在本发明液晶显示面板的一实施方式中，液晶显示面板包括阵列基板1001、彩膜基板1002以及位于阵列基板1001和彩膜基板1002之间的液晶层1003。其中，阵列基板1001为前述任一实施方式所述的阵列基板，或者为使用前述任一实施方式所述的阵列基板的制造方法所制造得到的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种阵列基板的制造方法，其中，包括：
    在基板上形成缓冲层；
    利用第一光罩在所述缓冲层上形成低温多晶硅有源层；
    在所述低温多晶硅有源层上形成栅极绝缘层；
    利用第二光罩在所述栅极绝缘层上形成栅极层；
    利用第三光罩在所述栅极层上形成层间介电层，所形成的所述层间介电层上形成有两个导通孔；除去所述栅极绝缘层中分别对应所述层间介电层的两个导通孔的部分，以暴露两部分低温多晶硅有源层；
    对暴露的所述两部分低温多晶硅有源层进行离子掺杂处理，以分别形成所述低温多晶硅有源层的源极掺杂区和漏极掺杂区；
    在所述源极掺杂区和所述漏极掺杂区上分别形成可控电阻间隔层，并且利用第四光罩在所述层间介电层上形成分别与源极层和漏极层对应的两个可控电阻间隔层；
    利用所述第四光罩在所述层间介电层上的两个可控电阻间隔层上分别形成源极层和漏极层，并使所述源极层和漏极层分别通过所述层间介电层上的两个导通孔与所述源极掺杂区和所述漏极掺杂区相连，其中所述源极层和所述漏极层分别通过源极掺杂区和漏极掺杂区上的可控电阻间隔层与所述源极掺杂区和漏极掺杂区相连；
    利用第五光罩在所述源极层和漏极层上形成第一绝缘层，并暴露部分所述漏极层；
    利用第六光罩在所述第一绝缘层上形成第一透明电极层，所述第一透明电极层不覆盖暴露的所述漏极层，且与暴露的所述漏极层也不相连；
    利用第七光罩在所述第一透明电极层上形成第二绝缘层，所述第二绝缘层不覆盖暴露的所述漏极层，且与暴露的所述漏极层也不相连；
    利用第八光罩在所述第二绝缘层上形成第二透明电极层，并使所述第二透明电极层与暴露的所述漏极层相连；
    其中，所述可控电阻间隔层在所述栅极层未施加开启信号时对流经的电流形成隔断作用，而在所述栅极层施加开启信号时对流经的电流形成导通作用。
  2. 根据权利要求1所述的方法，其中，所述可控电阻间隔层为非晶硅层；
    所述对暴露的所述两部分低温多晶硅有源层进行离子掺杂处理的步骤包括：对暴露的所述两部分低温多晶硅有源层进行离子注入，注入的离子的浓度大于或等于第一预定值，注入的离子为硼离子、磷离子或砷离子。
  3. 根据权利要求1所述的方法，其中，所述可控电阻间隔层为非晶硅层；
    所述对暴露的所述两部分低温多晶硅有源层进行离子掺杂处理的步骤包括：对暴露的所述两部分低温多晶硅有源层进行离子注入，注入的离子的浓度小于第一预定值，注入的离子为硼离子、磷离子或砷离子；
    所述在所述源极掺杂区和所述漏极掺杂区上分别形成可控电阻间隔层的步骤之后，包括：对在所述源极掺杂区和所述漏极掺杂区上的可控电阻间隔层进行离子注入，注入的离子的浓度大于或等于第二预定值。
  4. 一种阵列基板，其中，包括形成于基板上的低温多晶硅有源层、栅极层、层间介电层、源极层以及漏极层，所述层间介电层位于所述低温多晶硅有源层上，所述源极层和所述漏极层位于所述层间介电层上，所述栅极层位于所述低温多晶硅有源层之下或位于所述低温多晶硅有源层和所述层间介电层之间；
    所述层间介质层上设置有两个导通孔，所述低温多晶硅有源层包括源极掺杂区和漏极掺杂区，所述源极层和所述漏极层分别通过所述层间介质层上的两个导通孔与所述源极掺杂区和漏极掺杂区相连，且至少在所述源极层和所述源极掺杂区之间或所述漏极层和所述漏极掺杂区之间设置有可控电阻间隔层，所述可控电阻间隔层在所述栅极层未施加开启信号时对流经的电流形成隔断作用，而在所述栅极层施加开启信号时对流经的电流形成导通作用。
  5. 根据权利要求4所述的阵列基板，其中，所述源极层和所述源极掺杂区之间、所述漏极层和所述漏极掺杂区之间、所述源极层和所述层间介电层之间、所述漏极层和所述层间介电层之间分别设置有所述可控电阻间隔层。
  6. 根据权利要求5所述的阵列基板，其中，所述可控电阻间隔层为非晶硅层，所述源极掺杂区和所述漏极掺杂区所掺杂的离子的浓度大于或等于第一预定值，所述离子为硼离子、磷离子或砷离子。
  7. 根据权利要求5所述的阵列基板，其中，所述可控电阻间隔层为非晶硅层，所述源极掺杂区和所述漏极掺杂区所掺杂的离子的浓度小于第一预定值，所掺杂的所述离子为硼离子、磷离子或砷离子；
    所述源极层和所述源极掺杂区之间的可控电阻间隔层中靠近所述源极层的一侧掺杂有浓度大于或等于第二预定值的离子，所述漏极层和所述漏极掺杂区之间的可控电阻间隔层中靠近所述漏极层的一侧掺杂有浓度大于或等于第二预定值的离子，所述浓度大于或等于第二预定值的离子为硼离子、磷离子或砷离子。
  8. 一种液晶显示面板，其中，包括阵列基板、彩膜基板以及位于阵列基板和彩膜基板之间的液晶层，所述阵列基板包括形成于基板上的低温多晶硅有源层、栅极层、层间介电层、源极层以及漏极层，所述层间介电层位于所述低温多晶硅有源层上，所述源极层和所述漏极层位于所述层间介电层上，所述栅极层位于所述低温多晶硅有源层之下或位于所述低温多晶硅有源层和所述层间介电层之间；
    所述层间介质层上设置有两个导通孔，所述低温多晶硅有源层包括源极掺杂区和漏极掺杂区，所述源极层和所述漏极层分别通过所述层间介质层上的两个导通孔与所述源极掺杂区和漏极掺杂区相连，且至少在所述源极层和所述源极掺杂区之间或所述漏极层和所述漏极掺杂区之间设置有可控电阻间隔层，所述可控电阻间隔层在所述栅极层未施加开启信号时对流经的电流形成隔断作用，而在所述栅极层施加开启信号时对流经的电流形成导通作用。
  9. 根据权利要求8所述的液晶显示面板，其中，所述源极层和所述源极掺杂区之间、所述漏极层和所述漏极掺杂区之间、所述源极层和所述层间介电层之间、所述漏极层和所述层间介电层之间分别设置有所述可控电阻间隔层。
  10. 根据权利要求9所述的液晶显示面板，其中，所述可控电阻间隔层为非晶硅层，所述源极掺杂区和所述漏极掺杂区所掺杂的离子的浓度大于或等于第一预定值，所述离子为硼离子、磷离子或砷离子。
  11. 根据权利要求9所述的液晶显示面板，其中，所述可控电阻间隔层为非晶硅层，所述源极掺杂区和所述漏极掺杂区所掺杂的离子的浓度小于第一预定值，所掺杂的所述离子为硼离子、磷离子或砷离子；
    所述源极层和所述源极掺杂区之间的可控电阻间隔层中靠近所述源极层的一侧掺杂有浓度大于或等于第二预定值的离子，所述漏极层和所述漏极掺杂区之间的可控电阻间隔层中靠近所述漏极层的一侧掺杂有浓度大于或等于第二预定值的离子，所述浓度大于或等于第二预定值的离子为硼离子、磷离子或砷离子。
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